October 2016 - coreboot - mail.coreboot.org

Re: [coreboot] Stops at 0xD2
by Riko Ho Oct. 25, 2016

Oct. 25, 2016

It needs parameter....what parameter do you think ? src/mainboard/intel/i946gz/romstage.c: In function 'mainboard_romstage_entry': src/mainboard/intel/i946gz/romstage.c:209:9: error: too few arguments to function 'ite_kill_watchdog' ite_kill_watchdog(); ^ In file included from src/mainboard/intel/i946gz/romstage.c:28:0: src/superio/ite/common/ite.h:32:6: note: declared here void ite_kill_watchdog(pnp_devfn_t dev); On Wed, Oct 26, 2016 at 9:58 AM, Kyösti Mälkki <kyosti.malkki(a)gmail.com> wrote: > The information missing from the mail is I requested to have that halt() > added after console_init(). > > Also at least it was previously reported system was in a periodic reset-loop > regardless of the halt() there, so sn active watchdog may be involved here. > Looks like other boards > with same superio use call ite_kill_watchdog(), I don't know what > it8718f_disable_reboot() does. > > There was also suggestion to dump superio ID register on POST display to > make sure LPC bus communication to superio works, but I did not hear back > from that experiment. > > Kyösti > > On Wed, Oct 26, 2016 at 4:36 AM, Riko Ho <antonius.riko(a)gmail.com> wrote: >> >> Everyone, >> >> I tried to initialize UART on IT8718F and it stopped at 0xD2... >> Here's the complete function, any clues ? >> >> Cheers >> =============== >> void mainboard_romstage_entry(unsigned long bist) >> { >> int s3resume = 0, boot_mode = 0; >> >> if (bist == 0) >> enable_lapic(); >> >> ich7_enable_lpc(); >> post_code(0xD1); >> /* Enable SuperIO PM */ >> //lpc47m15x_enable_serial(PME_DEV, 0x680); >> //lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ >> //enable_dev(SERIAL_DEV); >> //ite_conf_clkin();//needs a parameter, what is it ? >> >> /* >> 04:24:31 AM) idwer: 24 or 48 MHz? >> >> (04:25:18 AM) idwer: how do you find out? run superiotool when >> having booted with the vendor bios, and look at register >> CR23 >> */ >> //ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); >> ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); >> >> >> ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ >> //printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT BY RIKO HO...\n"); >> //it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); >> it8718f_disable_reboot(GPIO_DEV); >> /* Set up the console */ >> console_init(); >> post_code(0xD2); >> printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT ...\n"); >> halt(); >> post_code(0xD3); >> >> >> >> /* Halt if there was a built in self test failure */ >> report_bist_failure(bist); >> >> if (MCHBAR16(SSKPD) == 0xCAFE) { >> printk(BIOS_DEBUG, "soft reset detected.\n"); >> boot_mode = 1; >> } >> >> /* Perform some early chipset initialization required >> * before RAM initialization can work >> */ >> i945_early_initialization(); >> post_code(0xD4); >> s3resume = southbridge_detect_s3_resume(); >> >> /* Enable SPD ROMs and DDR-II DRAM */ >> enable_smbus(); >> >> #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 >> dump_spd_registers(); >> #endif >> >> sdram_initialize(s3resume ? 2 : boot_mode, NULL); >> >> /* Perform some initialization that must run before stage2 */ >> early_ich7_init(); >> >> /* This should probably go away. Until now it is required >> * and mainboard specific >> */ >> rcba_config(); >> >> /* Chipset Errata! */ >> fixup_i945_errata(); >> >> /* Initialize the internal PCIe links before we go into stage2 */ >> i945_late_initialization(s3resume); >> } >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot > >

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Re: [coreboot] Stops at 0xD2
by Riko Ho Oct. 25, 2016

Oct. 25, 2016

Thanks for the reply.... Let me step it : 1. I got this when I compile it : build/auto.conf:1974:warning: override: reassigning to symbol CONSOLE_SERIAL_TEGRA210_UART_CHOICES 2. I requested to have that halt() added after console_init(). ===>Ok, I will move it.... 3. Looks like other boards with same superio use call ite_kill_watchdog(), I don't know what it8718f_disable_reboot() does. ===> I have no idea as well, I followed on example from the board which used it8718f 4. There was also suggestion to dump superio ID register on POST display to make sure LPC bus communication to superio works, but I did not hear back from that experiment. ===> can you tell me how to do that ? Cheers On Wed, Oct 26, 2016 at 9:58 AM, Kyösti Mälkki <kyosti.malkki(a)gmail.com> wrote: > The information missing from the mail is I requested to have that halt() > added after console_init(). > > Also at least it was previously reported system was in a periodic reset-loop > regardless of the halt() there, so sn active watchdog may be involved here. > Looks like other boards > with same superio use call ite_kill_watchdog(), I don't know what > it8718f_disable_reboot() does. > > There was also suggestion to dump superio ID register on POST display to > make sure LPC bus communication to superio works, but I did not hear back > from that experiment. > > Kyösti > > On Wed, Oct 26, 2016 at 4:36 AM, Riko Ho <antonius.riko(a)gmail.com> wrote: >> >> Everyone, >> >> I tried to initialize UART on IT8718F and it stopped at 0xD2... >> Here's the complete function, any clues ? >> >> Cheers >> =============== >> void mainboard_romstage_entry(unsigned long bist) >> { >> int s3resume = 0, boot_mode = 0; >> >> if (bist == 0) >> enable_lapic(); >> >> ich7_enable_lpc(); >> post_code(0xD1); >> /* Enable SuperIO PM */ >> //lpc47m15x_enable_serial(PME_DEV, 0x680); >> //lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ >> //enable_dev(SERIAL_DEV); >> //ite_conf_clkin();//needs a parameter, what is it ? >> >> /* >> 04:24:31 AM) idwer: 24 or 48 MHz? >> >> (04:25:18 AM) idwer: how do you find out? run superiotool when >> having booted with the vendor bios, and look at register >> CR23 >> */ >> //ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); >> ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); >> >> >> ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ >> //printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT BY RIKO HO...\n"); >> //it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); >> it8718f_disable_reboot(GPIO_DEV); >> /* Set up the console */ >> console_init(); >> post_code(0xD2); >> printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT ...\n"); >> halt(); >> post_code(0xD3); >> >> >> >> /* Halt if there was a built in self test failure */ >> report_bist_failure(bist); >> >> if (MCHBAR16(SSKPD) == 0xCAFE) { >> printk(BIOS_DEBUG, "soft reset detected.\n"); >> boot_mode = 1; >> } >> >> /* Perform some early chipset initialization required >> * before RAM initialization can work >> */ >> i945_early_initialization(); >> post_code(0xD4); >> s3resume = southbridge_detect_s3_resume(); >> >> /* Enable SPD ROMs and DDR-II DRAM */ >> enable_smbus(); >> >> #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 >> dump_spd_registers(); >> #endif >> >> sdram_initialize(s3resume ? 2 : boot_mode, NULL); >> >> /* Perform some initialization that must run before stage2 */ >> early_ich7_init(); >> >> /* This should probably go away. Until now it is required >> * and mainboard specific >> */ >> rcba_config(); >> >> /* Chipset Errata! */ >> fixup_i945_errata(); >> >> /* Initialize the internal PCIe links before we go into stage2 */ >> i945_late_initialization(s3resume); >> } >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot > >

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Re: [coreboot] Microcode.bin question ?
by Riko Ho Oct. 25, 2016

Oct. 25, 2016

Is it "Allow use of binary-only repository" option ? On 26/10/2016 8:15 AM, David Hendricks wrote: > > > On Tue, Oct 25, 2016 at 4:29 PM, Riko Ho <antonius.riko(a)gmail.com > <mailto:antonius.riko@gmail.com>> wrote: > > Hi Martin, > > Do you mean the value of CONFIG_USE_BLOBS inside .config file ? > > > Yes. > > What's the option name one 'make menuconfig' ? > > > Search for it using '/' (like in vi). > > -- > David Hendricks (dhendrix) > Systems Software Engineer, Google Inc.

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Re: [coreboot] Stops at 0xD2
by Kyösti Mälkki Oct. 25, 2016

Oct. 25, 2016

The information missing from the mail is I requested to have that halt() added after console_init(). Also at least it was previously reported system was in a periodic reset-loop regardless of the halt() there, so sn active watchdog may be involved here. Looks like other boards with same superio use call ite_kill_watchdog(), I don't know what it8718f_disable_reboot() does. There was also suggestion to dump superio ID register on POST display to make sure LPC bus communication to superio works, but I did not hear back from that experiment. Kyösti On Wed, Oct 26, 2016 at 4:36 AM, Riko Ho <antonius.riko(a)gmail.com> wrote: > Everyone, > > I tried to initialize UART on IT8718F and it stopped at 0xD2... > Here's the complete function, any clues ? > > Cheers > =============== > void mainboard_romstage_entry(unsigned long bist) > { > int s3resume = 0, boot_mode = 0; > > if (bist == 0) > enable_lapic(); > > ich7_enable_lpc(); > post_code(0xD1); > /* Enable SuperIO PM */ > //lpc47m15x_enable_serial(PME_DEV, 0x680); > //lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ > //enable_dev(SERIAL_DEV); > //ite_conf_clkin();//needs a parameter, what is it ? > > /* > 04:24:31 AM) idwer: 24 or 48 MHz? > > (04:25:18 AM) idwer: how do you find out? run superiotool when > having booted with the vendor bios, and look at register > CR23 > */ > //ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); > ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); > > > ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ > //printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT BY RIKO HO...\n"); > //it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); > it8718f_disable_reboot(GPIO_DEV); > /* Set up the console */ > console_init(); > post_code(0xD2); > printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT ...\n"); > halt(); > post_code(0xD3); > > > > /* Halt if there was a built in self test failure */ > report_bist_failure(bist); > > if (MCHBAR16(SSKPD) == 0xCAFE) { > printk(BIOS_DEBUG, "soft reset detected.\n"); > boot_mode = 1; > } > > /* Perform some early chipset initialization required > * before RAM initialization can work > */ > i945_early_initialization(); > post_code(0xD4); > s3resume = southbridge_detect_s3_resume(); > > /* Enable SPD ROMs and DDR-II DRAM */ > enable_smbus(); > > #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 > dump_spd_registers(); > #endif > > sdram_initialize(s3resume ? 2 : boot_mode, NULL); > > /* Perform some initialization that must run before stage2 */ > early_ich7_init(); > > /* This should probably go away. Until now it is required > * and mainboard specific > */ > rcba_config(); > > /* Chipset Errata! */ > fixup_i945_errata(); > > /* Initialize the internal PCIe links before we go into stage2 */ > i945_late_initialization(s3resume); > } > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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Stops at 0xD2
by Riko Ho Oct. 25, 2016

Oct. 25, 2016

Everyone, I tried to initialize UART on IT8718F and it stopped at 0xD2... Here's the complete function, any clues ? Cheers =============== void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0, boot_mode = 0; if (bist == 0) enable_lapic(); ich7_enable_lpc(); post_code(0xD1); /* Enable SuperIO PM */ //lpc47m15x_enable_serial(PME_DEV, 0x680); //lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ //enable_dev(SERIAL_DEV); //ite_conf_clkin();//needs a parameter, what is it ? /* 04:24:31 AM) idwer: 24 or 48 MHz? (04:25:18 AM) idwer: how do you find out? run superiotool when having booted with the vendor bios, and look at register CR23 */ //ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ //printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT BY RIKO HO...\n"); //it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); it8718f_disable_reboot(GPIO_DEV); /* Set up the console */ console_init(); post_code(0xD2); printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT ...\n"); halt(); post_code(0xD3); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; } /* Perform some early chipset initialization required * before RAM initialization can work */ i945_early_initialization(); post_code(0xD4); s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif sdram_initialize(s3resume ? 2 : boot_mode, NULL); /* Perform some initialization that must run before stage2 */ early_ich7_init(); /* This should probably go away. Until now it is required * and mainboard specific */ rcba_config(); /* Chipset Errata! */ fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(s3resume); }

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SerialICE question
by Riko Ho Oct. 25, 2016

Oct. 25, 2016

Everyone, I tried to understand : https://www.serialice.com/Getting_Started In my case: I want to see i946 init sequence, How can I tap it from vendor BIOS ? I have one debugging system and the other is debugged system, how SerialICE works between of them ? When i946 cold boots ....then ?? Cheers

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Re: [coreboot] Microcode.bin question ?
by Riko Ho Oct. 25, 2016

Oct. 25, 2016

Hi Martin, Do you mean the value of CONFIG_USE_BLOBS inside .config file ? What's the option name one 'make menuconfig' ? Cheers On 26/10/2016 6:45 AM, Martin Roth wrote: > Hi Riko, > Make sure you have "Allow use of binary-only repository" > (CONFIG_USE_BLOBS) selected in kconfig. This is disabled by default > for people who don't want any blobs in their builds. > > I've verified that the file exists in that location. > > Martin > > On Mon, Oct 24, 2016 at 8:40 PM, Riko Ho <antonius.riko(a)gmail.com > <mailto:antonius.riko@gmail.com>> wrote: > > Everyone, > > Where can I get microcode.bin, and how to patch it to my code ? > > I got this when I choose "Device tree" option.... > No rule to make target > '3rdparty/blobs/cpu/intel/model_6ex/microcode.bin', needed by > 'build/cpu_microcode_blob.bin'. Stop. > > Cheers > > -- > coreboot mailing list: coreboot(a)coreboot.org > <mailto:coreboot@coreboot.org> > https://www.coreboot.org/mailman/listinfo/coreboot > <https://www.coreboot.org/mailman/listinfo/coreboot> > >

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Re: [coreboot] Microcode.bin question ?
by Martin Roth Oct. 25, 2016

Oct. 25, 2016

Hi Riko, Make sure you have "Allow use of binary-only repository" (CONFIG_USE_BLOBS) selected in kconfig. This is disabled by default for people who don't want any blobs in their builds. I've verified that the file exists in that location. Martin On Mon, Oct 24, 2016 at 8:40 PM, Riko Ho <antonius.riko(a)gmail.com> wrote: > Everyone, > > Where can I get microcode.bin, and how to patch it to my code ? > > I got this when I choose "Device tree" option.... > No rule to make target > '3rdparty/blobs/cpu/intel/model_6ex/microcode.bin', needed by > 'build/cpu_microcode_blob.bin'. Stop. > > Cheers > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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Microcode.bin question ?
by Riko Ho Oct. 24, 2016

Oct. 24, 2016

Everyone, Where can I get microcode.bin, and how to patch it to my code ? I got this when I choose "Device tree" option.... No rule to make target '3rdparty/blobs/cpu/intel/model_6ex/microcode.bin', needed by 'build/cpu_microcode_blob.bin'. Stop. Cheers

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POST Code 0x24 and 0x2F
by Riko Ho Oct. 23, 2016

Oct. 23, 2016

Everyone, I got chat with idwer this noon and my CPU model : 4 Model name : Intel (R) Pentium (R) 4 CPU 3.00 GHz x 2 I got 0x24 and 0x2F on cache_as_ram_ht.inc ... so it stopped at before_romstage: and loop again to movl $1,%eax, What do you reckon to find out what wrong with it ? Have a look on the chat below : [10:35] <bianchi> CPU family : 15 x 2 [10:35] <bianchi> model : 4 [10:35] <bianchi> model name : Intel (R) Pentium (R) 4 CPU 3.00 GHz x 2 [10:35] <bianchi> idwer : from here, where do we go ? [10:38] * piccaruse (~piccaruse(a)h-64-105.a465.priv.bahnhof.se) Quit (Ping timeout: 256 seconds) [10:39] * arescorpio (~arescorpi(a)152.171.91.145) has joined #coreboot [10:39] <bianchi> the code stopped here : before_romstage: [10:39] <bianchi> post_code(0x2f) ...and return to [10:39] <bianchi> post_code(0x24) [10:39] <bianchi> movl $1, %eax [10:40] <bianchi> around cache memory initialization.. [10:40] <idwer> model 4 [10:40] <idwer> so model_f4x [10:40] <bianchi> yup [10:41] <idwer> I have no idea :( [10:41] <bianchi> that's allright...neither do I :( [10:41] <bianchi> may be someone else does... [10:41] <idwer> LGA774/Kconfig shows 'select CPU_INTEL_MODEL_F4X' [10:42] <idwer> well can you post your findings to the mailinglist [10:42] <bianchi> it's LGA775 ... [10:42] <bianchi> this chat ? [10:42] <bianchi> ok...not a problem.. Cheers

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