September 2013 - coreboot - mail.coreboot.org

Re: [coreboot] Freescale i.MX6
by Christian Gmeiner Sept. 18, 2013

Sept. 18, 2013

Hi all > I do not know of any active efforts to support i.MX6 in coreboot. However, > if you are interested in leading the porting effort then we can help. I > think that ARM-specific portions will be simple. The hard parts are DRAM and > peripheral init. If we can help you boot to the point where UART works, will > you feel comfortable doing the remaining work? > DRAM init is quite simple on the I.MX6. Also it is quite simple to turn on all peripheral clocks. The IOMUX stuff could be a little bit challenging as I don't know the current sw architecture coreboot uses on ARM. > As far as I know, the focus of ARM development in coreboot is on Exynos5 > (Cortex-A15). We are currently booting Exynos5250 and Exynos5420 systems. TI > AM335X (Cortex-A8) support is still somewhat active, but is a side-project. > We can initialize the CPU and get serial console output so future > development will be much easier. > Looks like a fun project for some rainy holiday days :) Maybe I can help out a little bit as I did a u-boot board-bring-up for a custom I-MX6D/Q board the last weeks. -- Christian Gmeiner, MSc

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Re: [coreboot] Tyan s2912-E reset loop, Please help
by Mark Mc Sept. 17, 2013

Sept. 17, 2013

Hi Marc, I think you are correct and that something is going wrong in romstage.c where "wants_reset = mcp55_early_setup_x()" which seems to execute that function in early_setup_car.c just before the warm reset however the code within this function is beyond my skill set and the only way I can see myself correcting this is if I cound find an older release of coreboot v4 (late 2010) as there are a number of posts in the mail archive of this board working correctly at that time. Do you of anyway to get this? Cheers Mark On Mon, Sep 16, 2013 at 4:21 AM, Marc Jones <marcj303(a)gmail.com> wrote: > On Tue, Sep 10, 2013 at 9:07 PM, Mark Mc <markymcd13(a)gmail.com> wrote: > > Thank you Kyösti, there was no need to change MAX_CPUS as I had selected > > S2912 Fam10 (Thunder n3600R) so it is already set to 12 CPUS, I did > change > > what else you told me to so that I could get more output to the serial > > console. I think I am getting closer to identifying the problem which is > > that the MCP55 (Southbridge) needs a warm reset to continue after POST: > 0x3a > > however in this case it cannot I am currently studying the > > /src/mainboard/tyan/s2912_fam10/romstage.c to try and identify what is > going > > wrong any suggestions are appreciated. > > > > My coreboot log now looks like this: > > > ----------------------------------------------------------------------------------------------------------------------------------------- > > > > coreboot-4.0-4671-g25dd247 Mon Sep 9 23:54:49 BST 2013 starting... > > BSP Family_Model: 00100f80 > > *sysinfo range: [000c4000,000c5fa0] > > bsp_apicid = 00 > > cpu_init_detectedx = 00000000 > > microcode: rev id not found. Skipping microcode patch! > > POST: 0x33 > > cpuSetAMDMSR done > > POST: 0x34 > > Enter amd_ht_init() > > AMD_CB_ManualBUIDSwapList() > > AMD_CB_EventNotify() > > event class: 05 > > event: 2006 > > data: 04 00 02 ff > > Exit amd_ht_init() > > POST: 0x35 > > cpuSetAMDPCI 00 done > > Prep FID/VID Node:00 > > F3x80: e600e681 > > F3x84: 80e641e6 > > F3xD4: c3310f27 > > F3xD8: 03000215 > > F3xDC: 00006428 > > POST: 0x36 > > core0 started: > > start_other_cores() > > init node: 00 cores: 05 > > Start other core - nodeid: 00 cores: 05 > > POST: 0x37 > > started ap apicid: * AP 01started > > * AP 02started > > * AP 03started > > * AP 04started > > * AP 05started > > > > POST: 0x38 > > > > Begin FIDVID MSR 0xc0010071 0x38a400c4 0x38044c40 > > POST: 0x39 > > FIDVID on BSP, APIC_id: 00 > > BSP fid = 0 > > Wait for AP stage 1: ap_apicid = 1 > > readback = 1000001 > > common_fid(packed) = 0 > > Wait for AP stage 1: ap_apicid = 2 > > readback = 2000001 > > common_fid(packed) = 0 > > Wait for AP stage 1: ap_apicid = 3 > > readback = 3000001 > > common_fid(packed) = 0 > > Wait for AP stage 1: ap_apicid = 4 > > readback = 4000001 > > common_fid(packed) = 0 > > Wait for AP stage 1: ap_apicid = 5 > > readback = 5000001 > > common_fid(packed) = 0 > > common_fid = 0 > > POST: 0x3a > > End FIDVIDMSR 0xc0010071 0x38a400c4 0x38044c40 > > mcp55_num:01 > > POST: 0x30 > > > > > > > > INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- > > > > Issuing SOFT_RESET... > > > --------------------------------------------------------------------------------------------------------------------------------------------- > > Cheers > > Mark > > > > After the soft reset, it should got through romstage again, but skip > the clock init (fid/vid) and then do the memory init. It might have a > problem with detecting the warm reset. > > Marc > > > > > > > > > > On Tue, Sep 10, 2013 at 4:54 AM, Kyösti Mälkki <kyosti.malkki(a)gmail.com> > > wrote: > >> > >> On Tue, 2013-09-10 at 02:01 +0100, Mark Mc wrote: > >> > Hi, I finally got coreboot compiled correctly and I am getting > >> > somewhere as my console output shows: > >> > > >> > coreboot-4.0-4671-g25dd247 Mon Sep 9 23:54:49 BST 2013 starting... > >> > BSP Family_Model: 00100f80 > >> > *sysinfo range: [000c4000,000c5fa0] > >> > bsp_apicid = 00 > >> > cpu_init_detectedx = 00000000 > >> > microcode: rev id not found. Skipping microcode patch! > >> > POST: 0x33 > >> > cpuSetAMDMSR done > >> > POST: 0x34 > >> > Enter amd_ht_init() > >> > AMD_CB_ManualBUIDSwapList() > >> > AMD_CB_EventNotify() > >> > event class: 05 > >> > event: 2006 > >> > data: 04 00 02 ff > >> > Exit amd_ht_init() > >> > POST: 0x35 > >> > cpuSetAMDPCI 00 done > >> > Prep FID/VID Node:00 > >> > F3x80: e600e681 > >> > F3x84: 80e641e6 > >> > F3xD4: c3310f27 > >> > F3xD8: 03000215 > >> > F3xDC: 00006428 > >> > POST: 0x36 > >> > core0 started: > >> > start_other_cores() > >> > init node: 00 cores: 05 > >> > Start other core - nodeid: 00 cores: 05 > >> > POST: 0x37 > >> > started ap apicid: * AP 01started > >> > * AP 02started > >> > * AP 03started > >> > * AP 04started > >> > * AP 05started > >> > > >> > >> > INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- > >> > Issuing SOFT_RESET... > >> > > >> > > >> > However it just keeps looping like this, any guidance would be really > >> > appreciated, so far I have tried booting with just 1 dimm (4GB),1 CPU > >> > (opteron 2419) and no PCI-E cards, both stable and master seabios > >> > payloads but so far absolutely no difference. > >> > >> > >> First increase MAX_CPUS in src/mainboard/tyan/2912/Kconfig from 4 to 12. > >> > >> If that alone does not work, try change SERIAL_CPU_INIT=yes in same > >> file. Additionally in menuconfig under consoles, try with > >> SQUELCH_EARLY_SMP=no. > >> > >> Last two changes should not be required, just something to try as they > >> will slow down the boot sequence and give more output on serial console. > >> > >> Remember that after modifying any Kconfig file, you need a clean build: > >> make clean && make oldconfig && make > >> > >> > >> Regards, > >> Kyösti > >> > > > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > > > -- > http://se-eng.com >

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Re: [coreboot] Freescale i.MX6
by David Hendricks Sept. 17, 2013

Sept. 17, 2013

Hi Wolfgang, I do not know of any active efforts to support i.MX6 in coreboot. However, if you are interested in leading the porting effort then we can help. I think that ARM-specific portions will be simple. The hard parts are DRAM and peripheral init. If we can help you boot to the point where UART works, will you feel comfortable doing the remaining work? As far as I know, the focus of ARM development in coreboot is on Exynos5 (Cortex-A15). We are currently booting Exynos5250 and Exynos5420 systems. TI AM335X (Cortex-A8) support is still somewhat active, but is a side-project. We can initialize the CPU and get serial console output so future development will be much easier.

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Re: [coreboot] Coreboot Haswell Support
by Patrick Georgi Sept. 17, 2013

Sept. 17, 2013

Am Dienstag, den 17.09.2013, 12:12 +0000 schrieb Stojsavljevic, Zoran: > Do not want to reply to your (rather angry) arguments, And for those angry arguments I'd like to apologize: I've seen "yet another Intel rep asking 'Why not UEFI?'" instead of the real human being you are. As for the other comments, I think it's getting off-topic quickly, so let's do that via private mail... Regards, Patrick

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Re: [coreboot] Coreboot Haswell Support
by ron minnich Sept. 17, 2013

Sept. 17, 2013

There is haswell support in coreboot. The recently demonstrated laptops at IDF have it, and intel even mentioned coreboot on a slide. In fact the HP chromebook which was demoed has no video bios; all the firmware video functions on that one are source-based. For the latest code you can see the chromium OS repo. We are upstreaming as fast as we can to coreboot.org, but it's a huge job. For SNB and IVB, Google clearly had permission from Intel to release the mrc.bin, since if we had not had permission, we would not have uploaded it. About 18 months ago we were asked to upload it and we did upload it; QED. You might perhaps read between the lines as to whether Google has been given permission to release the HSW mrc.bin, i.e. you might conclude that since it has not been uploaded, Google does not have permission. If Intel were not to grant Google permission to release the mrc.bin, I think that would be a regrettable situation, to say the least; that said, I am not saying either way whether permission has been granted, will be granted, or will not be granted. I am only suggesting that you could draw your own conclusions. I also feel that in a better world, that mrc.bin would have been uploaded to coreboot.org by now or we would have a URL for where to download it. I'm not holding my breath. Until FSP has an actual, binary release, it is vaporware and slide decks. So, yes, people can tell us with the best of intentions that it is coming; I have not seen it. No one I know has seen it. Some people that know some people say they have seen it. I suggest that you put "FSP' in the same category as "Santa Claus" until you have it on your system. There's a reason all my current coreboot work is on ARM. ron

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Re: [coreboot] Coreboot Haswell Support
by Patrick Georgi Sept. 17, 2013

Sept. 17, 2013

Am 2013-09-17 09:36, schrieb Stojsavljevic, Zoran: > I am not sure what is your scenario here. If you are attempting to > bring HSW to grub, and then to Linux, Coreboot is not required, as far > as you are using classical EFI BIOS or new UEFI BIOS (AMI, Phoenix, > Insyde). There's nothing said about GRUB or Linux in his mail - since he didn't go into detail on what he's planning, for all we know his project might be fundamentally incompatible with EFI, "Unified" or not. Anyway, reasons why UEFI might not be suitable for users (no matter if GRUB or not): - The IBVs's track record in product quality is rather mixed (Samsung's UEFI variable issue, for example. More examples: all the BIOS workarounds within Linux) - IBV's products aren't open source - UEFI's footprint is at least five times that of a coreboot solution in terms of lines of code (yes, I measured it) - the previous two issues make any quality and/or security assessment of UEFI solutions harder than of a coreboot solution I didn't think that these types of arguments need any more mention on the coreboot mailing list, but here we are... > As my best understanding is, mrc.bin was released by Google in the > best effort to support minimalistic approach (mrc.bin equivalent to > x-loader) with Coreboot SNB (I guess, applies for IVB as well) support > (Google did created mrc.bin with some internal INTEL group support). Yes, and Google's "best effort" only had to happen because Intel isn't willing to support their customers' wishes. > All these are now called Firmware Support Packages (FSPs), and they > have locked IPs, sole property of INTEL. Please, read the following, > widely available on INTEL external web site: "locked IPS, sole property of INTEL" is probably not a very appropriate slogan when interacting with an open source community. > http://www.intel.com/fsp > http://www.intel.com/content/dam/www/public/us/en/documents/training/intel-… Since nothing but whitepapers is published on FSP yet, this can be safely considered vaporware. > I am not sure about HSW FSP roadmap, I think HSW FSP is officially not > released yet. Indeed. Maybe you can figure out a schedule for when we can expect an FSP binary that we can host in our 3rdparty repository under the same terms as the current MRC binaries? That is, if FSP ever gets released at all (even Duke Nukem Forever did eventually happen, so let's hope) Regards, Patrick

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Re: [coreboot] Coreboot Haswell Support
by Stojsavljevic, Zoran Sept. 17, 2013

Sept. 17, 2013

Hello Karl-Heinz, I am not sure what is your scenario here. If you are attempting to bring HSW to grub, and then to Linux, Coreboot is not required, as far as you are using classical EFI BIOS or new UEFI BIOS (AMI, Phoenix, Insyde). As my best understanding is, mrc.bin was released by Google in the best effort to support minimalistic approach (mrc.bin equivalent to x-loader) with Coreboot SNB (I guess, applies for IVB as well) support (Google did created mrc.bin with some internal INTEL group support). All these are now called Firmware Support Packages (FSPs), and they have locked IPs, sole property of INTEL. Please, read the following, widely available on INTEL external web site: http://www.intel.com/fsp http://www.intel.com/content/dam/www/public/us/en/documents/training/intel-… I am not sure about HSW FSP roadmap, I think HSW FSP is officially not released yet. Best Regards, Zoran _______ Most of The Time you should be "intel inside" to be capable to think "out of the box". From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Karl-Heinz Nirschl Sent: Wednesday, September 11, 2013 11:37 AM To: coreboot(a)coreboot.org Subject: [coreboot] Coreboot Haswell Support Hi List, There seems to be some support for intel haswell platform in coreboot. But i can not find the neccessary systemagent / mrb.bin binary. Isnt it released yet? Best regards, Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft: Feldkirchen bei Muenchen Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk Registergericht: Muenchen HRB 47456 Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052

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Re: [coreboot] Freescale i.MX6
by Stojsavljevic, Zoran Sept. 17, 2013

Sept. 17, 2013

This is supported by U-Boot, I know this for the fact. Since ARMv7 Cortex A9 as main HSW driving force is used in most smart phones presently (Android). About i.MX6 not sure... Since I am new to Coreboot, I am also wondering about Cortex A9. :) Zoran _______ Most of The Time you should be "intel inside" to be capable to think "out of the box". From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Wolfgang Kamp - datakamp Sent: Tuesday, September 17, 2013 8:26 AM To: coreboot(a)coreboot.org Subject: [coreboot] Freescale i.MX6 Hi, are there any plans for coreboot support to Freescales's ARM Cortex A9 i.MX6 in the future? Regards, Wolfgang Kamp Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft: Feldkirchen bei Muenchen Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk Registergericht: Muenchen HRB 47456 Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052

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Freescale i.MX6
by Wolfgang Kamp - datakamp Sept. 17, 2013

Sept. 17, 2013

Hi, are there any plans for coreboot support to Freescales's ARM Cortex A9 i.MX6 in the future? Regards, Wolfgang Kamp

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About coreboot hangup on AMD KabiniPI
by xueshengfeng Sept. 16, 2013

Sept. 16, 2013

Dear All Coreboot member, I am a BIOS engineer which come from Byosoft. Now, we got a AMD KabiniPI CRB board and will power on this board with Coreboot+SeaBIOS. Would you please help to confirm some setting? 1. Mainboard model is Olive Hill or not? 2. It's will hangup when we using coreboot to power on. So I want to know where is the serial port? Or using any other tool to debug it? Best Regards, Roy EXT:8047

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