August 2013 - coreboot - mail.coreboot.org

Re: [coreboot] SOC directory under src
by David Hendricks Aug. 29, 2013

Aug. 29, 2013

On Wed, Aug 28, 2013 at 2:51 PM, Aaron Durbin <adurbin(a)chromium.org> wrote: > Hi folks, > > I'm going to be working on a part that is an SOC. Because of this all > the traditional northbridge, southbridge, and cpu are tightly coupled. > Instead of splitting things out across those 3 directories I'm > inclined to create a 'soc' directory under src. All the related files > would fall under there: > > src/soc/<vendor>/<soc_name>/... > > It seems more logical to me, and as I'm sure you are all aware the > lines are quite a bit of inter-dependencies in products now-a-days. > > I think/hope people won't too upset about this. > SGTM. We thought about doing something like that for the Exynos SoCs originally but ultimately decided on src/cpu to avoid polluting the codebase for what was essentially an experiment at the time. Now that it's past the experimental phase and we're going to see more SoCs in coreboot, it makes sense to avoid confusing them with the traditional CPU/NB/SB system architecture. If you add the src/soc directory, you can move src/cpu/{armltd,ti} into it as well. We can wait until the next large upstreaming for Exynos stuff before moving it. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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SOC directory under src
by Aaron Durbin Aug. 28, 2013

Aug. 28, 2013

Hi folks, I'm going to be working on a part that is an SOC. Because of this all the traditional northbridge, southbridge, and cpu are tightly coupled. Instead of splitting things out across those 3 directories I'm inclined to create a 'soc' directory under src. All the related files would fall under there: src/soc/<vendor>/<soc_name>/... It seems more logical to me, and as I'm sure you are all aware the lines are quite a bit of inter-dependencies in products now-a-days. I think/hope people won't too upset about this. -Aaron

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Support for Gigabyte GA-P55-USB3
by Дмитрий Aug. 27, 2013

Aug. 27, 2013

Hello, can you please tell me if it is possible to adapt coreboot to run on this motherboard? It's description can be found on http://www.gigabyte.com/products/product-page.aspx?pid=3440 . I'm not quite sure about the ICs on the MB, but according to superiotool it has IT8720F inside. BIOS resides on two MX25L1605 ICs (one re-programmable, other is persistent -- for backup). I am also attaching outputs of utils mentioned in FAQ. Flashing original BIOS via flashrom seems to work perfectly (upgraded to version F10g using this method without any problems). -- Regards, Dmitriy Dyomin

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Fwd: need to build coreboot on via epia-m w gcc 4.5.1 - impossible, eh ?
by matti christensen Aug. 27, 2013

Aug. 27, 2013

Many thanks for your kind comments --- the mb says 'VIA EPIA rev.b' = C3 1Ghz - but better to read dmesg --- You may find dmesg attached --- distribution is CRUX 2.7 with all the things no one needs ripped ( like udev, package management, ..... ) and some things that one may need built, like Xorg, git, svn /mc ---------- Forwarded message ---------- From: Idwer Vollering <vidwer(a)gmail.com> Date: Tue, 27 Aug 2013 13:37:04 +0200 Subject: Re: [coreboot] need to build coreboot on via epia-m w gcc 4.5.1 - impossible, eh ? To: coreboot <coreboot(a)coreboot.org> 2013/8/27 matti christensen <mattic(a)iki.fi> > /mc > matti christensen > ---keep-IT-simple--- > No one can, or will, help you when you don't include any information at all. Which linux distribution are you using? Did you run 'make crossgcc' ? coreboot supports three [1] epia-m boards, which one do you have? [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=tree;f=src/mainboard/via… > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- ---keep-IT-simple---

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Re: [coreboot] need to build coreboot on via epia-m w gcc 4.5.1 - impossible, eh ?
by Idwer Vollering Aug. 27, 2013

Aug. 27, 2013

2013/8/27 matti christensen <mattic(a)iki.fi> > /mc > matti christensen > ---keep-IT-simple--- > No one can, or will, help you when you don't include any information at all. Which linux distribution are you using? Did you run 'make crossgcc' ? coreboot supports three [1] epia-m boards, which one do you have? [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=tree;f=src/mainboard/via… > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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need to build coreboot on via epia-m w gcc 4.5.1 - impossible, eh ?
by matti christensen Aug. 27, 2013

Aug. 27, 2013

/mc matti christensen ---keep-IT-simple---

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Re: [coreboot] Ram initization
by ron minnich Aug. 26, 2013

Aug. 26, 2013

from my POV, the ddr3 startup in the exynos5420 code is good, and for a really good ddr memory example check out the i945, which I found very readable. ron

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Re: [coreboot] Ram initization
by David Hendricks Aug. 26, 2013

Aug. 26, 2013

On Mon, Aug 26, 2013 at 12:47 PM, David Hendricks <dhendrix(a)google.com>wrote: > On Mon, Aug 26, 2013 at 1:13 AM, Patrick Georgi <patrick(a)georgi-clan.de>wrote: > >> Am 26.08.2013 09:12, schrieb Mohit Gupta: >> > After that I get stuck completely mainly because of RAM initialization >> > steps as per JEDEC. I am looking for resources or tutorials which can >> > point to me in right direction as to how read SPD info and use that to >> > configure or initialize RAM module. >> Memory initialization varies a lot by the standard (DDR2 vs DDR3, for >> example), and - when looking at it from the point of view of a firmware >> implementer - also by the chipset that drives the memory. For example >> the VIA chipsets with DDR3 support seem to do many things by itself that >> must be handled explicitely by initialization code on other chipsets. >> >> I find our RAM init code for older Intel chipsets quite readable. But >> I'm probably biased because I was part of the development teams for that >> code. >> >> You can find it at src/northbridge/i945 (driving DDR2) and >> src/northbridge/gm45 (DDR3) in our source tree. >> http://www.coreboot.org/Git describes how to access the source code. >> > > As Patrick pointed out, it is quite specific to the hardware you are > working on. And unfortunately documentation is scarce. Fortunately AMD > publishes a good deal of info about their DRAM controller init in their > BIOS and Kernel Developer's Guides (BKDG). Section 2.9.7 of the Family 16h > BKDG sheds some light on the steps involved: > http://developer.amd.com/resources/documentation-articles/developer-guides-… > And on that note, you can peruse the sources here: http://review.coreboot.org/gitweb?p=coreboot.git;a=tree;f=src/vendorcode/am… However I didn't work on that code so I have no idea how closely it resembles the manual. It might be better to start with the Exynos code as it much simpler and more self-contained. Then as you familiarize yourself with some common terminology you can dig into the more sophisticated AMD Northbridge code. Ctags are your friend, BTW. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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Ram initization
by Mohit Gupta Aug. 26, 2013

Aug. 26, 2013

Hi all, I am a newbie, and trying to understand RAM / DRAM initialization code. I have understood upto SMBus Controller / I2C protocol and how it can be used to get SPD information from DRAM module (DDR/DDR2/DD3/...). After that I get stuck completely mainly because of RAM initialization steps as per JEDEC. I am looking for resources or tutorials which can point to me in right direction as to how read SPD info and use that to configure or initialize RAM module. Your help will definitely help me in understanding very core of RAM initialization process. My sole purpose is to enhance my knowledge. I also don't know if I am allowed to post such queries or if this mailing list is only for advanced level users. Regards Mohit Gupta

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MSI 870S-G54 (MS-7599) Motherboard Specs
by GS Hunt Aug. 24, 2013

Aug. 24, 2013

// <http://ca.msi.com/product/mb/870S-G54.html>Brief Descriptions MSI 870S-G54 (MS-7599) Chipset*NorthBridge AMD870 Soutbridge 850** *CPU AMD Athlon(tm) II X4 640 Processor lspci atached flashrom info attached. superiotool super io not detected super i/o info from dmesg -> f71882fg: Found f71889ed chip at 0x600, revision 16 Supports dumping bios to USB device Will run bios from a USB device (no flashing required) Manufacture Website http://ca.msi.com/product/mb/870S-G54.html#/?div=Detail

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