August 2013 - coreboot - mail.coreboot.org

Re: [coreboot] No VGA output on e350m1 after flashing. what to do?
by Reiner Luett Sept. 12, 2017

Sept. 12, 2017

Hi! On 30.06.2013 19:28, Christian Weinz wrote: > Maybe I didn't include the VGA option in the make menuconfig process. > How can I solve this problem? You need to add the VGA Option ROM (VGA BIOS -> Add VGA BIOS image). I've extracted it from the UEFI, but you also could use these: http://www.coreboot.org/index.php?title=ASRock_E350M1&oldid=11114 at the end of the page or you also may be able to use the default AMD fam14 (Persimmon) vbios. You will need to agree to the click through: http://wwwd.amd.com/support/vbioslic.nsf/userverify?openform http://www.coreboot.org/AMD_DB-FT1_PERSIMMON It's a pity, that bios_extract didn't work for now. You could use the AMI Aptio EFI MMTool with wine: http://win-lite.de/benutzer/fernando/BIOS-Tools/AMI_Aptio_EFI_MMTool_v4.50.… You need to extract OntarioEFIVbios with PCI ID 1002,9802 as Option ROM. Regards, Reiner --

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#95: Run coreboot in VirtualBox
by coreboot Dec. 10, 2014

Dec. 10, 2014

#95: Run coreboot in VirtualBox ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: misc | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ It would be nice if we could test coreboot images in VirtualBox, see http://virtualbox.org/. VirtualBox does not (yet) provide a simple mechanism to use a different BIOS in their emulated machines (something like "-L" in qemu). Instead the BIOS image (a custom bochs BIOS + LGPL'g VGABIOS) is converted to C code (an array of bytes, or the like) and merged into the VirtualBox executable. The relevant files are {{{ src/VBox/Devices/PC/DevPcBios.cpp bldprogs/bin2c.c }}} if someone want to hack VirtualBox to easily support using coreboot images instead of their usual BIOS. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/95> coreboot <http://www.coreboot.org/>

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EHCI debug port finder
by Carl-Daniel Hailfinger May 30, 2014

May 30, 2014

I wanted to know which physical port of my multiple USB controllers have the debug capability. There was no way to find that easily, so I created a tool which will do most of the work for the user. Example output: The following PCI devices support a USB debug port (says lspci): 0000:00:1d.7 The following PCI devices support a USB debug port (says the kernel): 0000:00:1d.7 PCI device 0000:00:1d.7, USB bus 3, USB physical port 1 Currently connected high-speed devices: /: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=ehci_hcd/6p, 480M |__ Port 2: Dev 20, If 0, Class=stor., Driver=usb-storage, 480M The output can be improved, but it's a good start. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Dual SPI Flash adapter attempt 2.0
by Oliver Schinagl March 9, 2014

March 9, 2014

Hi list(s), Here's my second attempt at routing the previously mailed png of my schema. It was a lot trickier to route then my previous version, but I think it worked out! As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1 should be 10k or ideally 100k, as Peter mentioned earlier. Hopefully there's no obvious mistakes and can start working on alternative layouts (so it is insert-able in different angles). DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow. That said, DRC check passes when I set the copper width/distance to 7mil's instead of the current 8 mils. I'm planning on having these PCB's manufactured by Seeed studio and their minimal width is much smaller. Minimum trace width: 6mil Minimum trace/vias/pads space : 6mil Minimum silkscreen width : 4mil Minimum silkscreen text size : 32mil I've used a grid size of 10mil and distances of 8 mils, as I didn't want to rely on the minimum of seed. The silkscreen I positioned using a grid size of 5 mil's however. Not sure what they mean with a 'minimum silkscreen text size' however. Anyhow, feedback greatly appreciated, so I can start working on alternative layouts :)

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fixed AMD SPI speed settings (leading to problems on E350M1/USB3)
by Stefan Tauner Feb. 2, 2014

Feb. 2, 2014

Hi, andor reported a problem where flashrom does reproducibly not work with coreboot but does with the vendor BIOS http://paste.flashrom.org/view.php?id=1614 Apparently it is related to fast reads and/or the frequency. We have forced the fastReadEnable bit in the SPI_Cntrl0 from 1 to 0 and also set NormSpeed in SPI_Cntrl1 to 16.5 Mhz (previously was 0 i.e. 66 MHz) in flashrom and the problem vanished. Coreboot hard codes the fast read setting in src/southbridge/amd/cimx/sb800/bootblock.c: static void enable_spi_fast_mode(void) { u8 byte; u32 dword; device_t dev = PCI_DEV(0, 0x14, 0x03); // set temp MMIO base volatile u32 *spi_base = (void *)0xa0000000; u32 save = pci_io_read_config32(dev, 0xa0); pci_io_write_config32(dev, 0xa0, (u32) spi_base | 2); // early enable of SPI 33 MHz fast mode read byte = spi_base[3]; spi_base[3] = (byte & ~(3 << 14)) | (1 << 14); spi_base[0] = spi_base[0] | (1 << 18); // fast read enable pci_io_write_config32(dev, 0xa0, save); } Marc suggested that this should be configurable in the devicetree or by a kconfig setting. Also, the statements using "byte" do not make a lot of sense to me. Shouldn't that be a u32 instead? The public documentation of the fastReadEnable is lacking any detail and I don't have access to the NDAed version of the RRG. Is my theory correct that the controller uses the 0x0B opcode with a fixed frequency (33 MHz?) instead of 0x03 with the frequency set by NormSpeed? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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#186: 3com 3c905tx / gpxe boot problem
by coreboot Jan. 11, 2014

Jan. 11, 2014

#186: 3com 3c905tx / gpxe boot problem -----------------------------------+---------------------------------- Reporter: jeroenkrabbendam@… | Owner: stepan@… Type: defect | Status: new Priority: minor | Milestone: Component: coreboot | Keywords: gpxe Dependencies: | Patch Status: there is no patch -----------------------------------+---------------------------------- Although (or: just because) novice in the field, I encountered some problems with netbooting with coreboot. Mobo's tried: Asus P2B, VTech with bios id ITE8671-2A69KV3IC-00. All mobo's boot '''harddisk''' fine with Asus P2B / Gigabyte GA-6BX{CE} respectively. NIC ROM is started, and loads the kernel by tftp. This is vvvveeeerrrryyy slow! Although loading, the kernel is never able to start itself. Same kernel on HDU is no problem at all (GRUB2) Note: the gpxe-image is on the nic, coreboot payload is seabios. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/186> coreboot <http://www.coreboot.org/>

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#191: Coreboot:libpayload-size_t conflicting types compiler error
by coreboot Nov. 5, 2013

Nov. 5, 2013

#191: Coreboot:libpayload-size_t conflicting types compiler error ---------------------------+---------------------------------- Reporter: Pradish | Owner: uwe@… Type: defect | Status: new Priority: blocker | Milestone: Component: libpayload | Keywords: Dependencies: | Patch Status: there is no patch ---------------------------+---------------------------------- Hi I have question related to libpayload, which I am trying to solve, but not able to. I have successfully build the coreboot.rom for QEMU x86. Now when I try to build the libpayload project it throws error. System configuration: Virtual Box –Ubuntu 11.10 version Building for X86 Paltform Earlier I have run the cross toolchain using the command ‘make crossgcc’ and it was succcessfull Error information: /coreboot/payloads/libpayload$ make install CC libpci/libpci.libpci.o In File included from include/libpayload.h:54:0, from libpci/libpci.c:30: include/x86/arch/types.h:56:22: error: conflicting types for 'size_t' In file included from include/libpayload.h:49:0, from libpci/libpci.c:30: /home/pradish/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/4.7.2/include/stdded.h:213:23: note: previous declaration of 'size_t' was here make: ***[build/libpci/libpci.libpci.o] Error 1 pradish@pradish-VrtualBox:~/coreboot/paylaods/libpayload$ can you tell me, how to resolve this , I have not done any changes to the source code. Just performed ‘make’ regards pradish -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/191> coreboot <http://www.coreboot.org/>

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tyan s8226 status
by Nick Lewycky Sept. 3, 2013

Sept. 3, 2013

What's the status of the Tyan s8226? There's a src/mainboard/tyan/s8226 directory in git coreboot, but no entry for s8226 under "board status pages". Does this mean that it's unsupported? Or conversely, is it known to work? Nick

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Problem in building coreboot + FILO for ASI_MB-5BLMP
by michele.montani＠libero.it Aug. 30, 2013

Aug. 30, 2013

Hi, I'm trying to make live again an old thin client based on ASI_MB-5BLMP motherboard. The original BIOS is blocked and I can't use it as is, so I thought to use coreboot and FILO, following the instructions found in "How to build". I retrived an old pc, installed Lubuntu and all packets listed in coreboot instructions: gcc / g++, make, ncurses-dev (when installed, a note from apt-get said that was selected libncurses5-dev), doxygen, iasl, gdb, flex and bison, used git for coreboot and FILO and, following instructions, tried to build libpayload. When I run "make menuconfig", I can set options and write them to . config, obtaining the following output: (‘comando non trovato’ means ‘command not found’) michele@pcscratch01:~/coreboot/payloads/libpayload$ sudo make menuconfig [sudo] password for michele: /bin/sh: -print-libgcc-file-name: comando non trovato /bin/sh: -print-libgcc-file-name: comando non trovato # # configuration written to .config # *** End of libpayload configuration. *** Execute 'make' to build or try 'make help'. When I try to run "make install" (or "make"), the output is: michele@pcscratch01:~/coreboot/payloads/libpayload$ sudo make install /bin/sh: -print-libgcc-file-name: comando non trovato /bin/sh: -print-libgcc-file-name: comando non trovato build/libpayload-config.h build/config.h differenza: byte 92, riga 4 CC libpci/libpci.libpci.o make: MMD: comando non trovato AR build/libpci.a make: rc: comando non trovato make: *** [build/libpci.a] Errore 127 And here I stopped. I googled to find some indication, and all I could find is to delete sh link and recreate it pointing to /bin/bash. I'm not expert in Linux world, nor in programming, and I discovered coreboot just because I'm looking for a new BIOS for my motherboard, so I really need for a little help. Thanks in advice for every suggestion you could give to me. Regards Michele Montani

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Change vga bios timing
by Piero Aug. 30, 2013

Aug. 30, 2013

Hi all, After some search on internet and on the coreboot wiki and forum, I decided to buy the E350m1 Asrock motherboard that seems to be full supported from coreboot community. But I'd like to modify the bios and/or the vgabios to use with an old CGA/EGA monitors that work with an HSYNC at (about) 15kHz despite the VGA at 31kHz. I found some interesting project on internet (1 free and 1 commercial), i.e. : http://tinyurl.com/r6n4l where the author has modified the Award 4.51pg bios to replace the vga table written by the video card in RAM with a modified version (different vgatable timings). Or i.e. this commercial project: http://tinyurl.com/mgcqnar where the author has modified the ati bios to force the card to work at other horizontal frequencies. I'd like to ask you if it is possible to do with coreboot the first example above. Somebody can advise me where to start? Now, I'm following the second example above in fact, I started to disassembly the AsRock E350m1 video bios (pci10029802.rom) and I identified the asm code part where the resolutions are set; but at the moment I was not able to find the vga table inside the hex in order to change the timing. Some help? :) Thank you very much Bye

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