September 2012 - coreboot - mail.coreboot.org

#95: Run coreboot in VirtualBox
by coreboot Dec. 10, 2014

Dec. 10, 2014

#95: Run coreboot in VirtualBox ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: misc | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ It would be nice if we could test coreboot images in VirtualBox, see http://virtualbox.org/. VirtualBox does not (yet) provide a simple mechanism to use a different BIOS in their emulated machines (something like "-L" in qemu). Instead the BIOS image (a custom bochs BIOS + LGPL'g VGABIOS) is converted to C code (an array of bytes, or the like) and merged into the VirtualBox executable. The relevant files are {{{ src/VBox/Devices/PC/DevPcBios.cpp bldprogs/bin2c.c }}} if someone want to hack VirtualBox to easily support using coreboot images instead of their usual BIOS. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/95> coreboot <http://www.coreboot.org/>

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EHCI debug port finder
by Carl-Daniel Hailfinger May 30, 2014

May 30, 2014

I wanted to know which physical port of my multiple USB controllers have the debug capability. There was no way to find that easily, so I created a tool which will do most of the work for the user. Example output: The following PCI devices support a USB debug port (says lspci): 0000:00:1d.7 The following PCI devices support a USB debug port (says the kernel): 0000:00:1d.7 PCI device 0000:00:1d.7, USB bus 3, USB physical port 1 Currently connected high-speed devices: /: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=ehci_hcd/6p, 480M |__ Port 2: Dev 20, If 0, Class=stor., Driver=usb-storage, 480M The output can be improved, but it's a good start. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Dual SPI Flash adapter attempt 2.0
by Oliver Schinagl March 9, 2014

March 9, 2014

Hi list(s), Here's my second attempt at routing the previously mailed png of my schema. It was a lot trickier to route then my previous version, but I think it worked out! As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1 should be 10k or ideally 100k, as Peter mentioned earlier. Hopefully there's no obvious mistakes and can start working on alternative layouts (so it is insert-able in different angles). DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow. That said, DRC check passes when I set the copper width/distance to 7mil's instead of the current 8 mils. I'm planning on having these PCB's manufactured by Seeed studio and their minimal width is much smaller. Minimum trace width: 6mil Minimum trace/vias/pads space : 6mil Minimum silkscreen width : 4mil Minimum silkscreen text size : 32mil I've used a grid size of 10mil and distances of 8 mils, as I didn't want to rely on the minimum of seed. The silkscreen I positioned using a grid size of 5 mil's however. Not sure what they mean with a 'minimum silkscreen text size' however. Anyhow, feedback greatly appreciated, so I can start working on alternative layouts :)

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#186: 3com 3c905tx / gpxe boot problem
by coreboot Jan. 11, 2014

Jan. 11, 2014

#186: 3com 3c905tx / gpxe boot problem -----------------------------------+---------------------------------- Reporter: jeroenkrabbendam@… | Owner: stepan@… Type: defect | Status: new Priority: minor | Milestone: Component: coreboot | Keywords: gpxe Dependencies: | Patch Status: there is no patch -----------------------------------+---------------------------------- Although (or: just because) novice in the field, I encountered some problems with netbooting with coreboot. Mobo's tried: Asus P2B, VTech with bios id ITE8671-2A69KV3IC-00. All mobo's boot '''harddisk''' fine with Asus P2B / Gigabyte GA-6BX{CE} respectively. NIC ROM is started, and loads the kernel by tftp. This is vvvveeeerrrryyy slow! Although loading, the kernel is never able to start itself. Same kernel on HDU is no problem at all (GRUB2) Note: the gpxe-image is on the nic, coreboot payload is seabios. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/186> coreboot <http://www.coreboot.org/>

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unsupported mb questions (amd fam10h)
by Roman Elshin July 21, 2013

July 21, 2013

I try to get coreboot working with asrock 880g pro3 board. First problem: spd eprom say that memory ddr1600 capable, but it is not so, is there are right way to limit memory frequency at ddr1333? Other problem, may be related as machine with broken memory are very unpredictable: boot process stop with "It is not SB800 or SB810" message. I try to enable sb850 by this patch, but looks like it is not enough, most of time coreboot does not detect hdd. Sometimes in very rare case it is possible to boot from sata. Are sb850 supported by coreboot? ----------------------------------------------------------------------- diff -urN a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c --- a/src/southbridge/amd/sb800/early_setup.c 2012-07-14 19:00:40.000000000 +0400 +++ b/src/southbridge/amd/sb800/early_setup.c 2012-07-14 21:49:54.000000000 +0400 @@ -94,7 +94,10 @@ rev = REV_SB800_A11; } else if (rev_id == 0x41) { rev = REV_SB800_A12; - } else { + } else if (rev_id == 0x42) { + rev = REV_SB800_A13; + } + else { die("It is not SB800 or SB810\r\n"); } diff -urN a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h --- a/src/southbridge/amd/sb800/sb800.h 2012-07-14 19:00:40.000000000 +0400 +++ b/src/southbridge/amd/sb800/sb800.h 2012-07-14 21:49:10.000000000 +0400 @@ -48,7 +48,7 @@ #define REV_SB800_A11 0x11 #define REV_SB800_A12 0x12 - +#define REV_SB800_A13 0x13 #ifdef __PRE_RAM__ void sb800_lpc_port80(void); -------------------------------------------------------------------------

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New patch to review: 49493f5 T60: add volume CMOS setting
by gerrit＠coreboot.org Jan. 28, 2013

Jan. 28, 2013

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12 -gerrit

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new Trinity APUs supported?
by Rudolf Marek Oct. 2, 2012

Oct. 2, 2012

Hi all I'm considering to buy FM2 A10 CPU & Asus F2A85-V PRO (or some cheaper variant) http://www.asus.com/Motherboards/AMD_Socket_FM2/F2A85M_PRO/ (looks it has also serial port). The CPU is I think family 12h. I checked the coreboot sources and there seems to be only LLANO mentioned. Any clue? Thanks Rudolf

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New patch to review for coreboot: 44b1a98 Top Makefile: Fix a typo.(trivial)
by Zheng Bao Sept. 29, 2012

Sept. 29, 2012

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1552 -gerrit commit 44b1a98f75ccf2e1de88b0ef0b2ac4d1b54bd124 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Sat Sep 29 11:21:29 2012 +0800 Top Makefile: Fix a typo.(trivial) Change-Id: I7e5b1e2c2e8e7d8a64f6859925f8e2eab4e2b80b Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 63c0403..0d159ef 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -272,7 +272,7 @@ update: dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF lint lint-stable: - FAILED=0; LINTLOG=`mktemp .tmpconfig.lintXXXXX`; \ + FAILED=0; LINTLOG=`mktemp.tmpconfig.lintXXXXX`; \ for script in util/lint/$@-*; do \ echo; echo `basename $$script`; \ grep "^# DESCR:" $$script | sed "s,.*DESCR: *,," ; \

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boards
by ron minnich Sept. 28, 2012

Sept. 28, 2012

the latinaware conference is going to let us run a workshop and we're going to help people bring up coreboot. I really appreciate carl-daniel's helpful recommendation, but I worry that it's not confirmed. People are willing to commit to buying something for the workshop but we have to confirm it. Requirements: - has to work. Really, really has to work. That means not only that it's the right mainboard, but we know the vendor has not recently made some change that will make it not work. This happens a lot. So, please, if you have a recommendation let's make sure that it's with a recent purchase. - has to be available in argentina, and + if brazil too. Thanks, I hope we can find something. Our first idea (chromebooks) did not work out due to lack of availability. ron

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Patch merged into coreboot/master: f11e706 build.h: Re-run hostname if it doesn't take '-s' option.
by gerrit＠coreboot.org Sept. 28, 2012

Sept. 28, 2012

the following patch was just integrated into master: commit f11e706dcf93e0f8c87191ab99622fa55959786e Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Fri Sep 28 16:06:44 2012 +0800 build.h: Re-run hostname if it doesn't take '-s' option. Cygwin's hostname comes from coreutils, which does not support all the options that some other hostname implementations provide. Change-Id: Ia6bd9157c351f440ad225046638a6bf3f9cfba11 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Sep 28 14:50:37 2012, giving +2 See http://review.coreboot.org/1546 for details. -gerrit

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