June 2012 - coreboot - mail.coreboot.org

How to make graphical issue go away with 4GB of ram
by Denis 'GNUtoo' Carikli June 30, 2012

June 30, 2012

Hi, me and Kyösti Mälkki(kmalkki on IRC) figured out how to workarround the following problem: If I installed 4GB of ram in the m4a785t-m the screen comes up,however it's black. If I only installed 2GB of ram it worked fine. I made a patch(I'll send it right after that email) but it seem to break graphics for the case where 2GB of ram is installed. So I wonder what would be the correct fix(a fix that would work for every cases). Explanation of the patch that will be sent right after the mail: "basek - mmio_basek;" should be 1048576 (1G): According to Kyösti Mälkki the correct value for the sizek is 1048576. So I looked for what could create that size and found that. I'm not convinced that "basek - mmio_basek" is the right fix but at least we're in the right direction. Denis.

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New patch to review for coreboot: f3e0919 msrtool: Added Intel Nehalem and Sandybridge MSRs
by Anton Kochkov June 30, 2012

June 30, 2012

Anton Kochkov (anton.kochkov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1153 -gerrit commit f3e0919dc053b50da3a1ba61a7417aa41d9508ef Author: Anton Kochkov <anton.kochkov(a)gmail.com> Date: Sat Jun 30 22:36:44 2012 +0400 msrtool: Added Intel Nehalem and Sandybridge MSRs Added MSRs definitions for Nehalem Intel CPUs and some stubs for Sandybridge Intel CPU. Change-Id: I35e464ba6c9aef97630279bac83f2944fa46a182 Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> --- util/msrtool/Makefile.in | 2 +- util/msrtool/intel_nehalem.c | 2010 ++++++++++++++++++++++++++++++++++++++ util/msrtool/intel_sandybridge.c | 538 ++++++++++ util/msrtool/msrtool.c | 2 + util/msrtool/msrtool.h | 8 + 5 files changed, 2559 insertions(+), 1 deletions(-) diff --git a/util/msrtool/Makefile.in b/util/msrtool/Makefile.in index bf9012e..9d1e67f 100644 --- a/util/msrtool/Makefile.in +++ b/util/msrtool/Makefile.in @@ -26,7 +26,7 @@ PREFIX = @PREFIX@ CFLAGS = @CFLAGS@ -fno-pic LDFLAGS = @LDFLAGS@ -TARGETS = geodegx2.o geodelx.o cs5536.o k8.o intel_pentium3_early.o intel_pentium3.o intel_pentium4_early.o intel_pentium4_later.o intel_core1.o intel_core2_early.o intel_core2_later.o +TARGETS = geodegx2.o geodelx.o cs5536.o k8.o intel_pentium3_early.o intel_pentium3.o intel_pentium4_early.o intel_pentium4_later.o intel_core1.o intel_core2_early.o intel_core2_later.o intel_nehalem.o intel_sandybridge.o SYSTEMS = linux.o darwin.o freebsd.o OBJS = $(PROGRAM).o msrutils.o sys.o $(SYSTEMS) $(TARGETS) diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c new file mode 100644 index 0000000..ebe5d2c --- /dev/null +++ b/util/msrtool/intel_nehalem.c @@ -0,0 +1,2010 @@ +/* + * This file is part of msrtool. + * + * Copyright (C) 2012 Anton Kochkov <anton.kochkov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "msrtool.h" + +int intel_nehalem_probe(const struct targetdef *target) { + struct cpuid_t *id = cpuid(); + return ((0x6 == id->family)&( + (0x1a == id->model) | + (0x1e == id->model) | + (0x1f == id->model) | + (0x2f == id->model) + )); +} + +const struct msrdef intel_nehalem_msrs[] = { + {0x11, MSRTYPE_RDWR, MSR2(0,0), "MSR_BBL_CR_CTL3", "", { + { BITS_EOT } + }}, + {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID Register", + "Model Specific Platform ID", { + { 63, 11, RESERVED }, + { 52, 3, RESERVED }, + { 49, 37, RESERVED }, + { 12, 5, "Maximum Qualified Ratio:", "The maximum allowed bus ratio", + PRESENT_DEC, { + { BITVAL_EOT } + }}, + { 7, 8, RESERVED }, + { BITS_EOT } + }}, + { 0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON Register", + "Processor Hard Power-On Configuration", { + { 63, 41, RESERVED }, + { 26, 5, "Integer Bus Frequency Ratio:", "R/O", PRESENT_DEC, { + { BITVAL_EOT } + }}, + { 21, 2, "Symmetric Arbitration ID:", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 1, RESERVED }, + { 18, 1, "N/2:", "Non-integer bus ratio", PRESENT_DEC, { + { MSR1(0), "Integer ratio" }, + { MSR1(1), "Non-integer ratio" }, + { BITVAL_EOT } + }}, + { 17, 2, "APIC Cluster ID:", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 15, 1, RESERVED }, + { 14, 1, "1 Mbyte Power on Reset Vector", "R/O", PRESENT_DEC, { + { MSR1(0), "4 GBytes Power on Reset Vector" }, + { MSR1(1), "1 Mbyte Power on Reset Vector" }, + { BITVAL_EOT } + }}, + { 13, 1, RESERVED }, + { 12, 1, "BINIT# Observation", "R/O", PRESENT_DEC, { + { MSR1(0), "BINIT# Observation disabled" }, + { MSR1(1), "BINIT# Observation enabled" }, + { BITVAL_EOT } + }}, + { 11, 1, "TXT", "Intel TXT Capable Chipset", PRESENT_DEC, { + { MSR1(0), "Intel TXT Capable Chipset not present" }, + { MSR1(1), "Intel TXT Capable Chipset present" }, + { BITVAL_EOT } + }}, + { 10, 1, "MCERR# Observation:", "R/O", PRESENT_DEC, { + { MSR1(0), "MCERR# Observation disabled" }, + { MSR1(1), "MCERR# Observation enabled" }, + { BITVAL_EOT } + }}, + { 9, 1, "Execute BIST", "R/O", PRESENT_DEC, { + { MSR1(0), "Execute BIST disabled" }, + { MSR1(1), "Execute BIST enabled" }, + { BITVAL_EOT } + }}, + { 8, 1, "Output Tri-state", "R/O", PRESENT_DEC, { + { MSR1(0), "Output Tri-state disabled" }, + { MSR1(1), "Output Tri-state enabled" }, + { BITVAL_EOT } + }}, + { 7, 1, "BINIT# Driver Enable", "R/W", PRESENT_DEC, { + { MSR1(0), "BINIT# Driver disabled" }, + { MSR1(1), "BINIT# Driver enabled" }, + { BITVAL_EOT } + }}, + { 6, 2, RESERVED }, + { 4, 1, "Address parity enable", "R/W", PRESENT_DEC, { + { MSR1(0), "Address parity disabled" }, + { MSR1(1), "Address parity enabled" }, + { BITVAL_EOT } + }}, + { 3, 1, "MCERR# Driver Enable", "R/W", PRESENT_DEC, { + { MSR1(0), "MCERR# Driver disabled" }, + { MSR1(1), "MCERR# Driver enabled" }, + { BITVAL_EOT } + }}, + { 2, 1, "Response error checking enable", "R/W", PRESENT_DEC, { + { MSR1(0), "Response Error Checking disabled" }, + { MSR1(1), "Response Error Checking enabled" }, + { BITVAL_EOT } + }}, + { 1, 1, "Data error checking enable", "R/W", PRESENT_DEC, { + { MSR1(0), "Data error checking disabled" }, + { MSR1(1), "Data error checking enabled" }, + { BITVAL_EOT } + }}, + { 0, 1, RESERVED }, + { BITS_EOT } + }}, + {0xcd, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_FREQ", "", { + { BITS_EOT } + }}, + {0xce, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PLATFORM_INFO", "", { + { 63, 16, RESERVED }, + { 47, 8, "Maximum Efficiency Ratio", "R/O", PRESENT_DEC, { + { BITVAL_EOT } + }}, + { 39, 10, RESERVED }, + { 29, 1, "Programmable TDC-TDP Limit for Turbo Mode", "R/O", PRESENT_DEC, { + { MSR1(0), "TDC and TDP Limits for Turbo Mode are not programmable" }, + { MSR1(1), "TDC and TDP Limits for Turbo Mode are programmable" }, + { BITVAL_EOT } + }}, + { 28, 1, "Programmable Ratio Limit for Turbo Mode", "R/O", PRESENT_DEC, { + { MSR1(0), "Programmable Ratio Limit for Turbo Mode is disabled" }, + { MSR1(1), "Programmable Ratio Limit for Turbo Mode is enabled" }, + { BITVAL_EOT } + }}, + { 27, 12, RESERVED }, + { 15, 8, "Maximum Non-Turbo Ratio", "R/O", PRESENT_DEC, { + /* The is ratio of the frequency that invariant TSC runs at. The invariant + * TSC requency can be computed by multipying this ratio by 133.33 Mhz + */ + { BITVAL_EOT } + }}, + { 7, 8, RESERVED }, + { BITS_EOT } + }}, + /* FIXME: There is already two 0x1ad MSRs for Nehalem in the + * Intel 64 and IA-32 Architectures Software Developer's Manual + * Volume 3C 34-91. So, we choose first, second 0x1ad MSR + * MSR_TURBO_RATIO_LIMIT is commented now. + */ + {0x1ad, MSRTYPE_RDWR, MSR2(0,0), "MSR_TURBO_POWER_CURRENT_LIMIT", "", { + { 63, 32, RESERVED }, + { 31, 1, "TDC Limit Override Enable", "R/W", PRESENT_BIN, { + { MSR1(0), "TDC Limit Override is not active" }, + { MSR1(1), "TDC Limit Override is active" }, + { BITVAL_EOT } + }}, + { 30, 15, "TDC Limit", "R/W", PRESENT_HEX, { + /* TDC Limit in 1/8 Amp granularity */ + { BITVAL_EOT } + }}, + { 15, 1, "TDP Limit Override Enable", "R/W", PRESENT_BIN, { + { MSR1(0), "TDP Limit Override is not active" }, + { MSR1(1), "TDP Limit Override is active" }, + { BITVAL_EOT } + }}, + { 14, 15, "TDP Limit", "R/W", PRESENT_HEX, { + /* TDP Limit in 1/8 Watt granularity */ + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, +/* + {0x1ad, MSRTYPE_RDWR, MSR2(0,0), "MSR_TURBO_RATIO_LIMIT", + "Maximum Ratio Limit of Turbo Mode", { + // "RO" if MSR_PLATFORM_INFO.[28] = 0 + // "RW" if MSR_PLATFORM_INFO.[23] = 1 + { 63, 32, RESERVED }, + { 31, 8, "Maximum Ratio Limit for 4C", "R/O", PRESENT_HEX, { + // Maximum Turbo Ratio Limit of 4 core active + { BITVAL_EOT } + }}, + { 23, 8, "Maximum Ratio Limit for 3C", "R/O", PRESENT_HEX, { + // Maximum Turbo Ratio Limit of 3 core active + { BITVAL_EOT } + }}, + { 15, 8, "Maximum Ratio Limit for 2C", "R/O", PRESENT_HEX, { + // Maximum Turbo Ratio Limit of 2 core active + { BITVAL_EOT } + }}, + { 7, 8, "Maximum Ratio Limit for 1C", "R/O", PRESENT_HEX, { + // Maximum Turbo Ratio Limit of 1 core active + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, +*/ + {0x280, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL2", "", { + { 63, 33, RESERVED }, + { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 29, 15, RESERVED }, + { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x281, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL2", "", { + { 63, 33, RESERVED }, + { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 29, 15, RESERVED }, + { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x286, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_CTL2", "", { + { 63, 33, RESERVED }, + { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 29, 15, RESERVED }, + { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x287, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC7_CTL2", "", { + { 63, 33, RESERVED }, + { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 29, 15, RESERVED }, + { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x288, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC8_CTL2", "", { + { 63, 33, RESERVED }, + { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 29, 15, RESERVED }, + { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x3f8, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PKG_C3_RESIDENCY", "", { + { 63, 64, "Package C3 Residency Counter", "R/O", PRESENT_DEC, { + /* Value since last reset that this package is in C3 states. + * Count at the same frequency as the TSC. + */ + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x3f9, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PKG_C6_RESIDENCY", "", { + { BITS_EOT } + }}, + {0x3fa, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PKG_C7_RESIDENCY", "", { + { BITS_EOT } + }}, + {0x418, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_CTL", "", { + { BITS_EOT } + }}, + {0x419, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_STATUS", "", { + { BITS_EOT } + }}, + {0x41a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_ADDR", "", { + { BITS_EOT } + }}, + {0x41b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_MISC", "", { + { BITS_EOT } + }}, + {0x41c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC7_CTL", "", { + { BITS_EOT } + }}, + {0x41d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC7_STATUS", "", { + { BITS_EOT } + }}, + {0x41e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC7_ADDR", "", { + { BITS_EOT } + }}, + {0x41f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC7_MISC", "", { + { BITS_EOT } + }}, + {0x420, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC8_CTL", "", { + { BITS_EOT } + }}, + {0x421, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC8_STATUS", "", { + { BITS_EOT } + }}, + {0x422, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC8_ADDR", "", { + { BITS_EOT } + }}, + {0x423, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC8_MISC", "", { + { BITS_EOT } + }}, + +/* ========================================================================== + * Per core MSRs + * ========================================================================== + */ + + {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", { + { BITS_EOT } + }}, + {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", { + { BITS_EOT } + }}, + {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_SIZE", "", { + { BITS_EOT } + }}, + {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "", { + { BITS_EOT } + }}, + {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { + { BITS_EOT } + }}, + {0x34, MSRTYPE_RDONLY, MSR2(0,0), "MSR_SMI_COUNT", "SMI Counter register", { + { 63, 32, RESERVED }, + { 31, 32, "SMI Count", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* if CPUID.01H: ECX[bit 5 or bit 6] = 1 */ + {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", + "Control features in Intel 64Processor", { + { 63, 48, RESERVED }, + /* if CPUID.01H: ECX[6] = 1 */ + { 15, 1, "SENTER Global Enable", "R/WL", PRESENT_BIN, { + { MSR1(0), "SENTER leaf functions are disabled" }, + { MSR1(1), "SENTER leaf functions are enabled" }, + { BITVAL_EOT } + }}, + /* if CPUID.01H: ECX[6] = 1 */ + { 14, 7, "SENTER Local Function Enables", "R/WL", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 7, 5, RESERVED }, + /* if CPUID.01H: ECX[5 or 6] = 1 */ + { 2, 1, "VMX outside of SMX operation", "R/WL", PRESENT_BIN, { + /* This bit enables VMX for system executive + * that do not require SMX. + */ + { MSR1(0), "VMX outside of SMX operation disabled" }, + { MSR1(1), "VMX outside of SMX operation enabled" }, + { BITVAL_EOT } + }}, + { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, { + /* This bit enables a system executive to use + * VMX in conjuction with SMX to support Intel + * Trusted Execution Technology. + */ + { MSR1(0), "VMX inside of SMX operation disabled" }, + { MSR1(1), "VMX outside of SMX operation enabled" }, + { BITVAL_EOT } + }}, + /* if CPUID.01H: ECX[5 or 6] = 1 */ + { 0, 1, "Lock bit", "R/WO", PRESENT_BIN, { + /* Once the Lock bit is set, the contents + * of this register cannot be modified. + * Therefore the lock bit must be set after + * configuring support for Intel Virtualization + * Technology and prior transferring control + * to an Option ROM or bootloader. Hence, once + * the lock bit is set, the entire IA32_FEATURE_CONTROL_MSR + * contents are preserved across RESET when + * PWRGOOD it not deasserted. + */ + { MSR1(0), "IA32_FEATURE_CONTROL MSR can be modified" }, + { MSR1(1), "IA32_FEATURE_CONTROL MSR cannot be modified" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x40, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", { + { BITS_EOT } + }}, + {0x41, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "", { + { BITS_EOT } + }}, + {0x42, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", { + { BITS_EOT } + }}, + {0x43, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "", { + { BITS_EOT } + }}, + {0x60, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "", { + { BITS_EOT } + }}, + {0x61, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "", { + { BITS_EOT } + }}, + {0x62, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "", { + { BITS_EOT } + }}, + {0x63, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "", { + { BITS_EOT } + }}, + {0x79, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_UPDT_TRIG", + "BIOS Update Trigger Register (W)", { + { BITS_EOT } + }}, + {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", + "BIOS Update Signature ID (RO)", { + { BITS_EOT } + }}, + {0xa0, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_BASE", "", { + { BITS_EOT } + }}, + {0xa1, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_MASK", "", { + { BITS_EOT } + }}, + {0xc1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC0", + "Performance counter register", { + { BITS_EOT } + }}, + {0xc2, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC1", + "Performance counter register", { + { BITS_EOT } + }}, + {0xc3, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC2", + "Performance counter register", { + { BITS_EOT } + }}, + {0xc4, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC3", + "Performance counter register", { + { BITS_EOT } + }}, + {0xe2, MSRTYPE_RDWR, MSR2(0,0), "MSR_PKG_CST_CONFIG_CONTROL", + "C-State Configuration Control", { + { 63, 37, RESERVED }, + { 26, 1, "C1 state auto demotion", "R/W", PRESENT_DEC, { + { MSR1(0), "Demotion of C3/C6/C7 requests to C1 is disabled" }, + { MSR1(1), "Demotion of C3/C6/C7 requests to C1 is enabled" }, + { BITVAL_EOT } + }}, + { 25, 1, "C3 state auto demotion", "R/W", PRESENT_DEC, { + { MSR1(0), "Demotion of C6/C7 requests to C3 is disabled" }, + { MSR1(1), "Demotion of C6/C7 requests to C3 is enabled" }, + { BITVAL_EOT } + }}, + { 24, 1, "Interrupt filtering enabled/disabled", "R/W", PRESENT_DEC, { + { MSR1(0), "All CPU cores in deep C-State will wake for an \ + event message" }, + { MSR1(1), "CPU in deep C-State will wake only when the event \ + message is destined for that core" }, + { BITVAL_EOT } + }}, + { 23, 8, RESERVED }, + { 15, 1, "CFG Lock", "R/WO", PRESENT_DEC, { + { MSR1(0), "[15:0] bits of MSR_PKG_CST_CONFIG_CONTROL(0xe2) \ + are writeable" }, + { MSR1(1), "[15:0] bits of MSR_PKG_CST_CONFIG_CONTROL(0xe2) \ + are locked until reset" }, + { BITVAL_EOT } + }}, + { 14, 4, RESERVED }, + { 10, 1, "I/O MWAIT Redirection", "R/W", PRESENT_DEC, { + { MSR1(0), "I/O MWAIT Redirection disabled" }, + { MSR1(1), "CPU will map IO_read instructions sent to \ + IO register specified by MSR_PMG_IO_CAPTURE_BASE \ + to MWAIT instructions" }, + { BITVAL_EOT } + }}, + { 9, 7, RESERVED }, + { 2, 3, "Package C-State limit", "R/W", PRESENT_BIN, { + /* Specifies the lowest processor specific C-state code name + * (consuming the least power) for the package. The default is set + * as factory-configured package C-state limit. + */ + { MSR1(0), "C0 (no package C-state support)" }, + { MSR1(1), "C1 (behavior is the same as C0)" }, + { MSR1(2), "C3" }, + { MSR1(3), "C6" }, + { MSR1(4), "C7" }, + { MSR1(5), "Reserved" }, + { MSR1(6), "Reserved" }, + { MSR1(7), "No package C-state limit" }, + { BITVAL_EOT } + /* Note: this field cannot be used to limit + * package C-state to C3 + */ + }}, + { BITS_EOT } + }}, + {0xe4, MSRTYPE_RDWR, MSR2(0,0), "MSR_PMG_IO_CAPTURE_BASE", + "Power Management IO Redirection in C-state", { + { 63, 45, RESERVED }, + { 18, 3, "C-state Range", "R/W", PRESENT_BIN, { + /* Specifies the encoding value of the maximum C-State code name + * to be included when IO read to MWAIT redirection is enabled by + * MSR_PMG_CST_CONFIG_CONTROL[bit10]. + */ + { MSR1(0), "C3 is the max C-State to include" }, + { MSR1(1), "C6 is the max C-State to include" }, + { MSR1(2), "C7 is the max C-State to include" }, + { BITVAL_EOT } + }}, + { 15, 16, "LVL_2 Base Address", "R/W", PRESENT_HEX, { + /* Specifies the base address visible to software for IO redirection. + * If I/O MWAIT Redirection is enabled, reads to this address will be + * consumed by the power management logic and decoded to MWAIT + * instructions. When IO port address redirection is enabled, + * this is the I/O port address reported to the OS/software. + */ + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", { + { BITS_EOT } + }}, + {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", { + { BITS_EOT } + }}, + {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + { BITS_EOT } + }}, + {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { + { BITS_EOT } + }}, + {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { + { BITS_EOT } + }}, + {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { + { BITS_EOT } + }}, + {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + { BITS_EOT } + }}, + {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + { 63, 61, RESERVED }, + { 2, 1, "MCIP", "R/W", PRESENT_DEC, { + /* When set, bit indicates that a machine check has been + * generated. If a second machine check is detected while + * this bit is still set, the processor enters a shutdown state. + * Software should write this bit to 0 after processing + * a machine check exception. + */ + { MSR1(0), "Nothing" }, + { MSR1(1), "Machine check has been generated" }, + { BITVAL_EOT } + }}, + { 1, 1, "EPIV", "R/W", PRESENT_DEC, { + /* When set, bit indicates that the instruction addressed + * by the instruction pointer pushed on the stack (when + * the machine check was generated) is directly associated + * with the error + */ + { MSR1(0), "Nothing" }, + { MSR1(1), "Instruction addressed directly associated with the error" }, + { BITVAL_EOT } + }}, + { 0, 1, "RIPV", "R/W", PRESENT_DEC, { + /* When set, bit indicates that the instruction addressed + * by the instruction pointer pushed on the stack (when + * the machine check was generated) can be used to restart + * the program. If cleared, the program cannot be reliably restarted + */ + { MSR1(0), "Program cannot be reliably restarted" }, + { MSR1(1), "Instruction addressed can be used to restart the program" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", "", { + { BITS_EOT } + }}, + {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", "", { + { BITS_EOT } + }}, + {0x188, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL2", "", { + { BITS_EOT } + }}, + {0x189, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL3", "", { + { BITS_EOT } + }}, + {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + { 63, 48, RESERVED }, + { 15, 16, "Current Performance State Value", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", { + { BITS_EOT } + }}, + {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", + "Clock Modulation", { + { 63, 59, RESERVED }, + { 4, 1, "On demand Clock Modulation", "R/W", PRESENT_BIN, { + { MSR1(0), "On demand Clock Modulation is disabled" }, + { MSR1(1), "On demand Clock Modulation is enabled" }, + { BITVAL_EOT } + }}, + { 3, 3, "On demand Clock Modulation Duty Cycle", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 0, 1, RESERVED }, + { BITS_EOT } + }}, + {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", + "Thermal Interrupt Control", { + { BITS_EOT } + }}, + {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", + "Thermal Monitor Status", { + { BITS_EOT } + }}, + {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { + { BITS_EOT } + }}, + {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", + "Enable miscellaneous processor features", { + { 63, 25, RESERVED }, + /* Note: [38] bit using for whole package, + * while some other bits can be Core or Thread + * specific. + */ + { 38, 1, "Turbo Mode", "R/W", PRESENT_BIN, { + /* When set to a 0 on processors that support IDA, + * CPUID.06H: EAX[1] reports the processor's + * support of turbo mode is enabled. + */ + { MSR1(0), "Turbo Mode enabled" }, + /* When set 1 on processors that support Intel Turbo Boost + * technology, the turbo mode feature is disabled and + * the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). + */ + { MSR1(1), "Turbo Mode disabled" }, + { BITVAL_EOT } + /* Note: the power-on default value is used by BIOS to detect + * hardware support of turbo mode. If power-on default value is 1, + * turbo mode is available in the processor. If power-on default + * value is 0, turbo mode not available. + */ + }}, + { 37, 3, RESERVED }, + { 34, 1, "XD Bit Disable", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 33, 10, RESERVED }, + { 23, 1, "xTPR Message Disable", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 22, 1, "Limit CPUID Maxval", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 21, 3, RESERVED }, + { 18, 1, "Enable Monitor FSM", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 17, 1, "UNDOCUMENTED", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* Note: [16] bit using for whole package, + * while some other bits can be Core or Thread + * specific. + */ + { 16, 1, "Enhanced Intel SpeedStep Technology Enable", "R/W", + PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 15, 3, RESERVED }, + { 12, 1, "Precise Event Based Sampling Unavailable", "R/O", + PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 11, 1, "Branch Trace Storage Unavailable", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 10, 3, RESERVED }, + { 7, 1, "Performance Monitoring Available", "R", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 6, 3, RESERVED }, + { 3, 1, "Automatic Thermal Control Circuit Enable", "R/W" + , PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 2, 2, RESERVED }, + { 0, 1, "Fast-Strings Enable", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x1a2, MSRTYPE_RDWR, MSR2(0,0), "MSR_TEMPERATURE_TARGET", "", { + { 63, 40, RESERVED }, + { 23, 8, "Temperature Target", "R", PRESENT_DEC, { + /* The minimum temperature at which PROCHOT# will be + * asserted. The value in degree C. + */ + { BITVAL_EOT } + }}, + { 15, 16, RESERVED }, + { BITS_EOT } + }}, + {0x1a6, MSRTYPE_RDWR, MSR2(0,0), "MSR_OFFCORE_RSP_O", + "Offcore Response Event Select Register", { + { BITS_EOT } + }}, + {0x1aa, MSRTYPE_RDWR, MSR2(0,0), "MSR_MISC_PWR_MGMT", "", { + { 63, 62, RESERVED }, + { 1, 1, "Energy/Performance Bias Enable", "R/W", PRESENT_BIN, { + /* This bit status is also reflected + * by CPUID.(EAX=06h):ECX[3] + */ + { MSR1(0), "IA32_ENERGY_PERF_BIAS (0x1b0) is invisible \ + for Ring 0 software" }, + { MSR1(1), "IA32_ENERGY_PERF_BIAS (0x1b0) accessible \ + by Ring 0 software" }, + { BITVAL_EOT } + }}, + { 0, 1, "EIST Hardware Coordination Disable", "R/W", PRESENT_BIN, { + { MSR1(0), "Hardware Coordination of EIST request \ + from processor cores is enabled" }, + { MSR1(1), "Hardware Coordination of EIST request \ + from processor cores is disabled" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x1c8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LBR_SELECT", + "Last Branch Record Filtering Select Register", { + /* "Nehalem support filtering of LBR based on combination of CPL + * and branch type conditions. When LBR filtering is enabled, + * the LBR stack only captures the subset of branches + * that are specified by MSR_LBR_SELECT." + * + * -- Section 17.6.2 of Intel 64 and IA-32 Architectures Software + * Developer's Manual, Volume 3 + */ + { BITS_EOT } + }}, + {0x1c9, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LASTBRANCH_TOS", + "Last Branch Record Stack TOS", { + /* Contains an index (bits 0-3) that points to the MSR containing + * the most recent branch record. See also MSR_LASTBRANCH_0_FROM_IP (0x680). + */ + { BITS_EOT } + }}, + {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", + "Debug/Trace/Profile Resource Control", { + /* (MSR_DEBUGCTTLA, MSR_DEBUGCTLB) */ + { 63, 49, RESERVED }, + /* Only if IA32_PERF_CAPABILITIES[12] = 1 */ + { 14, 1, "FREEZE_WHILE_SMM", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Freeze perfmon and trace messages while in SMM" }, + { BITVAL_EOT } + }}, + { 13, 1, "ENABLE_UNCORE_PMI", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Logical processor can receive and generate PMI \ + on behalf of the uncore" }, + { BITVAL_EOT } + }}, + /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ + { 12, 1, "FREEZE_PERFMON_ON_PMI", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Each ENABLE bit of the global counter control MSR \ + are frozen (address 0x3bf) on PMI request" }, + { BITVAL_EOT } + }}, + /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ + { 11, 1, "FREEZE_LBRS_ON_PMI", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "LBR stack is frozen on PMI request" }, + { BITVAL_EOT } + }}, + { 10, 1, "BTS_OFF_USR", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "BTS or BTM is skipped if CPL > 0" }, + { BITVAL_EOT } + }}, + { 9, 1, "BTS_OFF_OS", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "BTS or BTM is skipped if CPL = 0" }, + { BITVAL_EOT } + }}, + { 8, 1, "BTINT", "R/O", PRESENT_BIN, { + { MSR1(0), "BTMs are logged in a BTS buffer in circular fashion" }, + { MSR1(1), "An interrupt is generated by the BTS facility \ + when the BTS buffer is full" }, + { BITVAL_EOT } + }}, + { 7, 1, "BTS", "R/O", PRESENT_BIN, { + { MSR1(0), "Logging of BTMs (branch trace messages) \ + in BTS buffer is disabled" }, + { MSR1(1), "Logging of BTMs (branch trace messages) \ + in BTS buffer is enabled" }, + { BITVAL_EOT } + }}, + { 6, 1, "TR", "R/O", PRESENT_BIN, { + { MSR1(0), "Branch trace messages are disabled" }, + { MSR1(1), "Branch trace messages are enabled" }, + { BITVAL_EOT } + }}, + { 5, 4, RESERVED }, + { 1, 1, "BTF", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Enabled treating EFLAGS.TF as single-step on \ + branches instead of single-step on instructions" }, + { BITVAL_EOT } + }}, + { 0, 1, "LBR", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Enabled recording a running trace of the most \ + recent branches taken by the processor in the LBR stack" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x1dd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LER_FROM_LIP", + "Last Exception Record From Linear IP", { + /* Contains a pointer to the last branch instruction + * that the processor executed prior to the last exception + * that was generated or the last interrupt that was handled. + */ + { BITS_EOT } + }}, + {0x1de, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LER_TO_LIP", + "Last Exception Record To Linear IP", { + /* This area contains a pointer to the target of the + * last branch instruction that the processor executed + * prior to the last exception that was generated or + * the last interrupt that was handled + */ + { BITS_EOT } + }}, + {0x1f2, MSRTYPE_RDONLY, MSR2(0,0), "IA32_SMRR_PHYS_BASE", + "SMRR Base Address", { + /* Base address of SMM memory range. + * Writeable only in SMM, so marking it as read-only */ + { 63, 32, RESERVED }, + { 31, 20, "SMRR physical Base Address", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 11, 4, RESERVED }, + { 7, 8, "Memory type of the range", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x1f3, MSRTYPE_RDONLY, MSR2(0,0), "IA32_SMRR_PHYS_MASK", + "SMRR Range Mask", { + /* Range Mask of SMM memory range. + * Writeable only in SMM, so marking it as read-only */ + { 63, 32, RESERVED }, + { 31, 20, "SMRR address range mask", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 11, 1, "Is Valid SMRR range mask", "R/O", PRESENT_BIN, { + { MSR1(0), "SMRR range mask is disabled" }, + { MSR1(1), "SMRR range mask is enabled" }, + { BITVAL_EOT } + }}, + { 10, 11, RESERVED }, + { BITS_EOT } + }}, + {0x1f8, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PLATFORM_DCA_CAP", + "DCA Capability", { + { BITS_EOT } + }}, + {0x1f9, MSRTYPE_RDONLY, MSR2(0,0), "IA32_CPU_DCA_CAP", + "Support og Prefetch-Hint type", { + /* If set, CPU supports Prefetch-Hint type. + * TODO: As it is undocumented, which bit (or bits) + * are needed to "be set", we need collect some + * outputs of msrtool to understand possible msr values. + */ + { BITS_EOT } + }}, + {0x1fa, MSRTYPE_RDWR, MSR2(0,0), "IA32_DCA_0_CAP", + "DCA type 0 Status and Control register", { + /* This register defined as introduced only + * in 06_2EH Nehalem model (latest), so be careful! + */ + { 31, 5, RESERVED }, + { 26, 1, "HW_BLOCK", "R/O", PRESENT_BIN, { + /* Hardware block of DCA */ + { MSR1(0), "DCA is not blocked by HW" }, + { MSR1(1), "DCA is blocked by HW (e.g. CR0.CD=1)" }, + { BITVAL_EOT } + }}, + { 25, 1, RESERVED }, + { 24, 1, "SW_BLOCK", "R/W", PRESENT_BIN, { + /* Software block of DCA */ + { MSR1(0), "DCA is not blocked by SW" }, + { MSR1(1), "DCA is blocked by SW" }, + { BITVAL_EOT } + }}, + { 23, 7, RESERVED }, + { 16, 4, "DCA_RELAY", "R/W", PRESENT_HEX, { + /* Writes will update the register + * but have no HW side-effect */ + { BITVAL_EOT } + }}, + { 12, 2, RESERVED }, + { 10, 4, "DCA_QUEUE_SIZE", "R/O", PRESENT_DEC, { + { BITVAL_EOT } + }}, + { 6, 4, "DCA_TYPE", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 2, 2, "TRANSACTION", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 0, 1, "DCA_ACTIVE", "R/O", PRESENT_BIN, { + /* Set by HW when DCA is fuse-enabled and + * no defeauteres are set */ + { MSR1(0), "DCA inactive" }, + { MSR1(1), "DCA inactive" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x1fc, MSRTYPE_RDWR, MSR2(0,0), "MSR_POWER_CTL", + "Power Control Register", { + { 63, 62, RESERVED }, + /* Whole package bit */ + { 1, 1, "C1E Enable", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "CPU switch to the Minimum Enhaced Intel \ + SpeedStep Technology operating point when all \ + execution cores enter MWAIT (C1)" }, + { BITVAL_EOT } + }}, + { 0, 1, RESERVED }, + { BITS_EOT } + }}, + {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE0", "", { + { BITS_EOT } + }}, + {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK0", "", { + { BITS_EOT } + }}, + {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE1", "", { + { BITS_EOT } + }}, + {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK1", "", { + { BITS_EOT } + }}, + {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE2", "", { + { BITS_EOT } + }}, + {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK2", "", { + { BITS_EOT } + }}, + {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE3", "", { + { BITS_EOT } + }}, + {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK3", "", { + { BITS_EOT } + }}, + {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE4", "", { + { BITS_EOT } + }}, + {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK4", "", { + { BITS_EOT } + }}, + {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE5", "", { + { BITS_EOT } + }}, + {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK5", "", { + { BITS_EOT } + }}, + {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE6", "", { + { BITS_EOT } + }}, + {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK6", "", { + { BITS_EOT } + }}, + {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE7", "", { + { BITS_EOT } + }}, + {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK7", "", { + { BITS_EOT } + }}, + /* if IA32_MTRR_CAP[7:0] > 8 */ + {0x210, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE8", "", { + { BITS_EOT } + }}, + /* if IA32_MTRR_CAP[7:0] > 8 */ + {0x211, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK8", "", { + { BITS_EOT } + }}, + /* if IA32_MTRR_CAP[7:0] > 9 */ + {0x212, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE9", "", { + { BITS_EOT } + }}, + /* if IA32_MTRR_CAP[7:0] > 9 */ + {0x213, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK9", "", { + { BITS_EOT } + }}, + {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + { BITS_EOT } + }}, + {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + { BITS_EOT } + }}, + {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + { BITS_EOT } + }}, + {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + { BITS_EOT } + }}, + {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + { BITS_EOT } + }}, + {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + { BITS_EOT } + }}, + {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + { BITS_EOT } + }}, + {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + { BITS_EOT } + }}, + {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + { BITS_EOT } + }}, + {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + { BITS_EOT } + }}, + {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + { BITS_EOT } + }}, + {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "IA32_PAT", { + { 63, 5, RESERVED }, + { 58, 3, "PA7", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 55, 5, RESERVED }, + { 40, 3, "PA6", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 47, 5, RESERVED }, + { 42, 3, "PA5", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 39, 5, RESERVED }, + { 34, 3, "PA4", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 31, 5, RESERVED }, + { 26, 3, "PA3", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 23, 5, RESERVED }, + { 18, 3, "PA2", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 15, 5, RESERVED }, + { 10, 3, "PA1", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 7, 5, RESERVED }, + { 2, 3, "PA0", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x282, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL2", "", { + { 63, 33, RESERVED }, + { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 29, 15, RESERVED }, + { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x283, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL2", "", { + { 63, 33, RESERVED }, + { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 29, 15, RESERVED }, + { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x284, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL2", "", { + { 63, 33, RESERVED }, + { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 29, 15, RESERVED }, + { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x285, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL2", "", { + { 63, 33, RESERVED }, + { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 29, 15, RESERVED }, + { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", + "Default Memory Types", { + { 63, 52, RESERVED }, + { 11, 1, "MTRR Enable", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 10, 1, "Fixed Range MTRR Enable", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 9, 7, RESERVED }, + { 2, 3, "Default Memory Type", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* if CPUID.0AH: EDX[4:0] > 0 */ + {0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "Fixed-Function \ + Performance Counter Register 0: Counts Instr_Retired.Any", { + /* Also known as MSR_PERF_FIXED_CTR0 */ + { BITS_EOT } + }}, + /* if CPUID.0AH: EDX[4:0] > 1 */ + {0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "Fixed-Function \ + Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", { + /* Also known as MSR_PERF_FIXED_CTR1 */ + { BITS_EOT } + }}, + /* if CPUID.0AH: EDX[4:0] > 2 */ + {0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "Fixed-Function \ + Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", { + /* Also known as MSR_PERF_FIXED_CTR2 */ + { BITS_EOT } + }}, + /* if CPUID.01H: ECX[15] = 1 */ + {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { + /* Additional info available at Section 17.4.1 of + * Intel 64 and IA-32 Architecures Software Developer's + * Manual, Volume 3. + */ + { 63, 50, RESERVED }, + { 13, 1, "Counter width", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Full width of counter writable via IA32_A_PMCx" }, + { BITVAL_EOT } + }}, + { 12, 1, "SMM_FREEZE", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Freeze while SMM is supported" }, + { BITVAL_EOT } + }}, + { 11, 4, "PEBS_REC_FORMAT", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 7, 1, "PEBSSaveArchRegs", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 6, 1, "PEBS Record Format", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 5, 6, "LBR Format", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 1*/ + {0x38d, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR_CTRL", + "Fixed-Function-Counter Control Register", { + /* Also known as MSR_PERF_FIXED_CTR_CTRL. + * Counter increments while the results of ANDing respective enable bit + * in IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits + * in this MSR is true. */ + { 63, 52, RESERVED }, + { 11, 1, "EN2_PMI", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "PMI when fixed counter 2 overflows is enabled" }, + { BITVAL_EOT } + }}, + /* if CPUID.0AH EAX[7:0] > 2 */ + { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, { + { MSR1(0), "Counter only increments the associated event \ + conditions occuring in the logical processor which programmed the MSR" }, + { MSR1(1), "Counting the associated event conditions \ + occuring across all logical processors sharing a processor core" }, + { BITVAL_EOT } + }}, + { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Fixed counter 2 is enabled to count while CPL > 0" }, + { BITVAL_EOT } + }}, + { 8, 1, "EN2_OS", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Fixed counter 2 is enabled to count while CPL = 0" }, + { BITVAL_EOT } + }}, + { 7, 1, "EN1_PMI", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "PMI when fixed counter 1 overflows is enabled" }, + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 2 */ + { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, { + { MSR1(0), "Counter only increments the associated event \ + conditions occuring in the logical processor which programmed the MSR" }, + { MSR1(1), "Counting the associated event conditions \ + occuring across all logical processors sharing a processor core" }, + { BITVAL_EOT } + }}, + { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Fixed counter 1 is enabled to count while CPL > 0" }, + { BITVAL_EOT } + }}, + { 4, 1, "EN1_OS", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Fixed counter 1 is enabled to count while CPL = 0" }, + { BITVAL_EOT } + }}, + { 3, 1, "EN0_PMI", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "PMI when fixed counter 0 overflows is enabled" }, + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 2 */ + { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, { + { MSR1(0), "Counter only increments the associated event \ + conditions occuring in the logical processor which programmed the MSR" }, + { MSR1(1), "Counting the associated event conditions \ + occuring across all logical processors sharing a processor core" }, + { BITVAL_EOT } + }}, + { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Fixed counter 0 is enabled to count while CPL > 0" }, + { BITVAL_EOT } + }}, + { 0, 1, "EN0_OS", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Fixed counter 0 is enabled to count while CPL = 0" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + {0x38e, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_GLOBAL_STATUS", + "Global Performance Counter Status", { + /* Also known as MSR_PERF_GLOBAL_STATUS */ + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 63, 1, "CondChg: Status bits of this register has changed", + "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 62, 1, "OvfBuf: DS SAVE area Buffer overflow status", + "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 2 */ + { 61, 1, "Ovf_Uncore: Uncore counter overflow status", + "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 60, 26, RESERVED }, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 34, 1, "Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2", + "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 33, 1, "Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1", + "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 32, 1, "Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0", + "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 31, 28, RESERVED }, + /* presented only in 06_2EH Nehalem model */ + { 3, 1, "Ovf_PMC3: Overflow status of IA32_PMC3", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* presented only in 06_2EH Nehalem model */ + { 2, 1, "Ovf_PMC2: Overflow status of IA32_PMC2", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 1, 1, "Ovf_PMC1: Overflow status of IA32_PMC1", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 0, 1, "Ovf_PMC0: Overflow status of IA32_PMC0", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + {0x38f, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_CTL", + "Global Performance Counter Control", { + /* Counter increments while the result of ANDing respective + * enable bit in this MSR with corresponding OS or USR bits + * in general-purpose or fixed counter control MSR is true. + */ + { 63, 29, RESERVED }, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 34, 1, "EN_FIXED_CTR2", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 33, 1, "EN_FIXED_CTR1", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 32, 1, "EN_FIXED_CTR0", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 31, 30, RESERVED }, + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 1, 1, "EN_PMC1", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 0, 1, "EN_PMC0", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + {0x390, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_OVF_CTL", + "Global Performance Counter Overflow Control", { + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 63, 1, "Clear CondChg bit", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 62, 1, "Clear OvfBuf bit", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* Presented only in 06_2EH Nehalem model */ + { 61, 1, "Clear Ovf_Uncore bit", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 60, 26, RESERVED }, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 34, 1, "Clear Ovf_FIXED_CTR2 bit", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 33, 1, "Clear Ovf_FIXED_CTR1 bit", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 32, 1, "Clear Ovf_FIXED_CTR0 bit", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 31, 30, RESERVED }, + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 1, 1, "Clear Ovf_PMC1 bit", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 0, 1, "Clear Ovf_PMC0 bit", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* See Section 18.6.1.1 of Intel 64 and IA-32 Architectures + * Software Developer's Manual, Volume 3, + * "Precise Event Based Sampling (PEBS)". + */ + {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PEBS_ENABLE", "PEBS Control", { + { 63, 28, RESERVED }, + { 35, 1, "Load Latency on IA32_PMC3", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 34, 1, "Load Latency on IA32_PMC2", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 33, 1, "Load Latency on IA32_PMC1", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 32, 1, "Load Latency on IA32_PMC0", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 31, 28, RESERVED }, + { 3, 1, "PEBS on IA32_PMC3", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 2, 1, "PEBS on IA32_PMC2", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 1, 1, "PEBS on IA32_PMC1", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 0, 1, "PEBS on IA32_PMC0", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x3f6, MSRTYPE_RDWR, MSR2(0,0), "MSR_PEBS_LD_LAT", "", { + /* See Section 18.6.1.2 of Intel's manual + * for additional information. + */ + { 63, 28, RESERVED }, + { 35, 20, RESERVED }, + { 15, 16, "Minimum threshold latency value of tagged \ + load operation that will be counted", "R/W", PRESENT_DEC, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", { + { BITS_EOT } + }}, + {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", { + { BITS_EOT } + }}, + {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", { + { BITS_EOT } + }}, + {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", { + { BITS_EOT } + }}, + {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { + { BITS_EOT } + }}, + {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { + { BITS_EOT } + }}, + {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", { + { BITS_EOT } + }}, + {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", { + { BITS_EOT } + }}, + {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { + { BITS_EOT } + }}, + {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { + { BITS_EOT } + }}, + {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { + { BITS_EOT } + }}, + {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", { + { BITS_EOT } + }}, + {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + { BITS_EOT } + }}, + {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + { BITS_EOT } + }}, + {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + { BITS_EOT } + }}, + {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", { + { BITS_EOT } + }}, + {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + { BITS_EOT } + }}, + {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + { BITS_EOT } + }}, + {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + { BITS_EOT } + }}, + {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", { + { BITS_EOT } + }}, + {0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", { + { BITS_EOT } + }}, + {0x415, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_STATUS", "", { + { BITS_EOT } + }}, + {0x416, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_ADDR", "", { + { BITS_EOT } + }}, + {0x417, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_MISC", "", { + { BITS_EOT } + }}, + {0x480, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_BASIC", + "Reporting Register of Basic VMX Capabilities", { + /* Additional info available at + * Appendix A.1, "Basic VMX Information" */ + { 63, 10, RESERVED }, + { 53, 4, "Memory type for VMREAD and VMWRITE", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 49, 1, "Support of dual-treatment of system-management functions", + "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 48, 1, "Enable full linear address access", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 47, 3, RESERVED }, + { 44, 13, "VMXON region allocation size", "R/O", PRESENT_DEC, { + { BITVAL_EOT } + }}, + { 31, 32, "VMCS Revision Identifier", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x481, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PINBASED_CTLS", + "Capability Reporting Register of \ + Pin-based VM-execution Controls", { + /* Additional info available at Appendix A.3, + * "VM-Execution Controls" */ + { BITS_EOT } + }}, + {0x482, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PROCBASED_CTLS", + "Capability Reporting Register of \ + Primary Processor-based VM-execution Controls", { + /* Additional info available at Appendix A.3, + * "VM-Execution Controls" */ + { BITS_EOT } + }}, + {0x483, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_EXIT_CTLS", + "Capability Reporting Register of VM-exit Controls", { + /* Additional info available at Appendix A.4, + * "VM-Exit Controls" */ + { BITS_EOT } + }}, + {0x484, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_ENTRY_CTLS", + "Capability Reporting Register of VM-entry Controls", { + /* Additional info available at Appendix A.5, + * "VM-Entry Controls" */ + { BITS_EOT } + }}, + {0x485, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_MISC", + "Reporting Register of Miscellaneous VMX Capabilities", { + /* Additional info available at Appendix A.6, + * "Miscellaneous Data" */ + { BITS_EOT } + }}, + {0x486, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED0", + "Capability Reporting Register of CR0 Bits Fixed to 0", { + /* Additional info available at Appendix A.7, + * "VMX-Fixed Bits in CR0" */ + { BITS_EOT } + }}, + {0x487, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED1", + "Capability Reporting Register of CR0 Bits Fixed to 1", { + /* Additional info available at Appendix A.7, + * "VMX-Fixed Bits in CR0" */ + { BITS_EOT } + }}, + {0x488, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED0", + "Capability Reporting Register of CR4 Bits Fixed to 0", { + /* Additional info available at Appendix A.8, + * "VMX-Fixed Bits in CR4" */ + { BITS_EOT } + }}, + {0x489, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED1", + "Capability Reporting Register of CR4 Bits Fixed to 1", { + /* Additional info available at Appendix A.8, + * "VMX-Fixed Bits in CR4" */ + { BITS_EOT } + }}, + {0x48a, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_VMCS_ENUM", + "Capability Reporting Register of VMCS Field Enumeration", { + /* Additional info available at Appendix A.9, + * "VMCS Enumeration" */ + { BITS_EOT } + }}, + {0x48b, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2", + "Capability Reporting Register of Secondary \ + Processor-based VM-execution Controls", { + /* Additional info available at Appendix A.3, + * "VM-Execution Controls" */ + { BITS_EOT } + }}, + {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "DS Save Area", { + /* Additional info available at Section 18.10.4 of Intel 64 + * and IA-32 Architectures Software Developer's Manual, + * "Debug Store (DS) Mechanism". + */ + { 63, 32, RESERVED }, // reserved if not in IA-32e mode + { 31, 32, "Linear address of DS buffer management area", + "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + + /* Sixteen pairs + * of last branch record registers + * on the last branch record stack + */ + {0x680, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "R/W", { + { BITS_EOT } + }}, + {0x681, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "R/W", { + { BITS_EOT } + }}, + {0x682, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "R/W", { + { BITS_EOT } + }}, + {0x683, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "R/W", { + { BITS_EOT } + }}, + {0x684, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_FROM_IP", "R/W", { + { BITS_EOT } + }}, + {0x685, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_5_FROM_IP", "R/W", { + { BITS_EOT } + }}, + {0x686, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_FROM_IP", "R/W", { + { BITS_EOT } + }}, + {0x687, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_7_FROM_IP", "R/W", { + { BITS_EOT } + }}, + {0x688, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_8_FROM_IP", "R/W", { + { BITS_EOT } + }}, + {0x689, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_9_FROM_IP", "R/W", { + { BITS_EOT } + }}, + {0x68a, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_10_FROM_IP", "R/W", { + { BITS_EOT } + }}, + {0x68b, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_11_FROM_IP", "R/W", { + { BITS_EOT } + }}, + {0x68c, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_12_FROM_IP", "R/W", { + { BITS_EOT } + }}, + {0x68d, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_13_FROM_IP", "R/W", { + { BITS_EOT } + }}, + {0x68e, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_14_FROM_IP", "R/W", { + { BITS_EOT } + }}, + {0x68f, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_15_FROM_IP", "R/W", { + { BITS_EOT } + }}, + + /* Sixteen pairs + * of last branch record registers + * on the last branch record stack + */ + {0x6c0, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "R/W", { + { BITS_EOT } + }}, + {0x6c1, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "R/W", { + { BITS_EOT } + }}, + {0x6c2, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "R/W", { + { BITS_EOT } + }}, + {0x6c3, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "R/W", { + { BITS_EOT } + }}, + {0x6c4, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_TO_LIP", "R/W", { + { BITS_EOT } + }}, + {0x6c5, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_5_TO_LIP", "R/W", { + { BITS_EOT } + }}, + {0x6c6, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_TO_LIP", "R/W", { + { BITS_EOT } + }}, + {0x6c7, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_7_TO_LIP", "R/W", { + { BITS_EOT } + }}, + {0x6c8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_8_TO_LIP", "R/W", { + { BITS_EOT } + }}, + {0x6c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_9_TO_LIP", "R/W", { + { BITS_EOT } + }}, + {0x6ca, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_10_TO_LIP", "R/W", { + { BITS_EOT } + }}, + {0x6cb, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_11_TO_LIP", "R/W", { + { BITS_EOT } + }}, + {0x6cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_12_TO_LIP", "R/W", { + { BITS_EOT } + }}, + {0x6cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_13_TO_LIP", "R/W", { + { BITS_EOT } + }}, + {0x6ce, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_14_TO_LIP", "R/W", { + { BITS_EOT } + }}, + {0x6cf, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_15_TO_LIP", "R/W", { + { BITS_EOT } + }}, + + {0x802, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_APICID", + "x2APIC ID register", { + { BITS_EOT } + }}, + {0x803, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_VERSION", + "x2APIC Version register", { + { BITS_EOT } + }}, + {0x808, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_TPR", + "x2APIC Task Priority register", { + { BITS_EOT } + }}, + {0x80a, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_PPR", + "x2APIC Processor Priority register", { + { BITS_EOT } + }}, + /* + {0x80b, MSRTYPE_WRONLY, MSR2(0,0), "IA32_X2APIC_EOI", + "x2APIC EOI register", { + { BITS_EOT } + }}, + */ + {0x80d, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_LDR", + "x2APIC Logical Destination register", { + { BITS_EOT } + }}, + {0x80f, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_SIVR", + "x2APIC Spurious Interrupt Vector register", { + { BITS_EOT } + }}, + {0x810, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_0", + "x2APIC In-Service register bits [31:0]", { + { BITS_EOT } + }}, + {0x811, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_1", + "x2APIC In-Service register bits [63:32]", { + { BITS_EOT } + }}, + {0x812, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_2", + "x2APIC In-Service register bits [95:64]", { + { BITS_EOT } + }}, + {0x813, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_3", + "x2APIC In-Service register bits [127:96]", { + { BITS_EOT } + }}, + {0x814, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_4", + "x2APIC In-Service register bits [159:128]", { + { BITS_EOT } + }}, + {0x815, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_5", + "x2APIC In-Service register bits [191:160]", { + { BITS_EOT } + }}, + {0x816, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_6", + "x2APIC In-Service register bits [223:192]", { + { BITS_EOT } + }}, + {0x817, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_7", + "x2APIC In-Service register bits [255:224]", { + { BITS_EOT } + }}, + {0x818, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR0", + "x2APIC Trigger Mode register bits [31:0]", { + { BITS_EOT } + }}, + {0x819, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR1", + "x2APIC Trigger Mode register bits [63:32]", { + { BITS_EOT } + }}, + {0x81a, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR2", + "x2APIC Trigger Mode register bits [95:64]", { + { BITS_EOT } + }}, + {0x81b, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR3", + "x2APIC Trigger Mode register bits [127:96]", { + { BITS_EOT } + }}, + {0x81c, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR4", + "x2APIC Trigger Mode register bits [159:128]", { + { BITS_EOT } + }}, + {0x81d, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR5", + "x2APIC Trigger Mode register bits [191:160]", { + { BITS_EOT } + }}, + {0x81e, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR6", + "x2APIC Trigger Mode register bits [223:192]", { + { BITS_EOT } + }}, + {0x81f, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR7", + "x2APIC Trigger Mode register bits [255:224]", { + { BITS_EOT } + }}, + {0x820, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR0", + "x2APIC Interrupt Request register bits [31:0]", { + { BITS_EOT } + }}, + {0x821, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR1", + "x2APIC Trigger Mode register bits [63:32]", { + { BITS_EOT } + }}, + {0x822, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR2", + "x2APIC Trigger Mode register bits [95:64]", { + { BITS_EOT } + }}, + {0x823, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR3", + "x2APIC Trigger Mode register bits [127:96]", { + { BITS_EOT } + }}, + {0x824, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR4", + "x2APIC Trigger Mode register bits [159:128]", { + { BITS_EOT } + }}, + {0x825, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR5", + "x2APIC Trigger Mode register bits [191:160]", { + { BITS_EOT } + }}, + {0x826, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR6", + "x2APIC Trigger Mode register bits [223:192]", { + { BITS_EOT } + }}, + {0x827, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR7", + "x2APIC Trigger Mode register bits [255:224]", { + { BITS_EOT } + }}, + {0x828, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_ESR", + "x2APIC Error Status register", { + { BITS_EOT } + }}, + {0x82f, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_CMCI", + "x2APIC LVT Corrected Machine Check Interrupt register", { + { BITS_EOT } + }}, + {0x830, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_ICR", + "x2APIC Interrupt Command register", { + { BITS_EOT } + }}, + {0x832, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_TIMER", + "x2APIC LVT Timer Interrupt register", { + { BITS_EOT } + }}, + {0x833, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_THERMAL", + "x2APIC LVT Thermal Sensor Interrupt register", { + { BITS_EOT } + }}, + {0x834, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_PMI", + "x2APIC LVT Performance Monitor register", { + { BITS_EOT } + }}, + {0x835, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_LINT0", + "x2APIC LVT LINT0 register", { + { BITS_EOT } + }}, + {0x836, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_LINT1", + "x2APIC LVT LINT1 register", { + { BITS_EOT } + }}, + {0x837, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_ERROR", + "x2APIC LVT Error register", { + { BITS_EOT } + }}, + {0x838, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_INIT_COUNT", + "x2APIC Initial Count register", { + { BITS_EOT } + }}, + {0x839, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_CUR_COUNT", + "x2APIC Current Count register", { + { BITS_EOT } + }}, + {0x83e, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_DIV_CONF", + "x2APIC Divide Configuration register", { + { BITS_EOT } + }}, +/* + {0x83f, MSRTYPE_WRONLY, MSR2(0,0), "IA32_X2APIC_SELF_IPI", + "x2APIC Self IPI register", { + { BITS_EOT } + }}, +*/ + {0x107cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL0", "", { + { BITS_EOT } + }}, + {0x107cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL1", "", { + { BITS_EOT } + }}, + {0x107ce, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL2", "", { + { BITS_EOT } + }}, + {0x107cf, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL3", "", { + { BITS_EOT } + }}, + {0x107d0, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL4", "", { + { BITS_EOT } + }}, + {0x107d1, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL5", "", { + { BITS_EOT } + }}, + {0x107d2, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL6", "", { + { BITS_EOT } + }}, + {0x107d3, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL7", "", { + { BITS_EOT } + }}, + {0x107d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_GL_CTL", "", { + { BITS_EOT } + }}, + /* if CPUID.80000001H: EDX[29] = 1 or CPUID.80000001H: EDX[27] = 1 */ + {0xc0000080, MSRTYPE_RDWR, MSR2(0,0), "IA32_EFER", + "Extended Feature Enables", { + { 63, 52, RESERVED }, + { 11, 1, "Execute Disable Bit", "R/O", PRESENT_BIN, { + { MSR1(0), "NX bit disabled" }, + { MSR1(1), "NX bit enabled" }, + { BITVAL_EOT } + }}, + { 10, 1, "IA-32e Mode", "R/O", PRESENT_BIN, { + { MSR1(0), "IA-32e Mode Inactive" }, + { MSR1(1), "IA-32e Mode Active" }, + { BITVAL_EOT } + }}, + { 9, 1, RESERVED }, + { 8, 1, "IA-32e Mode Control", "R/W", PRESENT_BIN, { + /* Enable IA-32e Mode operation */ + { BITVAL_EOT } + }}, + { 7, 7, RESERVED }, + { 0, 1, "SYSCALL Control", "R/W", PRESENT_BIN, { + /* Enable SYSCALL/SYSRET instructions + * in 64-bit mode. */ + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* if CPUID.80000001H: EDX[29] = 1 */ + {0xc0000081, MSRTYPE_RDWR, MSR2(0,0), "IA32_STAR", + "System Call Target Address", { + { BITS_EOT } + }}, + /* if CPUID.80000001H: EDX[29] = 1 */ + {0xc0000082, MSRTYPE_RDWR, MSR2(0,0), "IA32_LSTAR", + "IA32e Mode System Call Target Address", { + { BITS_EOT } + }}, + /* if CPUID.80000001H: EDX[29] = 1 */ + {0xc0000084, MSRTYPE_RDWR, MSR2(0,0), "IA32_FMASK", + "System Call Flag Mask", { + { BITS_EOT } + }}, + /* if CPUID.80000001H: EDX[29] = 1 */ + {0xc0000100, MSRTYPE_RDWR, MSR2(0,0), "IA32_FS_BASE", + "Map of BASE Address of FS", { + { BITS_EOT } + }}, + /* if CPUID.80000001H: EDX[29] = 1 */ + {0xc0000101, MSRTYPE_RDWR, MSR2(0,0), "IA32_GS_BASE", + "Map of BASE Address of GS", { + { BITS_EOT } + }}, + /* if CPUID.80000001H: EDX[29] = 1 */ + {0xc0000102, MSRTYPE_RDWR, MSR2(0,0), "IA32_KERNEL_GS_BASE", + "Swap Target of BASE Address of GS", { + { BITS_EOT } + }}, + /* if CPUID.80000001H: EDX[27] = 1 */ + {0xc0000103, MSRTYPE_RDWR, MSR2(0,0), "IA32_TSC_AUX", + "AUXILIARY TSC Signature", { + { BITS_EOT } + }}, + { MSR_EOT } +}; + + diff --git a/util/msrtool/intel_sandybridge.c b/util/msrtool/intel_sandybridge.c new file mode 100644 index 0000000..0eebc96 --- /dev/null +++ b/util/msrtool/intel_sandybridge.c @@ -0,0 +1,538 @@ +/* + * This file is part of msrtool. + * + * Copyright (C) 2012 Anton Kochkov <anton.kochkov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "msrtool.h" + +int intel_sandybridge_probe(const struct targetdef *target) { + struct cpuid_t *id = cpuid(); + return ((0x6 == id->family)&( + (0x2a == id->model) | + (0x2d == id->model))); +} + +const struct msrdef intel_sandybridge_msrs[] = { + {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID Register", "Model Specific Platform ID", { + { 63, 11, RESERVED }, + { 52, 3, RESERVED }, + { 49, 37, RESERVED }, + { 12, 5, "Maximum Qualified Ratio:", "The maximum allowed bus ratio", PRESENT_DEC, { + { BITVAL_EOT } + }}, + { 7, 8, RESERVED }, + { BITS_EOT } + }}, + { 0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON Register", "Processor Hard Power-On Configuration", { + { 63, 41, RESERVED }, + { 26, 5, "Integer Bus Frequency Ratio:", "R/O", PRESENT_DEC, { + { BITVAL_EOT } + }}, + { 21, 2, "Symmetric Arbitration ID:", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 1, RESERVED }, + { 18, 1, "N/2:", "Non-integer bus ratio", PRESENT_DEC, { + { MSR1(0), "Integer ratio" }, + { MSR1(1), "Non-integer ratio" }, + { BITVAL_EOT } + }}, + { 17, 2, "APIC Cluster ID:", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 15, 1, RESERVED }, + { 14, 1, "1 Mbyte Power on Reset Vector", "R/O", PRESENT_DEC, { + { MSR1(0), "4 GBytes Power on Reset Vector" }, + { MSR1(1), "1 Mbyte Power on Reset Vector" }, + { BITVAL_EOT } + }}, + { 13, 1, RESERVED }, + { 12, 1, "BINIT# Observation", "R/O", PRESENT_DEC, { + { MSR1(0), "BINIT# Observation disabled" }, + { MSR1(1), "BINIT# Observation enabled" }, + { BITVAL_EOT } + }}, + { 11, 1, "TXT", "Intel TXT Capable Chipset", PRESENT_DEC, { + { MSR1(0), "Intel TXT Capable Chipset not present" }, + { MSR1(1), "Intel TXT Capable Chipset present" }, + { BITVAL_EOT } + }}, + { 10, 1, "MCERR# Observation:", "R/O", PRESENT_DEC, { + { MSR1(0), "MCERR# Observation disabled" }, + { MSR1(1), "MCERR# Observation enabled" }, + { BITVAL_EOT } + }}, + { 9, 1, "Execute BIST", "R/O", PRESENT_DEC, { + { MSR1(0), "Execute BIST disabled" }, + { MSR1(1), "Execute BIST enabled" }, + { BITVAL_EOT } + }}, + { 8, 1, "Output Tri-state", "R/O", PRESENT_DEC, { + { MSR1(0), "Output Tri-state disabled" }, + { MSR1(1), "Output Tri-state enabled" }, + { BITVAL_EOT } + }}, + { 7, 1, "BINIT# Driver Enable", "R/W", PRESENT_DEC, { + { MSR1(0), "BINIT# Driver disabled" }, + { MSR1(1), "BINIT# Driver enabled" }, + { BITVAL_EOT } + }}, + { 6, 2, RESERVED }, + { 4, 1, "Address parity enable", "R/W", PRESENT_DEC, { + { MSR1(0), "Address parity disabled" }, + { MSR1(1), "Address parity enabled" }, + { BITVAL_EOT } + }}, + { 3, 1, "MCERR# Driver Enable", "R/W", PRESENT_DEC, { + { MSR1(0), "MCERR# Driver disabled" }, + { MSR1(1), "MCERR# Driver enabled" }, + { BITVAL_EOT } + }}, + { 2, 1, "Response error checking enable", "R/W", PRESENT_DEC, { + { MSR1(0), "Response Error Checking disabled" }, + { MSR1(1), "Response Error Checking enabled" }, + { BITVAL_EOT } + }}, + { 1, 1, "Data error checking enable", "R/W", PRESENT_DEC, { + { MSR1(0), "Data error checking disabled" }, + { MSR1(1), "Data error checking enabled" }, + { BITVAL_EOT } + }}, + { 0, 1, RESERVED }, + { BITS_EOT } + }}, + {0xcd, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_FREQ", "", { + { BITS_EOT } + }}, + {0x11, MSRTYPE_RDWR, MSR2(0,0), "MSR_BBL_CR_CTL3", "", { + { BITS_EOT } + }}, + {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + { BITS_EOT } + }}, + {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", { + { BITS_EOT } + }}, + + // Per core msrs + + {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", { + { BITS_EOT } + }}, + {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", { + { BITS_EOT } + }}, + {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_SIZE", "", { + { BITS_EOT } + }}, + {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "", { + { BITS_EOT } + }}, + {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { + { BITS_EOT } + }}, + {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", { + { BITS_EOT } + }}, + {0x40, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", { + { BITS_EOT } + }}, + {0x41, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "", { + { BITS_EOT } + }}, + {0x42, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", { + { BITS_EOT } + }}, + {0x43, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "", { + { BITS_EOT } + }}, + {0x60, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "", { + { BITS_EOT } + }}, + {0x61, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "", { + { BITS_EOT } + }}, + {0x62, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "", { + { BITS_EOT } + }}, + {0x63, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "", { + { BITS_EOT } + }}, + {0x79, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_UPDT_TRIG", "", { + { BITS_EOT } + }}, + {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { + { BITS_EOT } + }}, + {0xa0, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_BASE", "", { + { BITS_EOT } + }}, + {0xa1, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_MASK", "", { + { BITS_EOT } + }}, + {0xc1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC0", "", { + { BITS_EOT } + }}, + {0xc2, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC1", "", { + { BITS_EOT } + }}, + {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", { + { BITS_EOT } + }}, + {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", { + { BITS_EOT } + }}, + {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + { BITS_EOT } + }}, + {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { + { BITS_EOT } + }}, + {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { + { BITS_EOT } + }}, + {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { + { BITS_EOT } + }}, + {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + { BITS_EOT } + }}, + {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + { BITS_EOT } + }}, + {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", "", { + { BITS_EOT } + }}, + {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", "", { + { BITS_EOT } + }}, + {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + { BITS_EOT } + }}, + {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", { + { BITS_EOT } + }}, + {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", { + { BITS_EOT } + }}, + {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", { + { BITS_EOT } + }}, + {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", { + { BITS_EOT } + }}, + {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { + { BITS_EOT } + }}, + {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", { + { BITS_EOT } + }}, + {0x1c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_TOS", "", { + { BITS_EOT } + }}, + {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", { + { BITS_EOT } + }}, + {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", { + { BITS_EOT } + }}, + {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", { + { BITS_EOT } + }}, + {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE0", "", { + { BITS_EOT } + }}, + {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK0", "", { + { BITS_EOT } + }}, + {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE1", "", { + { BITS_EOT } + }}, + {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK1", "", { + { BITS_EOT } + }}, + {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE2", "", { + { BITS_EOT } + }}, + {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK2", "", { + { BITS_EOT } + }}, + {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE3", "", { + { BITS_EOT } + }}, + {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK3", "", { + { BITS_EOT } + }}, + {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE4", "", { + { BITS_EOT } + }}, + {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK4", "", { + { BITS_EOT } + }}, + {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE5", "", { + { BITS_EOT } + }}, + {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK5", "", { + { BITS_EOT } + }}, + {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE6", "", { + { BITS_EOT } + }}, + {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK6", "", { + { BITS_EOT } + }}, + {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE7", "", { + { BITS_EOT } + }}, + {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK7", "", { + { BITS_EOT } + }}, + {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + { BITS_EOT } + }}, + {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + { BITS_EOT } + }}, + {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + { BITS_EOT } + }}, + {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + { BITS_EOT } + }}, + {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + { BITS_EOT } + }}, + {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + { BITS_EOT } + }}, + {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + { BITS_EOT } + }}, + {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + { BITS_EOT } + }}, + {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + { BITS_EOT } + }}, + {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + { BITS_EOT } + }}, + {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + { BITS_EOT } + }}, + {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "", { + { BITS_EOT } + }}, + {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + { BITS_EOT } + }}, + {0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "", { + { BITS_EOT } + }}, + {0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "", { + { BITS_EOT } + }}, + {0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "", { + { BITS_EOT } + }}, + {0x345, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { + { BITS_EOT } + }}, + {0x38d, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR_CTRL", "", { + { BITS_EOT } + }}, + {0x38e, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_STATUS", "", { + { BITS_EOT } + }}, + {0x38f, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_CTL", "", { + { BITS_EOT } + }}, + {0x390, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_OVF_CTL", "", { + { BITS_EOT } + }}, + {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PEBS_ENABLE", "", { + { BITS_EOT } + }}, + {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", { + { BITS_EOT } + }}, + {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", { + { BITS_EOT } + }}, + {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", { + { BITS_EOT } + }}, + {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", { + { BITS_EOT } + }}, + {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { + { BITS_EOT } + }}, + {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { + { BITS_EOT } + }}, + {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", { + { BITS_EOT } + }}, + {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", { + { BITS_EOT } + }}, + {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { + { BITS_EOT } + }}, + {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { + { BITS_EOT } + }}, + {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { + { BITS_EOT } + }}, + {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", { + { BITS_EOT } + }}, + {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + { BITS_EOT } + }}, + {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + { BITS_EOT } + }}, + {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + { BITS_EOT } + }}, + {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", { + { BITS_EOT } + }}, + {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + { BITS_EOT } + }}, + {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + { BITS_EOT } + }}, + {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + { BITS_EOT } + }}, + {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", { + { BITS_EOT } + }}, + {0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", { + { BITS_EOT } + }}, + {0x415, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_STATUS", "", { + { BITS_EOT } + }}, + {0x416, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_ADDR", "", { + { BITS_EOT } + }}, + {0x417, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_MISC", "", { + { BITS_EOT } + }}, + {0x418, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_CTL", "", { + { BITS_EOT } + }}, + {0x419, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_STATUS", "", { + { BITS_EOT } + }}, + {0x480, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_BASIC", "", { + { BITS_EOT } + }}, + {0x481, MSRTYPE_RDWR, MSR2(0,0), "IA32_PINBASED_CTLS", "", { + { BITS_EOT } + }}, + {0x482, MSRTYPE_RDWR, MSR2(0,0), "IA32_PROCBASED_CTLS", "", { + { BITS_EOT } + }}, + {0x483, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_EXIT_CTLS", "", { + { BITS_EOT } + }}, + {0x484, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_ENTRY_CTLS", "", { + { BITS_EOT } + }}, + {0x485, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_MISC", "", { + { BITS_EOT } + }}, + {0x486, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR0_FIXED0", "", { + { BITS_EOT } + }}, + {0x487, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR0_FIXED1", "", { + { BITS_EOT } + }}, + {0x488, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR4_FIXED0", "", { + { BITS_EOT } + }}, + {0x489, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR4_FIXED1", "", { + { BITS_EOT } + }}, + {0x48a, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_VMCS_ENUM", "", { + { BITS_EOT } + }}, + {0x48b, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2", "", { + { BITS_EOT } + }}, + {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "", { + { BITS_EOT } + }}, + {0x107cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL0", "", { + { BITS_EOT } + }}, + {0x107cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL1", "", { + { BITS_EOT } + }}, + {0x107ce, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL2", "", { + { BITS_EOT } + }}, + {0x107cf, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL3", "", { + { BITS_EOT } + }}, + {0x107d0, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL4", "", { + { BITS_EOT } + }}, + {0x107d1, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL5", "", { + { BITS_EOT } + }}, + {0x107d2, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL6", "", { + { BITS_EOT } + }}, + {0x107d3, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL7", "", { + { BITS_EOT } + }}, + {0x107d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_GL_CTL", "", { + { BITS_EOT } + }}, + {0xc0000080, MSRTYPE_RDWR, MSR2(0,0), "IA32_EFER", "", { + { BITS_EOT } + }}, + {0xc0000081, MSRTYPE_RDWR, MSR2(0,0), "IA32_STAR", "", { + { BITS_EOT } + }}, + {0xc0000082, MSRTYPE_RDWR, MSR2(0,0), "IA32_LSTAR", "", { + { BITS_EOT } + }}, + {0xc0000084, MSRTYPE_RDWR, MSR2(0,0), "IA32_FMASK", "", { + { BITS_EOT } + }}, + {0xc0000100, MSRTYPE_RDWR, MSR2(0,0), "IA32_FS_BASE", "", { + { BITS_EOT } + }}, + {0xc0000101, MSRTYPE_RDWR, MSR2(0,0), "IA32_GS_BASE", "", { + { BITS_EOT } + }}, + {0xc0000102, MSRTYPE_RDWR, MSR2(0,0), "IA32_KERNEL_GS_BASE", "", { + { BITS_EOT } + }}, + { MSR_EOT } +}; + + diff --git a/util/msrtool/msrtool.c b/util/msrtool/msrtool.c index 21f9c9d..e23eabf 100644 --- a/util/msrtool/msrtool.c +++ b/util/msrtool/msrtool.c @@ -51,6 +51,8 @@ static struct targetdef alltargets[] = { { "intel_core2_later", "Intel Xeon Processor 5200, 5400 series, Intel Core 2 Quad processors 8000, 9000 series", intel_core2_later_probe, intel_core2_later_msrs }, { "intel_pentium4_early", "Intel Xeon Processor, Intel Xeon Processor MP, Intel Pentium 4 processors", intel_pentium4_early_probe, intel_pentium4_early_msrs }, { "intel_pentium4_later", "Intel Xeon Processor, Intel Xeon Processor MP, Intel Pentium 4, Pentium D processors", intel_pentium4_later_probe, intel_pentium4_later_msrs }, + { "intel_nehalem", "Intel Core i5, i7 Processors, Intel Xeon Processor 3400, 3500, 5500, based on Nehalem architecture", intel_nehalem_probe, intel_nehalem_msrs }, + { "intel_sandybridge", "Intel 2nd Generation Core i3, i5, i7 Processors, Intel Xeon E3 and E5 Processor family", intel_sandybridge_probe, intel_sandybridge_msrs }, { TARGET_EOT } }; diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h index e6cea46..c92c7e1 100644 --- a/util/msrtool/msrtool.h +++ b/util/msrtool/msrtool.h @@ -242,4 +242,12 @@ extern const struct msrdef intel_pentium4_early_msrs[]; extern int intel_pentium4_later_probe(const struct targetdef *t); extern const struct msrdef intel_pentium4_later_msrs[]; +/* intel_nehalem.c */ +extern int intel_nehalem_probe(const struct targetdef *t); +extern const struct msrdef intel_nehalem_msrs[]; + +/* intel_sandybridge.c */ +extern int intel_sandybridge_probe(const struct targetdef *t); +extern const struct msrdef intel_sandybridge_msrs[]; + #endif /* MSRTOOL_H */

1 0

New patch to review for coreboot: 7d2dd95 superiotool: Add support for NCT6775F and NCT6779D
by Guenter Roeck June 30, 2012

June 30, 2012

Guenter Roeck (linux(a)roeck-us.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1148 -gerrit commit 7d2dd956c42b0d043fae3167bc17471a26c131db Author: Guenter Roeck <linux(a)roeck-us.net> Date: Fri Jun 29 12:22:51 2012 -0700 superiotool: Add support for NCT6775F and NCT6779D Change-Id: I66667fcb58f6885460021f4a2024d6ba56b95f11 Signed-off-by: Guenter Roeck <linux(a)roeck-us.net> --- util/superiotool/nuvoton.c | 234 ++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 234 insertions(+), 0 deletions(-) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index ed2eabc..46b8c2a 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -66,6 +66,170 @@ static const struct superio_registers reg_table[] = { {EOT}}}, {0x1a, "WPCM450", { {EOT}}}, + {0xb472, "NCT6775F (A)", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0xb4,0x72,0xff,0x78,0x40,0x00,0x00,0x7d,0x00, + 0x00,0x58,0x77,0xfc,0x04,0x00,MISC,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, + 0xf5,EOT}, + {0x03,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00, + 0x00,EOT}}, + {0x01, "Parallel Port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x03, "UART B, IR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x07, "GPIO6, GPIO7, GPIO8, GPIO9", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xf4,0xf5, + 0xf6,0xf7,0xf8,EOT}, + {0x18,0xff,0x00,0x00,0x00,0xef,0x00,0x00,0x00, + 0xff,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00, + 0x00,0x00,0x00,EOT}}, + {0x08, "WDT1, GPIO0, GPIO1", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0, + 0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0xff,0x00,0x00,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x09, "GPIO2, GPIO3, GPIO4, GPIO5", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4, + 0xf5,0xf6,0xf7,0xfe,EOT}, + {0x05,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xed,0xf2,0xf3,0xf4,0xf6, + 0xf7,0xfe,EOT}, + {0x00,0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00, + 0x00,0x00,0x00,0x00,0x00,0x7c,0x00,0x00,0x00, + 0x20,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb, + 0xfc,0xfd,0xfe, + EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0xc1,0x00,0x00, + 0x00,0x00,0x10,0x00,0x87,0x47,0x00,0x00,0x00, + 0x00,0x00,0x00, + EOT}}, + {0x0c, "PECI, SST", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xee,0xef,0xf1,0xf2,0xf3,0xfa,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x0f, + 0x47,0x5b,0x40,0x50,0x10,0x00,EOT}}, + {0x0d, "VID, VIDDAC, BUSSEL", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xeb, + 0xec,0xed,0xee,0xef,0xf3,0xf4,0xf5,0xf6,0xf7, + 0xf8,0xf9,EOT}, + {0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x14, + 0x01,0x00,0x88,0x00,0x00,0x00,0x00,0x07,0x00, + 0x00,0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xf0,0xf2,0xf3,0xf4,0xf8,0xfe,EOT}, + {0xff,0xff,0xf7,0xff,0xfb,0xcb,0xff,0xff,0xff, + 0xff,0x00,0x00,0x00,0x00,0x70,0xff,EOT}}, + {EOT}}}, + {0xb473, "NCT6775F (B)", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0xb4,0x73,0xff,0x78,0x40,0x00,0x00,0x7d,0x00, + 0x00,0x58,0x77,0xfc,0x04,0x00,MISC,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, + 0xf5,EOT}, + {0x03,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00, + 0x00,EOT}}, + {0x01, "Parallel Port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x03, "UART B, IR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x07, "GPIO6, GPIO7, GPIO8, GPIO9", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xf4,0xf5, + 0xf6,0xf7,0xf8,EOT}, + {0x18,0xff,0x00,0x00,0x00,0xef,0x00,0x00,0x00, + 0xff,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00, + 0x00,0x00,0x00,EOT}}, + {0x08, "WDT1, GPIO0, GPIO1", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0, + 0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0xff,0x00,0x00,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x09, "GPIO2, GPIO3, GPIO4, GPIO5", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4, + 0xf5,0xf6,0xf7,0xfe,EOT}, + {0x05,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xed,0xf2,0xf3,0xf4,0xf6, + 0xf7,0xfe,EOT}, + {0x00,0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00, + 0x00,0x00,0x00,0x00,0x00,0x7c,0x00,0x00,0x00, + 0x20,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb, + 0xfc,0xfd,0xfe, + EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0xc1,0x00,0x00, + 0x00,0x00,0x10,0x00,0x87,0x47,0x00,0x00,0x00, + 0x00,0x00,0x00, + EOT}}, + {0x0c, "PECI, SST", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xee,0xef,0xf1,0xf2,0xf3,0xfa,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x0f, + 0x47,0x5b,0x40,0x50,0x10,0x00,EOT}}, + {0x0d, "VID, VIDDAC, BUSSEL", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xeb, + 0xec,0xed,0xee,0xef,0xf3,0xf4,0xf5,0xf6,0xf7, + 0xf8,0xf9,EOT}, + {0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x14, + 0x01,0x00,0x88,0x00,0x00,0x00,0x00,0x07,0x00, + 0x00,0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xf0,0xf2,0xf3,0xf4,0xf8,0xfe,EOT}, + {0xff,0xff,0xf7,0xff,0xfb,0xcb,0xff,0xff,0xff, + 0xff,0x00,0x00,0x00,0x00,0x70,0xff,EOT}}, + {EOT}}}, {0xc332, "NCT6776F (B)", { {NOLDN, NULL, {0x10,0x11,0x13,0x14,0x16,0x17,0x18,0x19,0x1a, @@ -234,6 +398,76 @@ static const struct superio_registers reg_table[] = { {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,EOT}, {0x01,0x00,0x00,0x00,0x01,0x00,EOT}}, {EOT}}}, + {0xc562, "NCT6779D", { + {NOLDN, NULL, + {0x10,0x11,0x13,0x14,0x1a,0x1b,0x1c,0x1d,0x20, + 0x21,0x22,0x24,0x25,0x26,0x27,0x28,0x2a,0x2b, + 0x2c,0x2f,EOT}, + {0xff,0xff,0x00,0x00,0x30,0x70,0x10,0x00,0xc5, + 0x62,0xff,0x04,0x00,MISC,0x00,0x00,0xc0,0x00, + 0x01,MISC,EOT}}, + {0x01, "Parallel Port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,0xf2,EOT}, + {0x01,0x03,0xf8,0x04,0x00,0x00,EOT}}, + {0x03, "UART B, IR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}}, + {0x07, "GPIO6, GPIO7, GPIO8", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xec,0xed,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x0f,0x00,0x00,0x00,0xff,0x00,0x00,0x00, + 0x00,0x00,0xff,0x00,0x00,0x00,0x00,EOT}}, + {0x08, "WDT1, GPIO0, GPIO1", + {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0, + 0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x09, "GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4, + 0xf5,0xf6,0xf7,0xfe,EOT}, + {0x00,0xff,0x00,0x00,0x00,0x7f,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xee,0xf0,0xf2,0xf3,0xf4,0xf6,0xf7,0xfe,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00,0x00, + 0x00,0x10,0x5c,0x00,0x00,0x00,0xc0,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xe0,0xe1,0xe2, + 0xe4,0xf0,0xf1,0xf2,0xf5,0xf6,0xf7,0xf8,0xf9, + 0xfa,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x7f,0x7f,0xff, + 0xff,0x00,0x00,0x00,0x10,0x00,0x87,0x47,0x00, + 0x00,EOT}}, + {0x0d, "WDT1", + {0xf0,EOT}, + {0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xf0,0xf1,0xf2,EOT}, + {0xff,0xff,0x7f,0xff,0xff,0xff,0x0f,0xff,0xff, + 0x9d,0x00,0x00,EOT}}, + {0x14, "Port 80 UART", + {0xe0,0xe1,0xe2,0xe3,0xe4,EOT}, + {0x80,0x00,0x00,0x10,0x00,EOT}}, + {0x16, "Deep Sleep", + {0x30,0xe0,0xe1,0xe2,EOT}, + {0x20,0x20,0x04,0x05,EOT}}, + {EOT}}}, {EOT} };

3 3

New patch to review for coreboot: 7271623 IEI PM-LX2-800-R10: Added preliminary mainboard support
by Ricardo Martins June 30, 2012

June 30, 2012

Ricardo Martins (rasmartins(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1152 -gerrit commit 7271623bf1a0c27d4523c9532cd53f32257188cc Author: Ricardo Martins <rasmartins(a)gmail.com> Date: Sat Jun 30 13:44:22 2012 +0100 IEI PM-LX2-800-R10: Added preliminary mainboard support Details for this board are available at http://goo.gl/c4t6F. Most of the functionality provided by the original BIOS is implemented. Change-Id: Iaefe47f5ad405a56d230c929e5850156eb0f60ae Signed-off-by: Ricardo Martins <rasmartins(a)gmail.com> --- src/mainboard/iei/Kconfig | 3 + src/mainboard/iei/pm-lx2-800-r10/Kconfig | 56 +++++++++++++ src/mainboard/iei/pm-lx2-800-r10/chip.h | 23 +++++ src/mainboard/iei/pm-lx2-800-r10/cmos.layout | 103 ++++++++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/devicetree.cb | 87 ++++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/irq_tables.c | 68 ++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/it8888_io.def | 27 ++++++ src/mainboard/iei/pm-lx2-800-r10/mainboard.c | 103 ++++++++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/romstage.c | 94 +++++++++++++++++++++ 9 files changed, 564 insertions(+), 0 deletions(-) diff --git a/src/mainboard/iei/Kconfig b/src/mainboard/iei/Kconfig index 15d93d7..f9c264a 100644 --- a/src/mainboard/iei/Kconfig +++ b/src/mainboard/iei/Kconfig @@ -29,6 +29,8 @@ config BOARD_IEI_NOVA_4899R bool "NOVA-4899R" config BOARD_IEI_PCISA_LX_800_R10 bool "PCISA LX-800-R10" +config BOARD_IEI_PM_LX2_800_R10 + bool "PM-LX2-800-R10" endchoice @@ -36,6 +38,7 @@ source "src/mainboard/iei/juki-511p/Kconfig" source "src/mainboard/iei/kino-780am2-fam10/Kconfig" source "src/mainboard/iei/nova4899r/Kconfig" source "src/mainboard/iei/pcisa-lx-800-r10/Kconfig" +source "src/mainboard/iei/pm-lx2-800-r10/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/iei/pm-lx2-800-r10/Kconfig b/src/mainboard/iei/pm-lx2-800-r10/Kconfig new file mode 100644 index 0000000..ee88ce4 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/Kconfig @@ -0,0 +1,56 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +if BOARD_IEI_PM_LX2_800_R10 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_AMD_GEODE_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select HAVE_OPTION_TABLE + select PIRQ_ROUTE + select BOARD_ROMSIZE_KB_512 + select POWER_BUTTON_FORCE_ENABLE + +config MAINBOARD_DIR + string + default iei/pm-lx2-800-r10 + +config MAINBOARD_PART_NUMBER + string + default "PM-LX2-800-R10" + +config IRQ_SLOT_COUNT + int + default 3 + +config SCH3114_COM3_AUTO_DIR + bool "COM3 Automatic Direction Control" + default y + help + If selected, COM3 automatic direction control will + be enabled by default. + +endif # BOARD_IEI_PM_LX2_800_R10 diff --git a/src/mainboard/iei/pm-lx2-800-r10/chip.h b/src/mainboard/iei/pm-lx2-800-r10/chip.h new file mode 100644 index 0000000..b37994d --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/iei/pm-lx2-800-r10/cmos.layout b/src/mainboard/iei/pm-lx2-800-r10/cmos.layout new file mode 100644 index 0000000..4cf1174 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/cmos.layout @@ -0,0 +1,103 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +entries + # RTC + 0 384 r 0 reserved_rtc + # Coreboot + 384 1 e 3 boot_option + 385 1 e 3 last_boot + 386 4 r 0 reboot_bits + 390 3 e 4 baud_rate + 393 4 e 5 debug_level + 397 2 r 0 unused + # PM-LX2-800-R10 + 399 1 e 1 com3_auto_direction + 400 1 e 2 it8888_io_space0 + 401 1 e 2 it8888_io_space1 + 402 1 e 2 it8888_io_space2 + 403 1 e 2 it8888_io_space3 + 404 2 e 6 it8888_io_space0_speed + 406 2 e 6 it8888_io_space1_speed + 408 2 e 6 it8888_io_space2_speed + 410 2 e 6 it8888_io_space3_speed + 412 3 e 7 it8888_io_space0_size + 415 3 e 7 it8888_io_space1_size + 418 3 e 7 it8888_io_space2_size + 421 3 e 7 it8888_io_space3_size + 424 16 h 0 it8888_io_space0_addr + 440 16 h 0 it8888_io_space1_addr + 456 16 h 0 it8888_io_space2_addr + 472 16 h 0 it8888_io_space3_addr + 488 16 h 0 check_sum + +enumerations + # Yes / No + 1 0 No + 1 1 Yes + + # Enabled / Disabled + 2 0 Disabled + 2 1 Enabled + + # Normal / Fallback + 3 0 Fallback + 3 1 Normal + + # Console Baud Rate + 4 0 115200 + 4 1 57600 + 4 2 38400 + 4 3 19200 + 4 4 9600 + 4 5 4800 + 4 6 2400 + 4 7 1200 + + # Console Log Level + 5 0 Emergency + 5 1 Alert + 5 2 Critical + 5 3 Error + 5 4 Warning + 5 5 Notice + 5 6 Info + 5 7 Debug + 5 8 Spew + + # IT8888 Decoding Speeds + 6 0 Subtractive + 6 1 Slow + 6 2 Medium + 6 3 Fast + + # IT8888 Decoding Sizes + 7 0 1 + 7 1 2 + 7 2 4 + 7 3 8 + 7 4 16 + 7 5 32 + 7 6 64 + 7 7 128 + +checksums + checksum 384 487 488 diff --git a/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb b/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb new file mode 100644 index 0000000..adcdcad --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb @@ -0,0 +1,87 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Video Adapter + device pci 1.2 on end # AES Security Block + chip southbridge/amd/cs5536 + register "lpc_serirq_enable" = "0x00001C7A" + register "lpc_serirq_polarity" = "0x0000E385" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" + register "enable_USBP4_device" = "0" # 0:host, 1:device + register "enable_USBP4_overcurrent" = "0" + register "com1_enable" = "0" + register "com2_enable" = "0" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci 11.0 on end # IT8888 + device pci e.0 on end # RTL8100C + device pci f.0 on # ISA Bridge + chip superio/smsc/smscsuperio # SMSC SCH3114 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + + device pnp 2e.3 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 2e.7 on # PS/2 keyboard/mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + + device pnp 2e.a on # Runtime Register + io 0x60 = 0x400 + end + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device lapic_cluster 0 on + chip cpu/amd/geode_lx + device lapic 0 on end + end + end +end diff --git a/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c b/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c new file mode 100644 index 0000000..42afa3c --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +/* Platform IRQs */ +#define PIRQA 7 + +/* Map */ +#define M_PIRQA (1 << PIRQA) + +/* Link */ +#define L_PIRQA 1 +#define L_PIRQB 2 +#define L_PIRQC 3 +#define L_PIRQD 4 + +#define NC {0x00, 0x0000} + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 3, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x0f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x2090, /* Device */ + 0, /* Miniport */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0x4b, /* Checksum */ + { + /* Host bridge. */ + {0x00, (0x01 << 3) | 0x0, + {{L_PIRQA, M_PIRQA}, NC, NC, NC}, + 0x0, 0x0}, + /* ISA bridge. */ + {0x00, (0x0f << 3) | 0x0, + {NC, {L_PIRQB, M_PIRQA}, NC, {L_PIRQD, M_PIRQA}}, + 0x0, 0x0}, + /* Ethernet. */ + {0x00, (0x0e << 3) | 0x0, + {{L_PIRQD, M_PIRQA}, NC, NC, NC}, + 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def b/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def new file mode 100644 index 0000000..5920abc --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Name, Register, Enabled/Disabled, Speed, Size, Address. */ +IT8888_IO("it8888_io_space0", 0x58, 0, 0, 0, 0) +IT8888_IO("it8888_io_space1", 0x5c, 0, 0, 0, 0) +IT8888_IO("it8888_io_space2", 0x60, 0, 0, 0, 0) +IT8888_IO("it8888_io_space3", 0x64, 0, 0, 0, 0) +IT8888_IO("it8888_io_space4", 0x68, 0, 0, 0, 0) +IT8888_IO("it8888_io_space5", 0x6c, 0, 0, 0, 0) diff --git a/src/mainboard/iei/pm-lx2-800-r10/mainboard.c b/src/mainboard/iei/pm-lx2-800-r10/mainboard.c new file mode 100644 index 0000000..8c5b3ba --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/mainboard.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/device.h> +#include <boot/tables.h> +#include <pc80/mc146818rtc.h> +#include "chip.h" + +#if CONFIG_USE_OPTION_TABLE +# include "option_table.h" +#endif + +/* SCH3114 runtime register (RTR) address. */ +#define SCH3114_RTR_ADDR (0x400) +/* SP34 option register. */ +#define SCH3114_RTR_SP34_OPT (SCH3114_RTR_ADDR + 0x13) +/* H/W Monitoring register block index. */ +#define SCH3114_RTR_HWM_IDX (SCH3114_RTR_ADDR + 0x70) +/* H/W Monitoring register block data. */ +#define SCH3114_RTR_HWM_DAT (SCH3114_RTR_ADDR + 0x71) +/* H/W Monitoring Ready/Lock/Start register. */ +#define SCH3114_HWM_RLS_REG (0x40) +/* IT8888 PCI Vendor ID. */ +#define IT8888_PCI_VID (0x1283) +/* IT8888 PCI Device ID. */ +#define IT8888_PCI_DID (0x8888) + +static u16 opt(const char* option, u16 def_value) +{ +#if CONFIG_USE_OPTION_TABLE + u16 value = 0; + if (get_option(&value, option) != 0) + value = def_value; + return value; +#else + return def_value; +#endif +} + +static void init(struct device *dev) +{ + /* SCH3114: enable hardware monitor. */ + printk(BIOS_INFO, "Enabling SCH3114 hardware monitor\n"); + outb(SCH3114_HWM_RLS_REG, SCH3114_RTR_HWM_IDX); + outb(inb(SCH3114_RTR_HWM_DAT) | 0x01, SCH3114_RTR_HWM_DAT); + + /* SCH3114: COM3 Automatic Direction Control / nRTS control. */ + if (opt("com3_auto_direction", CONFIG_SCH3114_COM3_AUTO_DIR) != 0) { + printk(BIOS_INFO, "Enabling RS858 Auto Direction Control\n"); + outb(inb(SCH3114_RTR_SP34_OPT) | 0x03, SCH3114_RTR_SP34_OPT); + } + + /* IT8888. */ + device_t it8x = dev_find_device(IT8888_PCI_VID, IT8888_PCI_DID, 0); + if (!it8x) { + printk(BIOS_ERR, "IT8888 not found\n"); + return; + } + + u32 cfg = 0; +#define IT8888_IO(name, reg, dena, dspeed, dsize, daddr) \ + if (opt(name, dena) != 0) { \ + cfg = (1 << 31); \ + cfg |= opt(name "_addr", daddr); \ + cfg |= opt(name "_speed", dspeed) << 29; \ + cfg |= opt(name "_size", dsize) << 24; \ + } else { \ + cfg = 0; \ + } \ + pci_write_config32(it8x, reg, cfg); + +#include "it8888_io.def" +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("IEI PM-LX2-800-R10 Mainboard") + .enable_dev = enable_dev, +}; diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c new file mode 100644 index 0000000..9159933 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> + +#include <spd.h> +#include <arch/io.h> +#include <arch/hlt.h> +#include <arch/llshell.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/lxdef.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <southbridge/amd/cs5536/early_smbus.c> +#include <southbridge/amd/cs5536/early_setup.c> +#include <superio/smsc/smscsuperio/early_serial.c> + +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + /* Only DIMM0 is available. */ + if (device != DIMM0) + return 0xFF; + + return smbus_read_byte(device, address); +} + +#define ManualConf 1 +#define PLLMSRhi 0x0000059C +#define PLLMSRlo 0x00DE6001 + +#include <northbridge/amd/lx/raminit.h> +#include <northbridge/amd/lx/pll_reset.c> +#include <northbridge/amd/lx/raminit.c> +#include <lib/generic_sdram.c> +#include <cpu/amd/geode_lx/cpureginit.c> +#include <cpu/amd/geode_lx/syspreinit.c> +#include <cpu/amd/geode_lx/msrinit.c> + +void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + {.channel0 = {DIMM0, DIMM1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* Enable COM3. */ + device_t dev = PNP_DEV(0x2e, 0x0b); + u16 port = dev >> 8; + outb(0x55, port); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + outb(0xaa, port); + + report_bist_failure(bist); + + pll_reset(ManualConf); + + cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); + + sdram_initialize(1, memctrl); +}

1 0

Trouble in compiling tint payload
by manasa gv June 30, 2012

June 30, 2012

Hi, 1)I used the following commands to use tint payload. $ cd coreboot/payloads $ wget ftp://mirrors.kernel.org/ubuntu/pool/universe/t/tint/tint_0.03b.tar.gz $ tar xfvz tint_0.03b.tar.gz $ cd tint-0.03b $ svn export svn://coreboot.org/coreboot/trunk/payloads/external/tint/libpayload_tint.pa… $ patch -p1 < libpayload_tint.patch $ make 2)After doing make getting the following errors : Found Libpayload ./libpayloadbin. LPCC tint.o cc1: fatal error: tint.c: Permission denied compilation terminated. make: *** [tint.o] Error 1 3) So i changed the permission of the tint.c file by using this command. chmod ug+rw tint.c 4)Again i did make , then also am having these errors: Found Libpayload ./libpayloadbin. LPCC tint.o In file included from config.h:33:0, from tint.c:42: ./libpayloadbin/libpayload/bin/../include/curses.h:85:23: error: two or more data types in declaration specifiers ./libpayloadbin/libpayload/bin/../include/curses.h:85:1: warning: useless type name in empty declaration [enabled by default] ./libpayloadbin/libpayload/bin/../include/curses.h:597:0: warning: "COLOR_BLUE" redefined [enabled by default] In file included from tint.c:41:0: io.h:40:0: note: this is the location of the previous definition In file included from config.h:33:0, from tint.c:42: ./libpayloadbin/libpayload/bin/../include/curses.h:599:0: warning: "COLOR_RED" redefined [enabled by default] In file included from tint.c:41:0: io.h:37:0: note: this is the location of the previous definition In file included from config.h:33:0, from tint.c:42: ./libpayloadbin/libpayload/bin/../include/curses.h:602:0: warning: "COLOR_CYAN" redefined [enabled by default] In file included from tint.c:41:0: io.h:42:0: note: this is the location of the previous definition In file included from config.h:33:0, from tint.c:42: ./libpayloadbin/libpayload/bin/../include/curses.h:603:0: warning: "COLOR_MAGENTA" redefined [enabled by default] In file included from tint.c:41:0: io.h:41:0: note: this is the location of the previous definition In file included from config.h:33:0, from tint.c:42: ./libpayloadbin/libpayload/bin/../include/curses.h:604:0: warning: "COLOR_YELLOW" redefined [enabled by default] In file included from tint.c:41:0: io.h:39:0: note: this is the location of the previous definition make: *** [tint.o] Error 1 I am using Fedora17 OS. Please suggest me to comeout of these errors.. Thanks, Manasa

1 0

Re: [coreboot] RFC: automatic mptable creation
by Patrick Georgi June 29, 2012

June 29, 2012

Am 25.06.2012 17:50, schrieb ron minnich: > Hence, people's thinking move to MP auto generation from ACPI. And nothing like that ever happened (I think that's good). > I'm wondering if we want more effort going into MP tables when > they're basically obsolete? MP tables are a relatively easy problem. The next step could be reusing the data for PIR (and extending the devicetree model where necessary). Once our devicetree is suitable for these two, it should also be good enough for ACPI. That's one thing less to worry about when extending acpigen. > Or does the hardware somehow require it? Hardware doesn't require it, but some software is happier when having meaningful legacy tables. Patrick

3 2

Patch set updated for coreboot: 42d25f8 libpayload: add controller type in usbdev_hc
by Anton Kochkov June 29, 2012

June 29, 2012

Anton Kochkov (anton.kochkov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1145 -gerrit commit 42d25f8403209c331b288ea3df2bce5826ccf0fc Author: Anton Kochkov <anton.kochkov(a)gmail.com> Date: Thu Jun 28 08:30:15 2012 +0400 libpayload: add controller type in usbdev_hc Add controller type (UHCI, OHCI, EHCI or XHCI) into usbdev_hc (hci_t) struct, so now we know which type selected controller have. It needed to access controller specific data, if access usb tree outside of libpayload (e.g. in payload intself) Change-Id: I7df947bbb56a50d0d792ccd4d3a6b021ee95e2ea Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> --- payloads/libpayload/drivers/usb/ehci.c | 2 ++ payloads/libpayload/drivers/usb/ohci.c | 2 ++ payloads/libpayload/drivers/usb/uhci.c | 2 ++ payloads/libpayload/drivers/usb/xhci.c | 2 ++ payloads/libpayload/include/usb/usb.h | 3 +++ 5 files changed, 11 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 8d84f8d..4d0a209 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -635,6 +635,8 @@ ehci_init (pcidev_t addr) pci_command = (pci_command | PCI_COMMAND_MEMORY) & ~PCI_COMMAND_IO ; pci_write_config32(addr, PCI_COMMAND, pci_command); + controller->type = EHCI; + controller->start = ehci_start; controller->stop = ehci_stop; controller->reset = ehci_reset; diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 8a01cf2..f522d8d 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -95,6 +95,8 @@ ohci_init (pcidev_t addr) if(!controller->instance) fatal("Not enough memory creating USB controller instance.\n"); + controller->type = OHCI; + controller->start = ohci_start; controller->stop = ohci_stop; controller->reset = ohci_reset; diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c index 78f7aba..84b461a 100644 --- a/payloads/libpayload/drivers/usb/uhci.c +++ b/payloads/libpayload/drivers/usb/uhci.c @@ -147,6 +147,8 @@ uhci_init (pcidev_t addr) if(!controller->instance) fatal("Not enough memory creating USB controller instance.\n"); + controller->type = UHCI; + controller->start = uhci_start; controller->stop = uhci_stop; controller->reset = uhci_reset; diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index a25cf40..828e0ea 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -63,6 +63,8 @@ xhci_init (pcidev_t addr) if(!controller->instance) fatal("Not enough memory creating USB controller instance.\n"); + controller->type = XHCI; + controller->start = xhci_start; controller->stop = xhci_stop; controller->reset = xhci_reset; diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index ecfee54..27af9bc 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -111,10 +111,13 @@ struct usbdev { void (*poll) (usbdev_t *dev); }; +typedef enum { OHCI = 0, UHCI = 1, EHCI = 2, XHCI = 3} hc_type; + struct usbdev_hc { struct usbdev_hc *next; pcidev_t bus_address; u32 reg_base; + hc_type type; usbdev_t *devices[128]; // dev 0 is root hub, 127 is last addressable void (*start) (hci_t *controller); void (*stop) (hci_t *controller);

1 0

Patch set updated for coreboot: 833a825 superiotool: Add support for NCT6775F(A/B) and NCT6779D
by Guenter Roeck June 29, 2012

June 29, 2012

Guenter Roeck (linux(a)roeck-us.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1148 -gerrit commit 833a825f753779d366e401ebd8af6761bb5125f2 Author: Guenter Roeck <linux(a)roeck-us.net> Date: Fri Jun 29 12:22:51 2012 -0700 superiotool: Add support for NCT6775F(A/B) and NCT6779D Change-Id: I66667fcb58f6885460021f4a2024d6ba56b95f11 Signed-off-by: Guenter Roeck <linux(a)roeck-us.net> --- util/superiotool/nuvoton.c | 234 ++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 234 insertions(+), 0 deletions(-) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index ed2eabc..46b8c2a 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -66,6 +66,170 @@ static const struct superio_registers reg_table[] = { {EOT}}}, {0x1a, "WPCM450", { {EOT}}}, + {0xb472, "NCT6775F (A)", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0xb4,0x72,0xff,0x78,0x40,0x00,0x00,0x7d,0x00, + 0x00,0x58,0x77,0xfc,0x04,0x00,MISC,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, + 0xf5,EOT}, + {0x03,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00, + 0x00,EOT}}, + {0x01, "Parallel Port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x03, "UART B, IR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x07, "GPIO6, GPIO7, GPIO8, GPIO9", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xf4,0xf5, + 0xf6,0xf7,0xf8,EOT}, + {0x18,0xff,0x00,0x00,0x00,0xef,0x00,0x00,0x00, + 0xff,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00, + 0x00,0x00,0x00,EOT}}, + {0x08, "WDT1, GPIO0, GPIO1", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0, + 0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0xff,0x00,0x00,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x09, "GPIO2, GPIO3, GPIO4, GPIO5", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4, + 0xf5,0xf6,0xf7,0xfe,EOT}, + {0x05,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xed,0xf2,0xf3,0xf4,0xf6, + 0xf7,0xfe,EOT}, + {0x00,0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00, + 0x00,0x00,0x00,0x00,0x00,0x7c,0x00,0x00,0x00, + 0x20,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb, + 0xfc,0xfd,0xfe, + EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0xc1,0x00,0x00, + 0x00,0x00,0x10,0x00,0x87,0x47,0x00,0x00,0x00, + 0x00,0x00,0x00, + EOT}}, + {0x0c, "PECI, SST", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xee,0xef,0xf1,0xf2,0xf3,0xfa,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x0f, + 0x47,0x5b,0x40,0x50,0x10,0x00,EOT}}, + {0x0d, "VID, VIDDAC, BUSSEL", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xeb, + 0xec,0xed,0xee,0xef,0xf3,0xf4,0xf5,0xf6,0xf7, + 0xf8,0xf9,EOT}, + {0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x14, + 0x01,0x00,0x88,0x00,0x00,0x00,0x00,0x07,0x00, + 0x00,0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xf0,0xf2,0xf3,0xf4,0xf8,0xfe,EOT}, + {0xff,0xff,0xf7,0xff,0xfb,0xcb,0xff,0xff,0xff, + 0xff,0x00,0x00,0x00,0x00,0x70,0xff,EOT}}, + {EOT}}}, + {0xb473, "NCT6775F (B)", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0xb4,0x73,0xff,0x78,0x40,0x00,0x00,0x7d,0x00, + 0x00,0x58,0x77,0xfc,0x04,0x00,MISC,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, + 0xf5,EOT}, + {0x03,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00, + 0x00,EOT}}, + {0x01, "Parallel Port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x03, "UART B, IR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x07, "GPIO6, GPIO7, GPIO8, GPIO9", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xf4,0xf5, + 0xf6,0xf7,0xf8,EOT}, + {0x18,0xff,0x00,0x00,0x00,0xef,0x00,0x00,0x00, + 0xff,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00, + 0x00,0x00,0x00,EOT}}, + {0x08, "WDT1, GPIO0, GPIO1", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0, + 0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0xff,0x00,0x00,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x09, "GPIO2, GPIO3, GPIO4, GPIO5", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4, + 0xf5,0xf6,0xf7,0xfe,EOT}, + {0x05,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xed,0xf2,0xf3,0xf4,0xf6, + 0xf7,0xfe,EOT}, + {0x00,0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00, + 0x00,0x00,0x00,0x00,0x00,0x7c,0x00,0x00,0x00, + 0x20,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb, + 0xfc,0xfd,0xfe, + EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0xc1,0x00,0x00, + 0x00,0x00,0x10,0x00,0x87,0x47,0x00,0x00,0x00, + 0x00,0x00,0x00, + EOT}}, + {0x0c, "PECI, SST", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xee,0xef,0xf1,0xf2,0xf3,0xfa,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x0f, + 0x47,0x5b,0x40,0x50,0x10,0x00,EOT}}, + {0x0d, "VID, VIDDAC, BUSSEL", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xeb, + 0xec,0xed,0xee,0xef,0xf3,0xf4,0xf5,0xf6,0xf7, + 0xf8,0xf9,EOT}, + {0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x14, + 0x01,0x00,0x88,0x00,0x00,0x00,0x00,0x07,0x00, + 0x00,0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xf0,0xf2,0xf3,0xf4,0xf8,0xfe,EOT}, + {0xff,0xff,0xf7,0xff,0xfb,0xcb,0xff,0xff,0xff, + 0xff,0x00,0x00,0x00,0x00,0x70,0xff,EOT}}, + {EOT}}}, {0xc332, "NCT6776F (B)", { {NOLDN, NULL, {0x10,0x11,0x13,0x14,0x16,0x17,0x18,0x19,0x1a, @@ -234,6 +398,76 @@ static const struct superio_registers reg_table[] = { {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,EOT}, {0x01,0x00,0x00,0x00,0x01,0x00,EOT}}, {EOT}}}, + {0xc562, "NCT6779D", { + {NOLDN, NULL, + {0x10,0x11,0x13,0x14,0x1a,0x1b,0x1c,0x1d,0x20, + 0x21,0x22,0x24,0x25,0x26,0x27,0x28,0x2a,0x2b, + 0x2c,0x2f,EOT}, + {0xff,0xff,0x00,0x00,0x30,0x70,0x10,0x00,0xc5, + 0x62,0xff,0x04,0x00,MISC,0x00,0x00,0xc0,0x00, + 0x01,MISC,EOT}}, + {0x01, "Parallel Port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,0xf2,EOT}, + {0x01,0x03,0xf8,0x04,0x00,0x00,EOT}}, + {0x03, "UART B, IR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}}, + {0x07, "GPIO6, GPIO7, GPIO8", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xec,0xed,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x0f,0x00,0x00,0x00,0xff,0x00,0x00,0x00, + 0x00,0x00,0xff,0x00,0x00,0x00,0x00,EOT}}, + {0x08, "WDT1, GPIO0, GPIO1", + {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0, + 0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x09, "GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4, + 0xf5,0xf6,0xf7,0xfe,EOT}, + {0x00,0xff,0x00,0x00,0x00,0x7f,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xee,0xf0,0xf2,0xf3,0xf4,0xf6,0xf7,0xfe,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00,0x00, + 0x00,0x10,0x5c,0x00,0x00,0x00,0xc0,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xe0,0xe1,0xe2, + 0xe4,0xf0,0xf1,0xf2,0xf5,0xf6,0xf7,0xf8,0xf9, + 0xfa,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x7f,0x7f,0xff, + 0xff,0x00,0x00,0x00,0x10,0x00,0x87,0x47,0x00, + 0x00,EOT}}, + {0x0d, "WDT1", + {0xf0,EOT}, + {0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xf0,0xf1,0xf2,EOT}, + {0xff,0xff,0x7f,0xff,0xff,0xff,0x0f,0xff,0xff, + 0x9d,0x00,0x00,EOT}}, + {0x14, "Port 80 UART", + {0xe0,0xe1,0xe2,0xe3,0xe4,EOT}, + {0x80,0x00,0x00,0x10,0x00,EOT}}, + {0x16, "Deep Sleep", + {0x30,0xe0,0xe1,0xe2,EOT}, + {0x20,0x20,0x04,0x05,EOT}}, + {EOT}}}, {EOT} };

2 1

Patch set updated for coreboot: 8845dc7 superiotool: Add support for function to dump superio chip data registers
by Guenter Roeck June 29, 2012

June 29, 2012

Guenter Roeck (linux(a)roeck-us.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1149 -gerrit commit 8845dc7338f1dea50262f7b936abb099f3204a96 Author: Guenter Roeck <linux(a)roeck-us.net> Date: Fri Jun 29 12:23:50 2012 -0700 superiotool: Add support for function to dump superio chip data registers Add new function dump_data() to dump a bank of superio data registers. Change-Id: I13a58d87c14d319cfcdea1ec1d54c2b110d90f9f Signed-off-by: Guenter Roeck <linux(a)roeck-us.net> --- util/superiotool/superiotool.c | 29 +++++++++++++++++++++++++++++ util/superiotool/superiotool.h | 1 + 2 files changed, 30 insertions(+), 0 deletions(-) diff --git a/util/superiotool/superiotool.c b/util/superiotool/superiotool.c index 293aaa6..538aa09 100644 --- a/util/superiotool/superiotool.c +++ b/util/superiotool/superiotool.c @@ -34,6 +34,18 @@ int dump = 0, verbose = 0, extra_dump = 0; /* Global flag which indicates whether a chip was detected at all. */ int chip_found = 0; +static void set_bank(uint16_t port, uint8_t bank) +{ + OUTB(0x4E, port); + OUTB(bank, port + 1); +} + +static uint8_t datareg(uint16_t port, uint8_t reg) +{ + OUTB(reg, port); + return INB(port + 1); +} + uint8_t regval(uint16_t port, uint8_t reg) { OUTB(reg, port); @@ -186,6 +198,23 @@ void dump_io(uint16_t iobase, uint16_t length) printf("\n"); } +void dump_data(uint16_t iobase, int bank) +{ + uint16_t i; + + printf("Bank %d:\n", bank); + printf(" "); + for (i = 0; i < 16; i++) + printf("%02x ", i); + set_bank(iobase, bank); + for (i = 0; i < 256; i++) { + if (i % 16 == 0) + printf("\n%02x: ", i / 16); + printf("%02x ", datareg(iobase, i)); + } + printf("\n"); +} + void probing_for(const char *vendor, const char *info, uint16_t port) { if (!verbose) diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index 94918b8..7a0b7f6 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -174,6 +174,7 @@ const char *get_superio_name(const struct superio_registers reg_table[], void dump_superio(const char *name, const struct superio_registers reg_table[], uint16_t port, uint16_t id, uint8_t ldn_sel); void dump_io(uint16_t iobase, uint16_t length); +void dump_data(uint16_t iobase, int bank); void probing_for(const char *vendor, const char *info, uint16_t port); void print_vendor_chips(const char *vendor, const struct superio_registers reg_table[]);

1 0

Patch set updated for coreboot: 7d4e038 superiotool: Dump data registers for Nuvoton chips
by Guenter Roeck June 29, 2012

June 29, 2012

Guenter Roeck (linux(a)roeck-us.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1150 -gerrit commit 7d4e038535da3c45587fa31af520e8fb88489597 Author: Guenter Roeck <linux(a)roeck-us.net> Date: Fri Jun 29 12:24:57 2012 -0700 superiotool: Dump data registers for Nuvoton chips Add support to dump all data registers for Nuvoton chips (NCT6775F, NCT6776F, and NCT6779D). Register contents will be dumped if the -e option is provided on the command line. Change-Id: I2b425b48c1f28a10ff3c1ca1d7f21c501eff74ad Signed-off-by: Guenter Roeck <linux(a)roeck-us.net> --- util/superiotool/nuvoton.c | 27 ++++++++++++++++++++++++++- 1 files changed, 26 insertions(+), 1 deletions(-) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 46b8c2a..2adb90a 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -476,12 +476,16 @@ void probe_idregs_nuvoton(uint16_t port) uint8_t sid, srid; uint16_t chip_id = 0; uint8_t chip_rev = 0; + uint16_t iobase = 0; + int i; /* Probe for the 16bit IDs first to avoid collisions */ probing_for("Nuvoton", "", port); enter_conf_mode_winbond_fintek_ite_8787(port); chip_id = (regval(port, DEVICE_ID_REG) << 8) | regval(port, DEVICE_ID_REG + 1); + regwrite(port, LDN_SEL, 0x0b); + iobase = (regval(port, 0x60) << 8) | (regval(port, 0x61) & ~7); exit_conf_mode_winbond_fintek_ite_8787(port); @@ -492,7 +496,7 @@ void probe_idregs_nuvoton(uint16_t port) enter_conf_mode_winbond_fintek_ite_8787(port); dump_superio("Nuvoton", reg_table, port, chip_id, LDN_SEL); exit_conf_mode_winbond_fintek_ite_8787(port); - return; + goto extra; } if (verbose) @@ -524,6 +528,27 @@ void probe_idregs_nuvoton(uint16_t port) get_superio_name(reg_table, sid), chip_id, chip_rev, port); chip_found = 1; dump_superio("Nuvoton", reg_table, port, sid, LDN_SEL); + +extra: + if (extra_dump && iobase) { + switch (chip_id & 0xfff0) { + case 0xb470: /* NCT6775F */ + for (i = 0; i < 7; i++) + dump_data(iobase + 5, i); + dump_data(iobase + 5, 0xa); + dump_data(iobase + 5, 0xc); + dump_data(iobase + 5, 0xd); + break; + case 0xc330: /* NCT6776F */ + for (i = 0; i < 8; i++) + dump_data(iobase + 5, i); + break; + case 0xc560: /* NCT6779D */ + for (i = 0; i < 10; i++) + dump_data(iobase + 5, i); + break; + } + } } void print_nuvoton_chips(void)

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