April 2010 - coreboot - mail.coreboot.org

#95: Run coreboot in VirtualBox
by coreboot Dec. 10, 2014

Dec. 10, 2014

#95: Run coreboot in VirtualBox ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: misc | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ It would be nice if we could test coreboot images in VirtualBox, see http://virtualbox.org/. VirtualBox does not (yet) provide a simple mechanism to use a different BIOS in their emulated machines (something like "-L" in qemu). Instead the BIOS image (a custom bochs BIOS + LGPL'g VGABIOS) is converted to C code (an array of bytes, or the like) and merged into the VirtualBox executable. The relevant files are {{{ src/VBox/Devices/PC/DevPcBios.cpp bldprogs/bin2c.c }}} if someone want to hack VirtualBox to easily support using coreboot images instead of their usual BIOS. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/95> coreboot <http://www.coreboot.org/>

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EHCI debug port finder
by Carl-Daniel Hailfinger May 30, 2014

May 30, 2014

I wanted to know which physical port of my multiple USB controllers have the debug capability. There was no way to find that easily, so I created a tool which will do most of the work for the user. Example output: The following PCI devices support a USB debug port (says lspci): 0000:00:1d.7 The following PCI devices support a USB debug port (says the kernel): 0000:00:1d.7 PCI device 0000:00:1d.7, USB bus 3, USB physical port 1 Currently connected high-speed devices: /: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=ehci_hcd/6p, 480M |__ Port 2: Dev 20, If 0, Class=stor., Driver=usb-storage, 480M The output can be improved, but it's a good start. Regards, Carl-Daniel -- http://www.hailfinger.org/

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#131: New flashrom motherboard support
by coreboot Sept. 18, 2012

Sept. 18, 2012

#131: New flashrom motherboard support ---------------------------------+------------------------------------------ Reporter: anonymous | Owner: somebody Type: enhancement | Status: new Priority: trivial | Milestone: Going mainstream Component: flashrom | Version: v2 Keywords: flashrom asus | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Did not know where I should put this but the bugtracker seemed like the right place. I tried flashrom and it could not detect my chip on my ASUS P5ND2-SLI Deluxe motherboard. The board has a SST49LF004B flash chip and after enforcing the right chip flashrom seems to work fine. {{{ # ./flashrom -V -f -r -c SST49LF004A/B test Calibrating delay loop... 796M loops per second, 100 myus = 201 us. OK. No coreboot table found. WARNING: No chipset found. Flash detection will most likely fail. Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0x21, id2 0x5e, id1 parity violation No EEPROM/flash device found. Force read (-f -r -c) requested, forcing chip probe success: Probing for SST SST49LF004A/B, 512 KB: Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Force reading flash... done. }}} This should probably apply to the P5ND-SLI board, too. What do you need from me for adding autodetection of this board/chip? -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/131> coreboot <http://www.coreboot.org/>

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#135: Flashrom deletes MAC addresses on Tyan Tomcat n3400B (S2925-E)
by coreboot March 24, 2012

March 24, 2012

#135: Flashrom deletes MAC addresses on Tyan Tomcat n3400B (S2925-E) ---------------------------------+------------------------------------------ Reporter: Jan@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ I've tried updating the BIOS of a Tomcat n3400B (S2925-E). The update itself worked fine, but the MAC addresses of the onboard NVidia-Gigabit Ethernet chips were set to bogus values (66:55:44:33:22:11 or something like that) afterwards. Restoring the old flash backup worked. This does not happen with the official update tool from Tyan. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/135> coreboot <http://www.coreboot.org/>

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mptable and irq_tables.c for MSI P35 Neo (MS-7360)
by Fred . Nov. 30, 2011

Nov. 30, 2011

I've attached the mptable file, and irq_tables.c file.

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MSI P35 Neo (MS-7360) motherboard
by Fred . Nov. 30, 2011

Nov. 30, 2011

Files attached. MSI P35 Neo (MS-7360) Intel P35 chipset. Fintek F71882FG/F71883FG super i/o. ICH9 southbridge. $ dmidecode $ dmidecode --dump $ hardinfo $ lshw $ lspci -n $ lspci -tvnn $ lspci -v $ superiotool -dV Hope it helps.

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Re: [coreboot] [RFC] ACPI for ASUS P2B/P2B-LS (Intel 440BX/82371EB)
by Keith Hui Nov. 25, 2010

Nov. 25, 2010

Hi all, Based on Idwer's RFC I tried adding ACPI to P2B-LS plus completing the rest of the PIIX4 function 3 initialization. This is a summary of what I did: * I used the DSDT table from the final vendor BIOS. Not provided here for obvious reasons, but I can tell you how to extract it. * I also replicated the content of the PIIX4 function 3 config space after booting with vendor BIOS, as below: 00:04.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 02) 00: 86 80 13 71 03 00 80 02 02 00 80 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 e4 00 00 00 00 00 20 1e 30 00 01 00 00 00 00 50: 00 58 19 00 c0 c8 3b 02 37 40 40 03 00 00 00 00 60: 90 02 e7 00 00 00 00 10 04 e4 11 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 01 e8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 30 0f 00 00 00 00 00 00 One exception is 0x90-0x91 which has the SMBus host base address. I kept it as 0x0f00. * Idwer is trying to build ACPI 4.0 (!) tables. Since P2B-LS is shipped when ACPI was still at 1.0, that's what I did. For booting XP, even ACPI 2.0 compliance is sufficient. This is a summary of what happens: * I can no longer get POST codes on the PCI bus. POST codes still appear on the ISA bus. Glad I picked a POST card that works on both buses. * Power off does not work. The last POST code to show before complete kernel shutdown and hard drive spinning down is 0xF5. * I don't how how to enter soft suspend in Linux (silly me -_-! ), so I have not tested it. * the sensor appears on ISA bus port 0x290, just like vendor BIOS. * My SB AWE64 ISA card still got initialized and driver loaded, but no sound. In fact ALSA can't even do I/O to the card. That apparently is because PIIX4 needs to be configured to forward certain I/O port ranges to ISA, and some of those port ranges can be further configured. This would require detecting in runtime what ISA cards are installed, what are they, and what I/O port ranges they would use. Where in the source tree should I place such code? Southbridge? The changes I made are described in two attached patches, one to southbridge/intel/i82371eb, one to mainboard/asus/p2bls. My coreboot and linux boot log is also attached. This is also RFC and is not signed off at this point, but comments are welcome. Regards Keith

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#110: Allow for per-device subsystem IDs
by coreboot Oct. 1, 2010

Oct. 1, 2010

#110: Allow for per-device subsystem IDs ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: enhancement | Status: new Priority: minor | Milestone: Component: coreboot | Version: v3 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Currently both v2 and v3 only allow us to use one global set of PCI subsystem IDs, which is too simplistic. In theory (and often in practice) each PCI device has (or can have) its own subsystem ID. We should fix this, at least in v3, possibly also in v2. See also http://www.coreboot.org/pipermail/coreboot/2008-July/036514.html -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/110> coreboot <http://www.coreboot.org/>

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#152: v3 Geode cs5536 UART2 wrongly configured
by coreboot Oct. 1, 2010

Oct. 1, 2010

#152: v3 Geode cs5536 UART2 wrongly configured -------------------------------------------+-------------------------------- Reporter: edwin_beasant@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Going mainstream Component: coreboot | Version: v3 Keywords: serial com2 geode cs5536 | Dependencies: Patchstatus: patch needs review | -------------------------------------------+-------------------------------- The UART2 on the AMD cs5536 is incorrectly configured in two places in v3 code and also in v2. GPIO lines 4 and 3 are swapped and also incorrectly put in IR mode receive (compound fault). This patch corrects the v3 late configuration and the v3 and v2 early (stage1/cache as ram) mis-configuration of UART2 to addres 0x3f8 not the standard 0x2f8 for COM2. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/152> coreboot <http://www.coreboot.org/>

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flashrom patch: add support for Abit AB-BM6 board
by Tim ter Laak Sept. 13, 2010

Sept. 13, 2010

Hello all, This patch adds support for the Abit AB-BM6 mainboard to flashrom. The biggest part is a generic function to lower a GPIO line on the PIIX4E southbridge, copied and adapted from its ich_gpio_raise() counterpart (mostly lower instead of raise, followed names from the PIIX4E datasheet). The board specific function then uses this to lower GPO 26. Signed-off-by: Tim ter Laak <timl(a)scintilla.utwente.nl> --- The patch was made from the flashrom subdir, because svn diff from the top-level coreboot dir (as per the directions in the Development Guidelines on the wiki) didn't seem to work for me. Probably because flashrom is fetched externally when checking out coreboot? Anyway, I hope this is okay. If you really prefer a diff from the top-level dir just let me know, and I'll regenerate it with gnu diff. Kind regards, Tim. Index: board_enable.c =================================================================== --- board_enable.c (revision 3559) +++ board_enable.c (working copy) @@ -349,6 +349,58 @@ } /** + * Set the specified GPIO on the specified PIIX4 southbridge to low. + * + * @param name The name of this board. + * @param piix_vendor PCI vendor ID of the specified PIIX4 southbridge. (0x8086) + * @param piix_device PCI device ID of the specified PIIX4 southbridge, function Power Management (0x7113 for PIIX4E) + * @param pmbase_reg PMBASE register offset in the bridge. (0x40 for PIIX4E) + * @param pmbase_mask PMBASE bitmask (0xFFC0) + * @param gporeg Offset of GPOREG register in I/O space, relative to GPIOBASE. (0x34) + * @param gpio_bit The bit (GPIO) which shall be set to low. + * @return If the write-enable was successful return 0, otherwise return -1. + */ +static int piix4_gpio_lower(const char *name, uint16_t piix_vendor, + uint16_t piix_device, uint8_t pmbase_reg, + uint8_t gporeg, uint32_t pmbase_mask, + unsigned int gpio_bit) +{ + struct pci_dev *dev; + uint16_t pmbar; + uint32_t reg32; + + dev = pci_dev_find(piix_vendor, piix_device); /* Intel PIIX4 ACPI function */ + if (!dev) { + fprintf(stderr, "\nERROR: PIIX4 dev %4x:%4x not found.\n", + piix_vendor, piix_device); + return -1; + } + + /* Use PMBASE register to find the I/O space for GPIO. */ + pmbar = pci_read_word(dev, pmbase_reg) & pmbase_mask; + + /* Set specified GPIO to high. */ + reg32 = INL(pmbar + gporeg); + OUTB(0x00, 0xEB); /* dummy write to unused port as delay */ + + reg32 &= ~(1 << gpio_bit); + OUTL(reg32, pmbar + gporeg); + OUTB(0x00, 0xEB); /* another delay */ + + return 0; +} + +/** + * Suited for Abit AB-BM6. + */ +static int piix4_gpio26_lower(const char *name) +{ + return piix4_gpio_lower(name, 0x8086, 0x7113, 0x40, 0x34, 0xffc0, 26); +} + + + +/** * Suited for Acorp 6A815EPD. */ static int board_acorp_6a815epd(const char *name) @@ -672,6 +724,8 @@ NULL, NULL, "GIGABYTE GA-7VT600", board_biostar_p4m80_m4}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI K8T Neo2", w83627thf_gpio4_4_raise_2e}, + {0x8086, 0x7190, 0x0000, 0x0000, 0x8086, 0x7110, 0x0000, 0x0000, + "abit", "ab-bm6", "Abit AB-BM6", piix4_gpio26_lower}, {0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */ };

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