May 2009 - coreboot - mail.coreboot.org

#123: layout file
by coreboot Jan. 15, 2010

Jan. 15, 2010

#123: layout file -------------------------------------+-------------------------------------- Reporter: vivanov@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: v2 Keywords: layout address offset | Dependencies: Patchstatus: there is no patch | -------------------------------------+-------------------------------------- Hello, I am trying to update the BIOS "ST M50FW080" and get the following incomprehensibility - layout file works in a strange way 1) saved the current BIOS {{{ $ flashrom --read flash18_saved.rom }}} 2) then I filled first 512K of this file with zeros (it is needed because new BIOS will have 512K size) 3) then I created rom.layout file to use the normal image only: {{{ 00000000:0007ffff stuff 00080000:000fffff normal }}} 4) and started to upgrade BIOS {{{ $ flashrom --write --layout rom.layout --image flash18_saved.rom }}} And get the following: {{{ Looking for "normal"... found. Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH4/ICH4-L", enabling flash write... OK. Found chip "ST M50FW080" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0000 at address: 0x00000000SKIPPED 0001 at address: 0x00010000SKIPPED 0002 at address: 0x00020000SKIPPED 0003 at address: 0x00030000SKIPPED 0004 at address: 0x00040000SKIPPED 0005 at address: 0x00050000SKIPPED 0006 at address: 0x00060000SKIPPED '''0007 at address: 0x00070000DONE BLOCK 0x70000''' 0008 at address: 0x00080000SKIPPED 0009 at address: 0x00090000SKIPPED 0010 at address: 0x000a0000SKIPPED 0011 at address: 0x000b0000SKIPPED 0012 at address: 0x000c0000SKIPPED 0013 at address: 0x000d0000SKIPPED 0014 at address: 0x000e0000SKIPPED 0015 at address: 0x000f0000SKIPPED }}} '''Next''' I changed the rom.layout file like follows: {{{ # cat rom.layout 00000000:00080000 stuff 00080000:000fffff normal }}} and get the '''right''' behaviour: {{{ # flashrom --write --layout rom.layout --image normal --verify flash18_saved.rom Looking for "normal"... found. Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH4/ICH4-L", enabling flash write... OK. Found chip "ST M50FW080" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0000 at address: 0x00000000SKIPPED 0001 at address: 0x00010000SKIPPED 0002 at address: 0x00020000SKIPPED 0003 at address: 0x00030000SKIPPED 0004 at address: 0x00040000SKIPPED 0005 at address: 0x00050000SKIPPED 0006 at address: 0x00060000SKIPPED 0007 at address: 0x00070000SKIPPED 0008 at address: 0x00080000SKIPPED 0009 at address: 0x00090000SKIPPED 0010 at address: 0x000a0000SKIPPED 0011 at address: 0x000b0000SKIPPED 0012 at address: 0x000c0000SKIPPED 0013 at address: 0x000d0000SKIPPED 0014 at address: 0x000e0000SKIPPED 0015 at address: 0x000f0000SKIPPED Verifying flash... VERIFIED. }}} Please explain me which rom layout I should use to update the last 512K of 1M BIOS? -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/123> coreboot <http://www.coreboot.org/>

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#133: Create a typical failures FAQ
by coreboot Jan. 15, 2010

Jan. 15, 2010

#133: Create a typical failures FAQ ---------------------------------------+------------------------------------ Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: major | Milestone: Component: flashrom | Version: Keywords: faq documentation debug | Dependencies: Patchstatus: there is no patch | ---------------------------------------+------------------------------------ Briefly describe what flashrom needs to do to successfully identify, read and write/erase the different type of chips to optimize the remote debugging process with new users. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/133> coreboot <http://www.coreboot.org/>

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#130: flashrom segfault (with backtrace)
by coreboot Jan. 15, 2010

Jan. 15, 2010

#130: flashrom segfault (with backtrace) ---------------------------------+------------------------------------------ Reporter: fragabr@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ I want to test flashrom with a supported motherboard (Asus M2N-E with Linux 2.6.30-rc4) and it segfaults when I run it. I'm using the latest libpci (3.1.2): {{{ Calibrating delay loop... OK. No coreboot table found. Segmentation fault }}} Backtrace: {{{ #0 0x00007f1395141d49 in pci_fill_info_v31 () from /usr/local/lib/libpci.so.3 #1 0x00007f1395143c59 in pci_filter_match () from /usr/local/lib/libpci.so.3 #2 0x000000000040732f in ?? () #3 0x00000000004016f8 in ?? () #4 0x0000000000406d46 in ?? () #5 0x00007f1394df24f6 in __libc_start_main () from /lib64/libc.so.6 #6 0x0000000000401619 in ?? () #7 0x00007fff9d579e98 in ?? () #8 0x000000000000001c in ?? () #9 0x0000000000000001 in ?? () #10 0x00007fff9d57ab55 in ?? () #11 0x0000000000000000 in ?? () }}} -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/130> coreboot <http://www.coreboot.org/>

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flashrom on MCP73
by Fabrício Ceolin Oct. 8, 2009

Oct. 8, 2009

Hi guys, We are trying to make flashrom work on http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=858&… Chipset MCP73 / SIP chipset Macronix MX25L8005. We made modifications using a enable_flash_mcp55 function, but does't work. ./flashrom -V -c MX25L8005 -r -f rom Calibrating delay loop... 627M loops per second, 100 myus = 199 us. OK. No coreboot table found. Found chipset "NVIDIA MCP73", enabling flash write... OK. Probing for Macronix MX25L8005, 1024 KB: spi_command called, but no SPI chipset/strapping detected No EEPROM/flash device found. Force read (-f -r -c) requested, forcing chip probe success: Probing for Macronix MX25L8005, 1024 KB: Found chip "Macronix MX25L8005" (1024 KB) at physical address 0xfff00000. Force reading flash... spi_chip_read called, but no SPI chipset/strapping detected 0 done. How can I do works? Are there any hints? Thanks! -- Fabrício Ceolin

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#121: flashrom runtime error
by coreboot Aug. 29, 2009

Aug. 29, 2009

#121: flashrom runtime error ---------------------------------+------------------------------------------ Reporter: lymanrb@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ I got such errors when running flashrom. {{{ Calibrating delay loop... OK. Can't mmap memory using /dev/mem: Invalid argument }}} My env {{{ Linux xxx 2.6.28-ARCH #1 SMP PREEMPT Sun Jan 18 19:41:52 UTC 2009 x86_64 Intel(R) Core(TM)2 Duo CPU T7250 @ 2.00GHz GenuineIntel GNU/Linux core/pciutils 3.0.3-1 [installed] (base) PCI bus configuration space access library and tools core/zlib 1.2.3.3-3 [installed] (base) A compression/decompression Library $ ./flashrom -R flashrom r3869 }}} -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/121> coreboot <http://www.coreboot.org/>

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sony vaio pcg sr1k
by misi e July 21, 2009

July 21, 2009

Hello, as I posted on the blog of Uwe, I have a sony vaio pcg sr1k laptop, and wonder if I could flash it with coreboot. The box has Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge chipset. hovewer the results of the following commands are not encouriging, please tell me if there is any chance to get coreboot working. Please find attached the outpoot of the commands. sudo superiotool -dV > siot.out lspci -tvnn > lspci.out sudo flashrom -V

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#137: S2895 no function after coreboot 2 flash
by coreboot July 15, 2009

July 15, 2009

#137: S2895 no function after coreboot 2 flash --------------------------+------------------------------------------------- Reporter: anonymous | Type: defect Status: new | Priority: major Milestone: | Component: buildrom Version: v2 | Keywords: Dependencies: | Patchstatus: there is no patch --------------------------+------------------------------------------------- Hi Guys, I am not sure whether i am correct here with you guys. But i have some troubles after flashing the tyan-s2895.rom that has been generated with seabios as payload by the buildrom tool. There are no logs in the log folders and everything worked fine. But after flashing the coreboot bios to the board using "flashrom -v -w tyan-s2895.rom" and i "halt" the system, it will come up for a second and switches off immediately. I tried clearing the CMOS, but this did not solve the problem. Any idea what i am doing wrong? -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/137> coreboot <http://www.coreboot.org/>

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[PATCH] v3 Resource allocator to v2
by Myles Watson July 11, 2009

July 11, 2009

This patch series makes v2 more similar to v3. It splits resource allocation into read, compute, allocate. There is no more mutual recursion. They go in this order: 1. white.diff 2. read_first.diff 3. domain_resources.diff 4. constraint.diff 5. compute_allocate.diff It is boot tested on SimNOW and qemu. domain_resources needs to be expanded to include other southbridges and domains. I just wanted early feedback rather than late. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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msrtool CS5536 interrupt and DIVIL LBAR MSRs
by Peter Stuge July 9, 2009

July 9, 2009

Can someone please review these register definitions? Thank you! //Peter

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[patch] fix intel 82810 onboard VGA and SDRAM functions
by Elia Yehuda July 5, 2009

July 5, 2009

This patch enables the onboard VGA found on 82810 boards and fixes the memory procedures to support different kinds of DIMMs. also, support for 82810e board had been added. The only drawback from this patch is the HAVE_HIGH_TABLES being disabled since it disables (for unknown reason) the onboard VGA. Signed-off-by: Elia Yehuda <z4ziggy(a)gmail.com>

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