March 2008 - coreboot - mail.coreboot.org

PCI irq routing
by Nikolay Petukhov April 2, 2008

April 2, 2008

Hi, all. Now coreboot perform irq routing for some boards. You can see this by executing commands like this: grep -r pci_assign_irqs coreboot/src/* This basically AMD/LX based boards: pcengines/alix1c, digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800. Also for AMD/GX1 based boards need a patch [http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5…] for the right setup irq. AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320, bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p I have two ideas. 1. Delete duplicate code from AMD/LX based boards. 2. Add irq routing for AMD/GX1 boards in coreboot. The pirq.patch for irq routing logically consist from of two parts: First part of pirq.patch independent from type chipsets and assign irq for ever PCI device. It part based on AMD/LX write_pirq_routing_table() function. Second part of pirq.part depends of type chipset and set PIRQx linies in interrupt router. Now this part supports only CS5530/5536 interrupt routers. Irq routing functionality is include through macro PIRQ_ROUTE in Config.lb. Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on TeleVideo TC7020 http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html. -- Nikolay

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[PATCH] Disable integrated Intel 3100 devices properly
by Ed Swierk April 1, 2008

April 1, 2008

Setting an integrated southbridge device (like SATA or USB2.0) to "off" in Config.lb should cause the PCI device not to respond to configuration requests. The code that takes care of this for the Intel 3100 is in src/southbridge/intel/i3100/i3100.c. Unfortunately I copied the esb6300 implementation without noticing that it makes no sense at all on the Intel 3100. The attached patch implements this properly for the Intel 3100. --Ed

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Re: [coreboot] [LinuxBIOS] FILO with the USB
by Corey Osgood April 1, 2008

April 1, 2008

Sorry to be a pain, but any progress with this? Thanks, Corey > OK, thank you. > My employer approved the submission. I"ll do it soon. > > On Nov 26, 2007 1:24 AM, Corey Osgood <[EMAIL PROTECTED]> wrote: > > > Fridel Fainshtein wrote: > > > OK, > > > > > > supposing FILO USB works > > > How do I submit the corrections? > > > > > > > http://www.linuxbios.org/Development_Guidelines#How_to_contribute > > > > In short form: > > 1) cd to the filo-0.5/ folder > > 2) svn add * -R (if you've created any new files, be sure to move files > > you don't want added first) > > 3) svn diff > clever_patchname.patch > > 4) edit the patch, add a short description of what the patch does (which > > goes into the svn commit log) and a Signed-off-by: line, per the > > guidelines linked to above. > > > > Thanks! > > -Corey > >

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[PATCH] Hardcode PCI devices in Intel southbridge early init code
by Ed Swierk April 1, 2008

April 1, 2008

The early init code of several Intel southbridge chipsets calls pci_locate_device() to locate the SMBus controller and LPC bridge devices on the PCI bus. Since these devices are always located at a fixed PCI bus:device:function, the code can be simplified by hardcoding the devices. Signed-off-by: Ed Swierk <eswierk(a)arastra.com>

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gcc 4.3.0 and the direction flag
by Carl-Daniel Hailfinger March 31, 2008

March 31, 2008

Hi, do we clear the x86 direction flag everywhere before and after we run code not under our control? I'm thinking of option ROM code and initial asm code as examples. Regards, Carl-Daniel

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r3204 - trunk/payloads/libpayload/i386
by svn＠coreboot.org March 31, 2008

March 31, 2008

Author: uwe Date: 2008-03-31 23:02:29 +0200 (Mon, 31 Mar 2008) New Revision: 3204 Modified: trunk/payloads/libpayload/i386/head.S trunk/payloads/libpayload/i386/main.c Log: Libpayload fixes to prevent triple-faults when running in QEMU. Let the linker figure out the correct address and just CALL the start_main entry point. Signed-off-by: Klaus Schnass <dev(a)stuffit.at> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/payloads/libpayload/i386/head.S =================================================================== --- trunk/payloads/libpayload/i386/head.S 2008-03-31 20:30:18 UTC (rev 3203) +++ trunk/payloads/libpayload/i386/head.S 2008-03-31 21:02:29 UTC (rev 3204) @@ -50,31 +50,26 @@ /* No interrupts, please. */ cli - /* Get the current stack pointer. */ + /* Store current stack pointer. */ movl %esp, %esi + /* Setup new stack. */ movl _istack, %ebx - /* lret needs %cs in the stack, so copy it over. */ - movw %cs, 4(%ebx) + movl (%ebx), %esp - /* - * Exchange the current stack pointer for the one in the initial - * stack (which happens to be the new stack pointer). - */ - xchgl %esi, 16(%ebx) + /* Save old stack pointer. */ + pushl %esi - /* Set the new stack pointer. */ - movl %esi, %esp - - /* Return into the main entry function and go. */ - lret - + /* Let's rock. */ + call start_main + _leave: - movl _istack, %ebx + /* Get old stack pointer. */ + popl %ebx - /* Restore the stack pointer from the storage area. */ - movl 16(%ebx), %esp + /* Restore old stack. */ + movl %esp, %ebx /* Return to the original context. */ lret Modified: trunk/payloads/libpayload/i386/main.c =================================================================== --- trunk/payloads/libpayload/i386/main.c 2008-03-31 20:30:18 UTC (rev 3203) +++ trunk/payloads/libpayload/i386/main.c 2008-03-31 21:02:29 UTC (rev 3204) @@ -36,17 +36,12 @@ * stack we store the original stack pointer from the calling application. */ -static void start_main(void); extern void _leave(void); static struct { - uint32_t eip[2]; - uint32_t raddr[2]; uint32_t esp; -} initial_stack __attribute__ ((section(".istack"))) = { - { (uint32_t) start_main, 0 }, - { (uint32_t) _leave, 0 }, - (uint32_t) & initial_stack, +} initial_stack __attribute__ ((section(".istack"))) = { + (uint32_t) &initial_stack, }; void *_istack = &initial_stack; @@ -55,7 +50,7 @@ * This is our C entry function - set up the system * and jump into the payload entry point. */ -static void start_main(void) +void start_main(void) { extern int main(void); @@ -70,9 +65,10 @@ * user gets control goes here. */ - /* Go to the entry point. */ - - /* In the future we may care about the return value. */ + /* + * Go to the entry point. + * In the future we may care about the return value. + */ (void) main(); /*

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[PATCH] coreinfo: CMOS Dump support and other fixes
by Uwe Hermann March 31, 2008

March 31, 2008

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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r3203 - trunk/payloads/coreinfo
by svn＠coreboot.org March 31, 2008

March 31, 2008

Author: uwe Date: 2008-03-31 22:30:18 +0200 (Mon, 31 Mar 2008) New Revision: 3203 Added: trunk/payloads/coreinfo/nvram_module.c Modified: trunk/payloads/coreinfo/Kconfig trunk/payloads/coreinfo/Makefile trunk/payloads/coreinfo/coreboot_module.c trunk/payloads/coreinfo/coreinfo.c trunk/payloads/coreinfo/coreinfo.h trunk/payloads/coreinfo/cpuinfo_module.c trunk/payloads/coreinfo/pci_module.c Log: Add support for an "NVRAM Dump" screen in coreinfo (optional), as well as for displaying the current date/time in the lower-right corner (optional). Also, only build/use coreinfo modules which were selected in kconfig. This makes coreinfo truly modular, and you can save quite a bit of ROM space by disabling unwanted parts of coreinfo. Finally, simplify the Makefile a bit by getting rid of MODULES (and only using OBJECTS). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/coreinfo/Kconfig =================================================================== --- trunk/payloads/coreinfo/Kconfig 2008-03-31 20:21:49 UTC (rev 3202) +++ trunk/payloads/coreinfo/Kconfig 2008-03-31 20:30:18 UTC (rev 3203) @@ -24,10 +24,20 @@ mainmenu "coreinfo Configuration" +menu "General settings" + +# TODO: Needs changes in coreinfo, won't update without keypress currently. +config SHOW_DATE_TIME + bool "Show current date/time in the menu" + default y + help + Show the current date and time in the lower-right corner of + the coreinfo menu. + +endmenu + menu "Modules" -# TODO: Currently none of these options has any effect. - config MODULE_COREBOOT bool "Enable the coreboot module" default y @@ -40,5 +50,9 @@ bool "Enable the PCI info module" default y +config MODULE_NVRAM + bool "Enable the NVRAM dump module" + default y + endmenu Modified: trunk/payloads/coreinfo/Makefile =================================================================== --- trunk/payloads/coreinfo/Makefile 2008-03-31 20:21:49 UTC (rev 3202) +++ trunk/payloads/coreinfo/Makefile 2008-03-31 20:30:18 UTC (rev 3203) @@ -46,15 +46,15 @@ CC = gcc CROSS_CFLAGS = -m32 -INCLUDES = -I../libpayload/include \ +INCLUDES = -I../libpayload/include -Ibuild \ -I$(shell $(CC) $(CROSS_CFLAGS) -print-search-dirs | \ head -n 1 | cut -d' ' -f2)include LIBPAYLOAD = ../libpayload/libpayload.a LIBGCC := $(shell $(CC) $(CROSS_CFLAGS) -print-libgcc-file-name) CFLAGS := -Wall -Werror -Os -fno-stack-protector -nostdinc $(INCLUDES) -MODULES = cpuinfo_module.o cpuid.S.o pci_module.o coreboot_module.o -OBJECTS = coreinfo.o -OBJS = $(patsubst %,$(obj)/%,$(OBJECTS)) $(patsubst %,$(obj)/%,$(MODULES)) +OBJECTS = cpuinfo_module.o cpuid.S.o pci_module.o coreboot_module.o \ + nvram_module.o coreinfo.o +OBJS = $(patsubst %,$(obj)/%,$(OBJECTS)) TARGET = $(obj)/coreinfo.elf ifeq ($(strip $(HAVE_DOTCONFIG)),) Modified: trunk/payloads/coreinfo/coreboot_module.c =================================================================== --- trunk/payloads/coreinfo/coreboot_module.c 2008-03-31 20:21:49 UTC (rev 3202) +++ trunk/payloads/coreinfo/coreboot_module.c 2008-03-31 20:30:18 UTC (rev 3203) @@ -20,6 +20,8 @@ #include <coreboot_tables.h> #include "coreinfo.h" +#ifdef CONFIG_MODULE_COREBOOT + #define MAX_MEMORY_COUNT 5 static struct { @@ -252,3 +254,10 @@ .init = coreboot_module_init, .redraw = coreboot_module_redraw, }; + +#else + +struct coreinfo_module coreboot_module = { +}; + +#endif Modified: trunk/payloads/coreinfo/coreinfo.c =================================================================== --- trunk/payloads/coreinfo/coreinfo.c 2008-03-31 20:21:49 UTC (rev 3202) +++ trunk/payloads/coreinfo/coreinfo.c 2008-03-31 20:30:18 UTC (rev 3203) @@ -25,11 +25,21 @@ extern struct coreinfo_module cpuinfo_module; extern struct coreinfo_module pci_module; extern struct coreinfo_module coreboot_module; +extern struct coreinfo_module nvram_module; struct coreinfo_module *modules[] = { +#ifdef CONFIG_MODULE_CPUINFO &cpuinfo_module, +#endif +#ifdef CONFIG_MODULE_PCI &pci_module, +#endif +#ifdef CONFIG_MODULE_COREBOOT &coreboot_module, +#endif +#ifdef CONFIG_MODULE_NVRAM + &nvram_module, +#endif }; static WINDOW *modwin; @@ -63,6 +73,16 @@ ptr += sprintf(ptr, "F%d: %s ", i + 1, modules[i]->name); mvprintw(23, 0, menu); + +#ifdef CONFIG_SHOW_DATE_TIME + mvprintw(23, 59, "%02d/%02d/20%02d - %02d:%02d:%02d", + bcd2dec(nvram_read(NVRAM_RTC_MONTH)), + bcd2dec(nvram_read(NVRAM_RTC_DAY)), + bcd2dec(nvram_read(NVRAM_RTC_YEAR)), + bcd2dec(nvram_read(NVRAM_RTC_HOURS)), + bcd2dec(nvram_read(NVRAM_RTC_MINUTES)), + bcd2dec(nvram_read(NVRAM_RTC_SECONDS))); +#endif } static void center(int row, const char *str) Modified: trunk/payloads/coreinfo/coreinfo.h =================================================================== --- trunk/payloads/coreinfo/coreinfo.h 2008-03-31 20:21:49 UTC (rev 3202) +++ trunk/payloads/coreinfo/coreinfo.h 2008-03-31 20:30:18 UTC (rev 3203) @@ -21,6 +21,7 @@ #define COREINFO_H_ #include <libpayload.h> +#include <config.h> #include <curses.h> struct coreinfo_module { Modified: trunk/payloads/coreinfo/cpuinfo_module.c =================================================================== --- trunk/payloads/coreinfo/cpuinfo_module.c 2008-03-31 20:21:49 UTC (rev 3202) +++ trunk/payloads/coreinfo/cpuinfo_module.c 2008-03-31 20:30:18 UTC (rev 3203) @@ -23,6 +23,8 @@ #include "coreinfo.h" #include <arch/rdtsc.h> +#ifdef CONFIG_MODULE_CPUINFO + #define VENDOR_INTEL 0x756e6547 #define VENDOR_AMD 0x68747541 #define VENDOR_CYRIX 0x69727943 @@ -267,5 +269,11 @@ .name = "CPU Info", .init = cpuinfo_module_init, .redraw = cpuinfo_module_redraw, - .handle = NULL, }; + +#else + +struct coreinfo_module cpuinfo_module = { +}; + +#endif Added: trunk/payloads/coreinfo/nvram_module.c =================================================================== --- trunk/payloads/coreinfo/nvram_module.c (rev 0) +++ trunk/payloads/coreinfo/nvram_module.c 2008-03-31 20:30:18 UTC (rev 3203) @@ -0,0 +1,68 @@ +/* + * This file is part of the coreinfo project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "coreinfo.h" + +#ifdef CONFIG_MODULE_NVRAM + +/** + * Dump 256 bytes of NVRAM. + */ +static void dump_nvram(WINDOW *win, int row, int col) +{ + int i, x = 0, y = 0; + + for (i = 1; i < 257; i++) { + mvwprintw(win, row + y, col + x, "%02x ", nvram_read(i - 1)); + x += 3; + if (i % 16 == 0) { + y++; /* Start a newline after 16 bytes. */ + x = 0; + } + if (i % 64 == 0) { + y++; /* Add an empty line after 64 bytes. */ + x = 0; + } + } +} + +static int nvram_module_redraw(WINDOW *win) +{ + print_module_title(win, "NVRAM Dump"); + dump_nvram(win, 2, 1); + return 0; +} + +static int nvram_module_init(void) +{ + return 0; +} + +struct coreinfo_module nvram_module = { + .name = "NVRAM", + .init = nvram_module_init, + .redraw = nvram_module_redraw, +}; + +#else + +struct coreinfo_module nvram_module = { +}; + +#endif Modified: trunk/payloads/coreinfo/pci_module.c =================================================================== --- trunk/payloads/coreinfo/pci_module.c 2008-03-31 20:21:49 UTC (rev 3202) +++ trunk/payloads/coreinfo/pci_module.c 2008-03-31 20:30:18 UTC (rev 3203) @@ -20,6 +20,8 @@ #include <arch/io.h> #include "coreinfo.h" +#ifdef CONFIG_MODULE_PCI + struct pci_devices { unsigned short device; unsigned int id; @@ -282,3 +284,10 @@ .redraw = pci_module_redraw, .handle = pci_module_handle, }; + +#else + +struct coreinfo_module pci_module = { +}; + +#endif

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[PATCH] libpayload: Fix upper 128 NVRAM bytes handling
by Uwe Hermann March 31, 2008

March 31, 2008

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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r3202 - in trunk/payloads/libpayload: . curses drivers
by svn＠coreboot.org March 31, 2008

March 31, 2008

Author: uwe Date: 2008-03-31 22:21:49 +0200 (Mon, 31 Mar 2008) New Revision: 3202 Modified: trunk/payloads/libpayload/Config.in trunk/payloads/libpayload/curses/Makefile.inc trunk/payloads/libpayload/drivers/nvram.c Log: Fix the NVRAM access functions to work correctly for the upper 128 bytes of NVRAM (if enabled). For most chipsets this means using I/O ports 0x72/0x73, but at least on some VIA chipsets (I tested the VIA VT8237R on actual hardware) these ports won't work and you have to use 0x74/0x75. Thus, make this a Kconfig option for now. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/libpayload/Config.in =================================================================== --- trunk/payloads/libpayload/Config.in 2008-03-31 15:21:24 UTC (rev 3201) +++ trunk/payloads/libpayload/Config.in 2008-03-31 20:21:49 UTC (rev 3202) @@ -72,6 +72,22 @@ bool "Support for reading/writing NVRAM bytes" default y +config RTC_PORT_EXTENDED_VIA + bool "Extended RTC ports are 0x74/0x75" + default n + help + For recent chipsets with 256 NVRAM bytes, you have to access the + upper 128 bytes (128-255) using two different I/O ports, + usually 0x72/0x73. + + On some chipsets this can be a different set of ports, though. + The VIA VT8237R for example only recognizes the ports 0x74/0x75 + for accessing the high 128 NVRAM bytes (as seems to be the case for + multiple VIA chipsets). + + If you want to read or write CMOS bytes on computers with one of + these chipsets, say 'y' here. + endmenu menu "Build Options" Modified: trunk/payloads/libpayload/curses/Makefile.inc =================================================================== --- trunk/payloads/libpayload/curses/Makefile.inc 2008-03-31 15:21:24 UTC (rev 3201) +++ trunk/payloads/libpayload/curses/Makefile.inc 2008-03-31 20:21:49 UTC (rev 3202) @@ -27,7 +27,7 @@ ## SUCH DAMAGE. ## -TARGETS-$(CONFIG_TINYCURSES) += curses/keyboard.o +TARGETS-$(CONFIG_TINYCURSES) += curses/keyboard.o TARGETS-$(CONFIG_TINYCURSES) += curses/tinycurses.o TARGETS-$(CONFIG_TINYCURSES) += curses/speaker.o TARGETS-$(CONFIG_TINYCURSES) += curses/colors.o Modified: trunk/payloads/libpayload/drivers/nvram.c =================================================================== --- trunk/payloads/libpayload/drivers/nvram.c 2008-03-31 15:21:24 UTC (rev 3201) +++ trunk/payloads/libpayload/drivers/nvram.c 2008-03-31 20:21:49 UTC (rev 3202) @@ -42,9 +42,31 @@ #include <libpayload.h> -#define RTC_PORT 0x70 /** + * PCs can have either 64 (very old ones), 128, or 256 bytes of CMOS RAM. + * + * Usually you access the lower 128 CMOS bytes via I/O port 0x70/0x71. + * For more recent chipsets with 256 bytes, you have to access the upper + * 128 bytes (128-255) using two different registers, usually 0x72/0x73. + * + * On some chipsets this can be different, though. The VIA VT8237R for example + * only recognizes the ports 0x74/0x75 for accessing the high 128 CMOS bytes + * (as seems to be the case for multiple VIA chipsets). + * + * It's very chipset-specific if and how the upper 128 bytes are enabled at + * all, but this work should be done in coreboot anyway. Libpayload assumes + * that coreboot has properly enabled access to the upper 128 bytes and + * doesn't try to do this on its own. + */ +#define RTC_PORT_STANDARD 0x70 +#ifdef CONFIG_RTC_PORT_EXTENDED_VIA +#define RTC_PORT_EXTENDED 0x74 +#else +#define RTC_PORT_EXTENDED 0x72 +#endif + +/** * Read a byte from the specified NVRAM address. * * @param addr The NVRAM address to read a byte from. @@ -52,8 +74,10 @@ */ u8 nvram_read(u8 addr) { - outb(addr, RTC_PORT); - return inb(RTC_PORT + 1); + u16 rtc_port = addr < 128 ? RTC_PORT_STANDARD : RTC_PORT_EXTENDED; + + outb(addr, rtc_port); + return inb(rtc_port + 1); } /** @@ -64,6 +88,8 @@ */ void nvram_write(u8 val, u8 addr) { - outb(addr, RTC_PORT); - outb(val, RTC_PORT + 1); + u16 rtc_port = addr < 128 ? RTC_PORT_STANDARD : RTC_PORT_EXTENDED; + + outb(addr, rtc_port); + outb(val, rtc_port + 1); }

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