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October 2008

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r3625 build service
by coreboot information Oct. 1, 2008

Oct. 1, 2008

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3625 to the coreboot source repository and caused the following changes: Change Log: Enable all available devices on the ASUS A8N-E (trivial). This is in preparation for actually making the devices work (which needs some extra code). Also, fix the incorrect mainboard subsystem IDs. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3625&device=m2v-mx_se&vend… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3625&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3625&device=epia-cn&vendor… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3624 build service
by coreboot information Oct. 1, 2008

Oct. 1, 2008

Dear coreboot readers! This is the automated build check service of coreboot. The developer "hailfinger" checked in revision 3624 to the coreboot source repository and caused the following changes: Change Log: The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of code to use it. That makes the code more readable and also less error-prone. Abuild tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3624&device=m2v-mx_se&vend… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3624&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3624&device=epia-cn&vendor… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3625 - trunk/coreboot-v2/src/mainboard/asus/a8n_e
by svn＠coreboot.org Oct. 1, 2008

Oct. 1, 2008

Author: uwe Date: 2008-10-01 15:10:39 +0200 (Wed, 01 Oct 2008) New Revision: 3625 Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb Log: Enable all available devices on the ASUS A8N-E (trivial). This is in preparation for actually making the devices work (which needs some extra code). Also, fix the incorrect mainboard subsystem IDs. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb 2008-10-01 12:52:52 UTC (rev 3624) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb 2008-10-01 13:10:39 UTC (rev 3625) @@ -165,7 +165,7 @@ device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/ite/it8712f # Super I/O - device pnp 2e.0 off # Floppy + device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 @@ -174,13 +174,14 @@ io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 + device pnp 2e.2 off # Com2 (N/A on this board) io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.3 on # Parallel port io 0x60 = 0x378 irq 0x70 = 7 + drq 0x74 = 3 end device pnp 2e.4 on # Environment controller io 0x60 = 0x290 @@ -198,6 +199,7 @@ irq 0x71 = 2 end device pnp 2e.7 on # GPIO config + io 0x60 = 0x0800 # Set GPIO 1 & 2 io 0x25 = 0x0000 # Set GPIO 3 & 4 @@ -212,9 +214,17 @@ io 0xc8 = 0x0000 io 0xca = 0x0500 end - device pnp 2e.8 off end # Midi port - device pnp 2e.9 off end # Game port - device pnp 2e.a off end # IR + device pnp 2e.8 on # Midi port + io 0x60 = 0x300 + irq 0x70 = 10 + end + device pnp 2e.9 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.a off # IR (N/A on this board) + io 0x60 = 0x310 + irq 0x70 = 11 + end end end device pci 1.1 on # SM 0 @@ -245,8 +255,8 @@ end device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 - device pci 4.0 off end # Onboard audio (ACI) - device pci 4.1 off end # Onboard modem (MCI) + device pci 4.0 on end # Onboard audio (ACI) + device pci 4.1 off end # Onboard modem (MCI), N/A device pci 6.0 on end # IDE device pci 7.0 on end # SATA 1 device pci 8.0 on end # SATA 0 Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2008-10-01 12:52:52 UTC (rev 3624) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2008-10-01 13:10:39 UTC (rev 3625) @@ -146,8 +146,8 @@ default CONFIG_IOAPIC = 1 default MAINBOARD_PART_NUMBER = "A8N-E" default MAINBOARD_VENDOR = "ASUS" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x2891 +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a default STACK_SIZE = 8 * 1024 default HEAP_SIZE = 16 * 1024 # Only use the option table in a normal image.

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[PATCH] v2: Use ARRAY_SIZE everywhere
by Carl-Daniel Hailfinger Oct. 1, 2008

Oct. 1, 2008

The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of code to use it. That makes the code more readable and also less error-prone. I'd appreciate test builds. I see v3 as the future and occassional patches to v2 are only intended to keep v2 roughly up to date with v3 code changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-array_size/src/southbridge/amd/cs5536/cs5536.c =================================================================== --- LinuxBIOSv2-array_size/src/southbridge/amd/cs5536/cs5536.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/southbridge/amd/cs5536/cs5536.c (Arbeitskopie) @@ -93,7 +93,7 @@ {FLASH_TYPE_NONE, 0, 0}, /* CS3, or Flash Device 3 */ }; -#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0])) +#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable)) uint32_t FlashPort[] = { MDD_LBAR_FLSH0, Index: LinuxBIOSv2-array_size/src/southbridge/amd/amd8111/amd8111_lpc.c =================================================================== --- LinuxBIOSv2-array_size/src/southbridge/amd/amd8111/amd8111_lpc.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/southbridge/amd/amd8111/amd8111_lpc.c (Arbeitskopie) @@ -77,7 +77,7 @@ ioapicregvalues[0].value_high = bsp_apicid<<(56-32); printk_debug("amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid); - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; Index: LinuxBIOSv2-array_size/src/southbridge/nvidia/ck804/ck804_early_setup.c =================================================================== --- LinuxBIOSv2-array_size/src/southbridge/nvidia/ck804/ck804_early_setup.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/southbridge/nvidia/ck804/ck804_early_setup.c (Arbeitskopie) @@ -102,7 +102,7 @@ #endif }; - setup_resource_map(ctrl_devport_conf, sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0])); + setup_resource_map(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf)); } @@ -121,7 +121,7 @@ #endif }; - setup_resource_map(ctrl_devport_conf_clear, sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0])); + setup_resource_map(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear)); } @@ -324,7 +324,7 @@ - setup_resource_map_x(ctrl_conf, sizeof(ctrl_conf)/sizeof(ctrl_conf[0])); + setup_resource_map_x(ctrl_conf, ARRAY_SIZE(ctrl_conf)); setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64); setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64); Index: LinuxBIOSv2-array_size/src/southbridge/nvidia/ck804/ck804_lpc.c =================================================================== --- LinuxBIOSv2-array_size/src/southbridge/nvidia/ck804/ck804_lpc.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/southbridge/nvidia/ck804/ck804_lpc.c (Arbeitskopie) @@ -82,7 +82,7 @@ l = (unsigned long *) ioapic_base; - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; Index: LinuxBIOSv2-array_size/src/southbridge/nvidia/ck804/ck804_early_setup_car.c =================================================================== --- LinuxBIOSv2-array_size/src/southbridge/nvidia/ck804/ck804_early_setup_car.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/southbridge/nvidia/ck804/ck804_early_setup_car.c (Arbeitskopie) @@ -105,12 +105,12 @@ for(j = 0; j < ck804_num; j++ ) { if(busn[j]==0) { //sb chain setup_resource_map_offset(ctrl_devport_conf, - sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]), + ARRAY_SIZE(ctrl_devport_conf), PCI_DEV(busn[j], 0, 0) , io_base[j]); continue; } setup_resource_map_offset(ctrl_devport_conf_b, - sizeof(ctrl_devport_conf_b)/sizeof(ctrl_devport_conf_b[0]), + ARRAY_SIZE(ctrl_devport_conf_b), PCI_DEV(busn[j], 0, 0) , io_base[j]); } } @@ -132,12 +132,12 @@ for(j = 0; j < ck804_num; j++ ) { if(busn[j]==0) { //sb chain setup_resource_map_offset(ctrl_devport_conf_clear, - sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]), + ARRAY_SIZE(ctrl_devport_conf_clear), PCI_DEV(busn[j], 0, 0) , io_base[j]); continue; } setup_resource_map_offset(ctrl_devport_conf_clear_b, - sizeof(ctrl_devport_conf_clear_b)/sizeof(ctrl_devport_conf_clear_b[0]), + ARRAY_SIZE(ctrl_devport_conf_clear_b), PCI_DEV(busn[j], 0, 0) , io_base[j]); } @@ -327,13 +327,13 @@ for(j=0; j<ck804_num; j++) { if(busn[j] == 0) { - setup_resource_map_x_offset(ctrl_conf_master, sizeof(ctrl_conf_master)/sizeof(ctrl_conf_master[0]), + setup_resource_map_x_offset(ctrl_conf_master, ARRAY_SIZE(ctrl_conf_master), PCI_DEV(busn[0],0,0), io_base[0]); continue; } - setup_resource_map_x_offset(ctrl_conf_slave, sizeof(ctrl_conf_slave)/sizeof(ctrl_conf_slave[0]), + setup_resource_map_x_offset(ctrl_conf_slave, ARRAY_SIZE(ctrl_conf_slave), PCI_DEV(busn[j],0,0), io_base[j]); } Index: LinuxBIOSv2-array_size/src/southbridge/nvidia/mcp55/mcp55_lpc.c =================================================================== --- LinuxBIOSv2-array_size/src/southbridge/nvidia/mcp55/mcp55_lpc.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/southbridge/nvidia/mcp55/mcp55_lpc.c (Arbeitskopie) @@ -106,7 +106,7 @@ l = (unsigned long *) ioapic_base; - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; Index: LinuxBIOSv2-array_size/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c =================================================================== --- LinuxBIOSv2-array_size/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c (Arbeitskopie) @@ -106,7 +106,7 @@ int j; for(j = 0; j < mcp55_num; j++ ) { setup_resource_map_offset(ctrl_devport_conf, - sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]), + ARRAY_SIZE(ctrl_devport_conf), PCI_DEV(busn[j], devn[j], 0) , io_base[j]); } } @@ -123,7 +123,7 @@ int j; for(j = 0; j < mcp55_num; j++ ) { setup_resource_map_offset(ctrl_devport_conf_clear, - sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]), + ARRAY_SIZE(ctrl_devport_conf_clear), PCI_DEV(busn[j], devn[j], 0) , io_base[j]); } @@ -327,23 +327,23 @@ for(j=0; j<mcp55_num; j++) { mcp55_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]); - setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]), + setup_resource_map_x_offset(ctrl_conf_1, ARRAY_SIZE(ctrl_conf_1), PCI_DEV(busn[j], devn[j], 0), io_base[j]); for(i=0; i<3; i++) { // three SATA - setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]), + setup_resource_map_x_offset(ctrl_conf_1_1, ARRAY_SIZE(ctrl_conf_1_1), PCI_DEV(busn[j], devn[j], i), io_base[j]); } if(busn[j] == 0) { - setup_resource_map_x_offset(ctrl_conf_mcp55_only, sizeof(ctrl_conf_mcp55_only)/sizeof(ctrl_conf_mcp55_only[0]), + setup_resource_map_x_offset(ctrl_conf_mcp55_only, ARRAY_SIZE(ctrl_conf_mcp55_only), PCI_DEV(busn[j], devn[j], 0), io_base[j]); } if( (busn[j] == 0) && (mcp55_num>1) ) { - setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]), + setup_resource_map_x_offset(ctrl_conf_master_only, ARRAY_SIZE(ctrl_conf_master_only), PCI_DEV(busn[j], devn[j], 0), io_base[j]); } - setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]), + setup_resource_map_x_offset(ctrl_conf_2, ARRAY_SIZE(ctrl_conf_2), PCI_DEV(busn[j], devn[j], 0), io_base[j]); } Index: LinuxBIOSv2-array_size/src/southbridge/sis/sis966/sis966_lpc.c =================================================================== --- LinuxBIOSv2-array_size/src/southbridge/sis/sis966/sis966_lpc.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/southbridge/sis/sis966/sis966_lpc.c (Arbeitskopie) @@ -102,7 +102,7 @@ l = (unsigned long *) ioapic_base; - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; Index: LinuxBIOSv2-array_size/src/superio/via/vt1211/vt1211.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/via/vt1211/vt1211.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/via/vt1211/vt1211.c (Arbeitskopie) @@ -212,7 +212,7 @@ printk_debug("vt1211 enabling PNP devices.\n"); pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info) / sizeof(pnp_dev_info[0]), + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } Index: LinuxBIOSv2-array_size/src/superio/winbond/w83627thf/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/winbond/w83627thf/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/winbond/w83627thf/superio.c (Arbeitskopie) @@ -101,7 +101,7 @@ static void enable_dev(device_t dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_winbond_w83627thf_ops = { Index: LinuxBIOSv2-array_size/src/superio/winbond/w83977tf/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/winbond/w83977tf/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/winbond/w83977tf/superio.c (Arbeitskopie) @@ -105,7 +105,7 @@ static void enable_dev(device_t dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_winbond_w83977tf_ops = { Index: LinuxBIOSv2-array_size/src/superio/winbond/w83627ehg/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/winbond/w83627ehg/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/winbond/w83627ehg/superio.c (Arbeitskopie) @@ -93,7 +93,7 @@ 0x48, 0x7f, 0x2a, /* Set SMBus base to 0x54 >> 1. */ }; - for(i = 0; i < sizeof(hwm_reg_values)/sizeof(hwm_reg_values[0]); i += 3) { + for(i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) { reg = hwm_reg_values[i]; value = pnp_read_index(base, reg); value &= 0xff & (~(hwm_reg_values[i + 1])); @@ -200,7 +200,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_winbond_w83627ehg_ops = { Index: LinuxBIOSv2-array_size/src/superio/winbond/w83627hf/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/winbond/w83627hf/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/winbond/w83627hf/superio.c (Arbeitskopie) @@ -83,7 +83,7 @@ }; - for(i = 0; i< sizeof(hwm_reg_values)/sizeof(hwm_reg_values[0]); i+=3 ) { + for(i = 0; i< ARRAY_SIZE(hwm_reg_values); i+=3 ) { reg = hwm_reg_values[i]; value = pnp_read_index(base, reg); value &= 0xff & hwm_reg_values[i+1]; @@ -189,7 +189,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_winbond_w83627hf_ops = { Index: LinuxBIOSv2-array_size/src/superio/winbond/w83977f/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/winbond/w83977f/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/winbond/w83977f/superio.c (Arbeitskopie) @@ -109,7 +109,7 @@ static void enable_dev(device_t dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_winbond_w83977f_ops = { Index: LinuxBIOSv2-array_size/src/superio/ite/it8712f/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/ite/it8712f/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/ite/it8712f/superio.c (Arbeitskopie) @@ -133,7 +133,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8712f_ops = { Index: LinuxBIOSv2-array_size/src/superio/ite/it8705f/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/ite/it8705f/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/ite/it8705f/superio.c (Arbeitskopie) @@ -80,7 +80,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8705f_ops = { Index: LinuxBIOSv2-array_size/src/superio/ite/it8661f/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/ite/it8661f/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/ite/it8661f/superio.c (Arbeitskopie) @@ -72,7 +72,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8661f_ops = { Index: LinuxBIOSv2-array_size/src/superio/ite/it8671f/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/ite/it8671f/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/ite/it8671f/superio.c (Arbeitskopie) @@ -77,7 +77,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8671f_ops = { Index: LinuxBIOSv2-array_size/src/superio/ite/it8716f/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/ite/it8716f/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/ite/it8716f/superio.c (Arbeitskopie) @@ -165,7 +165,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info) / sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8716f_ops = { Index: LinuxBIOSv2-array_size/src/superio/ite/it8673f/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/ite/it8673f/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/ite/it8673f/superio.c (Arbeitskopie) @@ -79,7 +79,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8673f_ops = { Index: LinuxBIOSv2-array_size/src/superio/ite/it8718f/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/ite/it8718f/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/ite/it8718f/superio.c (Arbeitskopie) @@ -81,7 +81,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8718f_ops = { Index: LinuxBIOSv2-array_size/src/superio/nsc/pc87366/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/nsc/pc87366/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/nsc/pc87366/superio.c (Arbeitskopie) @@ -67,7 +67,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc87366_ops = { Index: LinuxBIOSv2-array_size/src/superio/nsc/pc8374/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/nsc/pc8374/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/nsc/pc8374/superio.c (Arbeitskopie) @@ -64,7 +64,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc8374_ops = { Index: LinuxBIOSv2-array_size/src/superio/nsc/pc87351/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/nsc/pc87351/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/nsc/pc87351/superio.c (Arbeitskopie) @@ -71,7 +71,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc87351_ops = { Index: LinuxBIOSv2-array_size/src/superio/nsc/pc87360/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/nsc/pc87360/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/nsc/pc87360/superio.c (Arbeitskopie) @@ -67,7 +67,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc87360_ops = { Index: LinuxBIOSv2-array_size/src/superio/nsc/pc97307/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/nsc/pc97307/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/nsc/pc97307/superio.c (Arbeitskopie) @@ -79,7 +79,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc97307_ops = { Index: LinuxBIOSv2-array_size/src/superio/nsc/pc87309/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/nsc/pc87309/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/nsc/pc87309/superio.c (Arbeitskopie) @@ -73,7 +73,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info) / sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc87309_ops = { Index: LinuxBIOSv2-array_size/src/superio/nsc/pc87417/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/nsc/pc87417/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/nsc/pc87417/superio.c (Arbeitskopie) @@ -68,7 +68,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc87417_ops = { Index: LinuxBIOSv2-array_size/src/superio/nsc/pc97317/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/nsc/pc97317/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/nsc/pc97317/superio.c (Arbeitskopie) @@ -81,7 +81,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc97317_ops = { Index: LinuxBIOSv2-array_size/src/superio/nsc/pc87427/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/nsc/pc87427/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/nsc/pc87427/superio.c (Arbeitskopie) @@ -68,7 +68,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc87427_ops = { Index: LinuxBIOSv2-array_size/src/superio/smsc/lpc47m10x/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/smsc/lpc47m10x/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/smsc/lpc47m10x/superio.c (Arbeitskopie) @@ -82,7 +82,7 @@ static void enable_dev(device_t dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } Index: LinuxBIOSv2-array_size/src/superio/smsc/fdc37m60x/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/smsc/fdc37m60x/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/smsc/fdc37m60x/superio.c (Arbeitskopie) @@ -77,7 +77,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_smsc_fdc37m60x_ops = { Index: LinuxBIOSv2-array_size/src/superio/smsc/lpc47n217/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/smsc/lpc47n217/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/smsc/lpc47n217/superio.c (Arbeitskopie) @@ -86,7 +86,7 @@ static void enable_dev(device_t dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } Index: LinuxBIOSv2-array_size/src/superio/smsc/lpc47b272/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/smsc/lpc47b272/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/smsc/lpc47b272/superio.c (Arbeitskopie) @@ -84,7 +84,7 @@ static void enable_dev(device_t dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } Index: LinuxBIOSv2-array_size/src/superio/smsc/lpc47b397/superio.c =================================================================== --- LinuxBIOSv2-array_size/src/superio/smsc/lpc47b397/superio.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/superio/smsc/lpc47b397/superio.c (Arbeitskopie) @@ -207,7 +207,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_smsc_lpc47b397_ops = { Index: LinuxBIOSv2-array_size/src/cpu/amd/sc520/sc520.c =================================================================== --- LinuxBIOSv2-array_size/src/cpu/amd/sc520/sc520.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/cpu/amd/sc520/sc520.c (Arbeitskopie) @@ -151,7 +151,7 @@ // int i; int idx; #if 0 - for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) { + for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); /* these are ENDING addresses, not sizes. Index: LinuxBIOSv2-array_size/src/cpu/amd/model_10xxx/init_cpus.c =================================================================== --- LinuxBIOSv2-array_size/src/cpu/amd/model_10xxx/init_cpus.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/cpu/amd/model_10xxx/init_cpus.c (Arbeitskopie) @@ -522,7 +522,7 @@ printk_debug("setup_remote_node: %02x", node); /* copy the default resource map from node 0 */ - for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) { + for(i = 0; i < ARRAY_SIZE(pci_reg); i++) { u32 value; u16 reg; reg = pci_reg[i]; @@ -852,7 +852,7 @@ revision = mctGetLogicalCPUID(0xFF); platform = get_platform_type(); - for(i = 0; i < sizeof(fam10_msr_default)/sizeof(fam10_msr_default[0]); i++) { + for(i = 0; i < ARRAY_SIZE(fam10_msr_default); i++) { if ((fam10_msr_default[i].revision & revision) && (fam10_msr_default[i].platform & platform)) { msr = rdmsr(fam10_msr_default[i].msr); @@ -889,7 +889,7 @@ AMD_SetupPSIVID_d(platform, node); /* Set PSIVID offset which is not table driven */ - for(i = 0; i < sizeof(fam10_pci_default)/sizeof(fam10_pci_default[0]); i++) { + for(i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) { if ((fam10_pci_default[i].revision & revision) && (fam10_pci_default[i].platform & platform)) { val = pci_read_config32(NODE_PCI(node, @@ -903,7 +903,7 @@ } } - for(i = 0; i < sizeof(fam10_htphy_default)/sizeof(fam10_htphy_default[0]); i++) { + for(i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) { if ((fam10_htphy_default[i].revision & revision) && (fam10_htphy_default[i].platform & platform)) { /* HT Phy settings either apply to both sublinks or have Index: LinuxBIOSv2-array_size/src/cpu/emulation/qemu-x86/northbridge.c =================================================================== --- LinuxBIOSv2-array_size/src/cpu/emulation/qemu-x86/northbridge.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/cpu/emulation/qemu-x86/northbridge.c (Arbeitskopie) @@ -80,7 +80,7 @@ unsigned char rambits; int i, idx; - for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) { + for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); /* these are ENDING addresses, not sizes. Index: LinuxBIOSv2-array_size/src/stream/fs/vfs.c =================================================================== --- LinuxBIOSv2-array_size/src/stream/fs/vfs.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/stream/fs/vfs.c (Arbeitskopie) @@ -70,7 +70,7 @@ { int i; - for (i = 0; i < sizeof(fsys_table)/sizeof(fsys_table[0]); i++) { + for (i = 0; i < ARRAY_SIZE(fsys_table); i++) { if (fsys_table[i].mount_func()) { fsys = &fsys_table[i]; printk_info("Mounted %s\n", fsys->name); Index: LinuxBIOSv2-array_size/src/mainboard/iwill/dk8_htx/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/iwill/dk8_htx/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/iwill/dk8_htx/resourcemap.c (Arbeitskopie) @@ -258,7 +258,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/iwill/dk8_htx/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/iwill/dk8_htx/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/iwill/dk8_htx/get_bus_conf.c (Arbeitskopie) @@ -90,7 +90,7 @@ m = sysconf.mb; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/iwill/dk8s2/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/iwill/dk8s2/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/iwill/dk8s2/auto.c (Arbeitskopie) @@ -149,7 +149,7 @@ #endif memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); #if 0 dump_pci_devices(); Index: LinuxBIOSv2-array_size/src/mainboard/iwill/dk8x/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/iwill/dk8x/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/iwill/dk8x/auto.c (Arbeitskopie) @@ -148,7 +148,7 @@ #endif memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); #if 1 dump_pci_devices(); @@ -181,7 +181,7 @@ #endif }; int i; - for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) { + for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { ram_check(check_addrs[i].lo, check_addrs[i].hi); } #endif Index: LinuxBIOSv2-array_size/src/mainboard/broadcom/blast/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/broadcom/blast/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/broadcom/blast/resourcemap.c (Arbeitskopie) @@ -259,7 +259,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/broadcom/blast/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/broadcom/blast/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/broadcom/blast/get_bus_conf.c (Arbeitskopie) @@ -61,7 +61,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dai_g/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dai_g/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dai_g/auto.c (Arbeitskopie) @@ -113,7 +113,7 @@ } #endif disable_watchdogs(); - sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + sdram_initialize(ARRAY_SIZE(mch), mch); #if 1 dump_pci_device(PCI_DEV(0, 0x00, 0)); // dump_bar14(PCI_DEV(0, 0x00, 0)); Index: LinuxBIOSv2-array_size/src/mainboard/supermicro/h8dmr/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/supermicro/h8dmr/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/supermicro/h8dmr/resourcemap.c (Arbeitskopie) @@ -277,7 +277,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/supermicro/h8dmr/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/supermicro/h8dmr/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/supermicro/h8dmr/get_bus_conf.c (Arbeitskopie) @@ -81,7 +81,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dhe_g/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dhe_g/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dhe_g/auto.c (Arbeitskopie) @@ -138,7 +138,7 @@ // dump_ipmi_registers(); // mainboard_set_e7520_leds(); // memreset_setup(); - sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); #endif Index: LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dhe_g2/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dhe_g2/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dhe_g2/auto.c (Arbeitskopie) @@ -139,7 +139,7 @@ // dump_ipmi_registers(); // mainboard_set_e7520_leds(); // memreset_setup(); - sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); #endif Index: LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dhe_g2/auto.updated.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dhe_g2/auto.updated.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dhe_g2/auto.updated.c (Arbeitskopie) @@ -139,7 +139,7 @@ // dump_ipmi_registers(); // mainboard_set_e7520_leds(); // memreset_setup(); - sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); #endif Index: LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dhr_ig/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dhr_ig/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dhr_ig/auto.c (Arbeitskopie) @@ -139,7 +139,7 @@ // dump_ipmi_registers(); mainboard_set_e7520_leds(); // memreset_setup(); - sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + sdram_initialize(ARRAY_SIZE(mch), mch); #if 1 dump_pci_devices(); #endif Index: LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dhr_ig2/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dhr_ig2/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/supermicro/x6dhr_ig2/auto.c (Arbeitskopie) @@ -139,7 +139,7 @@ // dump_ipmi_registers(); mainboard_set_e7520_leds(); // memreset_setup(); - sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); #endif Index: LinuxBIOSv2-array_size/src/mainboard/a-trend/atc-6220/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/a-trend/atc-6220/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/a-trend/atc-6220/auto.c (Arbeitskopie) @@ -67,6 +67,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Index: LinuxBIOSv2-array_size/src/mainboard/gigabyte/m57sli/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/gigabyte/m57sli/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/gigabyte/m57sli/resourcemap.c (Arbeitskopie) @@ -277,7 +277,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/gigabyte/m57sli/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/gigabyte/m57sli/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/gigabyte/m57sli/get_bus_conf.c (Arbeitskopie) @@ -80,7 +80,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c (Arbeitskopie) @@ -277,7 +277,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c (Arbeitskopie) @@ -82,7 +82,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/gigabyte/ga-6bxc/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/gigabyte/ga-6bxc/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/gigabyte/ga-6bxc/auto.c (Arbeitskopie) @@ -67,6 +67,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Index: LinuxBIOSv2-array_size/src/mainboard/digitallogic/adl855pc/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/digitallogic/adl855pc/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/digitallogic/adl855pc/auto.c (Arbeitskopie) @@ -100,7 +100,7 @@ memreset_setup(); - sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } #if 0 Index: LinuxBIOSv2-array_size/src/mainboard/amd/serengeti_cheetah/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/amd/serengeti_cheetah/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/amd/serengeti_cheetah/resourcemap.c (Arbeitskopie) @@ -258,7 +258,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c (Arbeitskopie) @@ -90,7 +90,7 @@ m = sysconf.mb; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c (Arbeitskopie) @@ -275,7 +275,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c (Arbeitskopie) @@ -111,7 +111,7 @@ m->bus_type[i] = 0; } - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/biostar/m6tba/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/biostar/m6tba/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/biostar/m6tba/auto.c (Arbeitskopie) @@ -67,6 +67,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Index: LinuxBIOSv2-array_size/src/mainboard/azza/pt-6ibd/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/azza/pt-6ibd/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/azza/pt-6ibd/auto.c (Arbeitskopie) @@ -70,6 +70,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Index: LinuxBIOSv2-array_size/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c (Arbeitskopie) @@ -51,7 +51,7 @@ int i; if (device == DIMM0){ - for (i=0; i < (sizeof spd_table/sizeof spd_table[0]); i++){ + for (i=0; i < (ARRAY_SIZE(spd_table)); i++){ if (spd_table[i].address == address){ return spd_table[i].data; } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2912/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2912/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2912/resourcemap.c (Arbeitskopie) @@ -277,7 +277,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2912/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2912/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2912/get_bus_conf.c (Arbeitskopie) @@ -107,7 +107,7 @@ m = sysconf.mb; memset(m, 0, sizeof(struct mb_sysconf_t)); - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2850/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2850/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2850/auto.c (Arbeitskopie) @@ -197,6 +197,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2850/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2850/cache_as_ram_auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2850/cache_as_ram_auto.c (Arbeitskopie) @@ -206,7 +206,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); post_cache_as_ram(); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2735/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2735/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2735/auto.c (Arbeitskopie) @@ -96,7 +96,7 @@ #endif memreset_setup(); - sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } #if 0 else { Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2880/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2880/cache_as_ram_auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2880/cache_as_ram_auto.c (Arbeitskopie) @@ -205,7 +205,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); post_cache_as_ram(); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s1846/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s1846/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s1846/auto.c (Arbeitskopie) @@ -67,6 +67,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2881/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2881/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2881/resourcemap.c (Arbeitskopie) @@ -258,7 +258,7 @@ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2881/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2881/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2881/auto.c (Arbeitskopie) @@ -172,6 +172,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2881/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2881/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2881/get_bus_conf.c (Arbeitskopie) @@ -63,7 +63,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2882/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2882/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2882/auto.c (Arbeitskopie) @@ -176,6 +176,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2882/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2882/cache_as_ram_auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2882/cache_as_ram_auto.c (Arbeitskopie) @@ -208,7 +208,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); post_cache_as_ram(); Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2891/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2891/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2891/resourcemap.c (Arbeitskopie) @@ -267,7 +267,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2891/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2891/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2891/auto.c (Arbeitskopie) @@ -148,6 +148,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2891/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2891/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2891/get_bus_conf.c (Arbeitskopie) @@ -71,7 +71,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s4880/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s4880/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s4880/resourcemap.c (Arbeitskopie) @@ -258,7 +258,7 @@ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s4880/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s4880/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s4880/auto.c (Arbeitskopie) @@ -227,6 +227,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s4880/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s4880/cache_as_ram_auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s4880/cache_as_ram_auto.c (Arbeitskopie) @@ -254,7 +254,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); post_cache_as_ram(); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2892/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2892/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2892/resourcemap.c (Arbeitskopie) @@ -267,7 +267,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2892/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2892/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2892/auto.c (Arbeitskopie) @@ -149,6 +149,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2892/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2892/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2892/get_bus_conf.c (Arbeitskopie) @@ -68,7 +68,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2875/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2875/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2875/auto.c (Arbeitskopie) @@ -167,6 +167,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2875/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2875/cache_as_ram_auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2875/cache_as_ram_auto.c (Arbeitskopie) @@ -203,7 +203,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); post_cache_as_ram(); Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s4882/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s4882/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s4882/resourcemap.c (Arbeitskopie) @@ -258,7 +258,7 @@ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s4882/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s4882/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s4882/auto.c (Arbeitskopie) @@ -227,6 +227,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2885/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2885/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2885/resourcemap.c (Arbeitskopie) @@ -259,7 +259,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2885/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2885/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2885/auto.c (Arbeitskopie) @@ -178,7 +178,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2885/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2885/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2885/get_bus_conf.c (Arbeitskopie) @@ -65,7 +65,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2895/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2895/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2895/resourcemap.c (Arbeitskopie) @@ -261,7 +261,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2895/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2895/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2895/auto.c (Arbeitskopie) @@ -190,7 +190,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Index: LinuxBIOSv2-array_size/src/mainboard/tyan/s2895/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/tyan/s2895/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/tyan/s2895/get_bus_conf.c (Arbeitskopie) @@ -76,7 +76,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/via/epia-m/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/via/epia-m/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/via/epia-m/auto.c (Arbeitskopie) @@ -146,7 +146,7 @@ #endif }; int i; - for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) { + for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { ram_check(check_addrs[i].lo, check_addrs[i].hi); } #endif Index: LinuxBIOSv2-array_size/src/mainboard/via/epia/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/via/epia/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/via/epia/auto.c (Arbeitskopie) @@ -107,7 +107,7 @@ /* this is way more generic than we need. - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); */ sdram_set_registers((const struct mem_controller *) 0); sdram_set_spd_registers((const struct mem_controller *) 0); @@ -129,7 +129,7 @@ #endif }; int i; - for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) { + for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { ram_check(check_addrs[i].lo, check_addrs[i].hi); } #endif Index: LinuxBIOSv2-array_size/src/mainboard/compaq/deskpro_en_sff_p600/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/compaq/deskpro_en_sff_p600/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/compaq/deskpro_en_sff_p600/auto.c (Arbeitskopie) @@ -70,6 +70,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Index: LinuxBIOSv2-array_size/src/mainboard/dell/s1850/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/dell/s1850/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/dell/s1850/auto.c (Arbeitskopie) @@ -139,7 +139,7 @@ // dump_ipmi_registers(); mainboard_set_e7520_leds(); // memreset_setup(); - sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); #endif Index: LinuxBIOSv2-array_size/src/mainboard/msi/ms7135/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/msi/ms7135/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/msi/ms7135/get_bus_conf.c (Arbeitskopie) @@ -67,8 +67,8 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); - sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/msi/ms9282/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/msi/ms9282/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/msi/ms9282/resourcemap.c (Arbeitskopie) @@ -293,7 +293,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/msi/ms9282/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/msi/ms9282/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/msi/ms9282/get_bus_conf.c (Arbeitskopie) @@ -110,7 +110,7 @@ m = sysconf.mb; memset(m, 0, sizeof(struct mb_sysconf_t)); - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/msi/ms6178/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/msi/ms6178/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/msi/ms6178/auto.c (Arbeitskopie) @@ -65,6 +65,6 @@ console_init(); report_bist_failure(bist); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Index: LinuxBIOSv2-array_size/src/mainboard/msi/ms9185/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/msi/ms9185/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/msi/ms9185/resourcemap.c (Arbeitskopie) @@ -285,7 +285,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/msi/ms9185/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/msi/ms9185/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/msi/ms9185/get_bus_conf.c (Arbeitskopie) @@ -82,7 +82,7 @@ m = sysconf.mb; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; Index: LinuxBIOSv2-array_size/src/mainboard/msi/ms7260/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/msi/ms7260/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/msi/ms7260/resourcemap.c (Arbeitskopie) @@ -278,6 +278,6 @@ }; - int max = sizeof(register_values) / sizeof(register_values[0]); + int max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/msi/ms7260/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/msi/ms7260/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/msi/ms7260/get_bus_conf.c (Arbeitskopie) @@ -81,7 +81,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/arima/hdama/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/arima/hdama/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/arima/hdama/auto.c (Arbeitskopie) @@ -157,11 +157,11 @@ #endif enable_smbus(); #if 0 - dump_spd_registers(sizeof(cpu)/sizeof(cpu[0]), cpu); + dump_spd_registers(ARRAY_SIZE(cpu), cpu); #endif memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); #if 0 dump_pci_devices(); Index: LinuxBIOSv2-array_size/src/mainboard/arima/hdama/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/arima/hdama/cache_as_ram_auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/arima/hdama/cache_as_ram_auto.c (Arbeitskopie) @@ -215,7 +215,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); post_cache_as_ram(); Index: LinuxBIOSv2-array_size/src/mainboard/sunw/ultra40/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/sunw/ultra40/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/sunw/ultra40/resourcemap.c (Arbeitskopie) @@ -260,7 +260,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/sunw/ultra40/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/sunw/ultra40/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/sunw/ultra40/auto.c (Arbeitskopie) @@ -191,7 +191,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Index: LinuxBIOSv2-array_size/src/mainboard/sunw/ultra40/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/sunw/ultra40/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/sunw/ultra40/get_bus_conf.c (Arbeitskopie) @@ -75,7 +75,7 @@ get_bus_conf_done = 1; - hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]); + hc_possible_num = ARRAY_SIZE(pci1234); get_sblk_pci1234(); Index: LinuxBIOSv2-array_size/src/mainboard/eaglelion/5bcm/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/eaglelion/5bcm/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/eaglelion/5bcm/auto.c (Arbeitskopie) @@ -48,7 +48,7 @@ #endif }; int i; - for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) { + for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { ram_check(check_addrs[i].lo, check_addrs[i].hi); } #endif Index: LinuxBIOSv2-array_size/src/mainboard/newisys/khepri/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/newisys/khepri/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/newisys/khepri/resourcemap.c (Arbeitskopie) @@ -265,7 +265,7 @@ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/newisys/khepri/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/newisys/khepri/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/newisys/khepri/auto.c (Arbeitskopie) @@ -138,7 +138,7 @@ dump_spd_registers(&cpu[0]); #endif memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); #if 0 dump_pci_devices(); Index: LinuxBIOSv2-array_size/src/mainboard/ibm/e326/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/ibm/e326/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/ibm/e326/resourcemap.c (Arbeitskopie) @@ -266,6 +266,6 @@ PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/ibm/e326/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/ibm/e326/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/ibm/e326/auto.c (Arbeitskopie) @@ -163,7 +163,7 @@ #endif memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); #if 0 dump_pci_devices(); Index: LinuxBIOSv2-array_size/src/mainboard/ibm/e326/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/ibm/e326/cache_as_ram_auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/ibm/e326/cache_as_ram_auto.c (Arbeitskopie) @@ -211,7 +211,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); post_cache_as_ram(); Index: LinuxBIOSv2-array_size/src/mainboard/ibm/e325/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/ibm/e325/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/ibm/e325/resourcemap.c (Arbeitskopie) @@ -266,6 +266,6 @@ PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/ibm/e325/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/ibm/e325/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/ibm/e325/auto.c (Arbeitskopie) @@ -163,7 +163,7 @@ #endif memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); #if 0 dump_pci_devices(); Index: LinuxBIOSv2-array_size/src/mainboard/ibm/e325/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/ibm/e325/cache_as_ram_auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/ibm/e325/cache_as_ram_auto.c (Arbeitskopie) @@ -211,7 +211,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); post_cache_as_ram(); Index: LinuxBIOSv2-array_size/src/mainboard/nvidia/l1_2pvv/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/nvidia/l1_2pvv/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/nvidia/l1_2pvv/resourcemap.c (Arbeitskopie) @@ -277,7 +277,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c (Arbeitskopie) @@ -108,7 +108,7 @@ m = sysconf.mb; memset(m, 0, sizeof(struct mb_sysconf_t)); - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; Index: LinuxBIOSv2-array_size/src/mainboard/intel/xe7501devkit/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/intel/xe7501devkit/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/intel/xe7501devkit/auto.c (Arbeitskopie) @@ -83,7 +83,7 @@ // dump_smbus_registers(); // memreset_setup(); No-op for this chipset - sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } // NOTE: ROMCC dies with an internal compiler error Index: LinuxBIOSv2-array_size/src/mainboard/intel/jarrell/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/intel/jarrell/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/intel/jarrell/auto.c (Arbeitskopie) @@ -120,7 +120,7 @@ power_down_reset_check(); // dump_ipmi_registers(); mainboard_set_e7520_leds(); - sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + sdram_initialize(ARRAY_SIZE(mch), mch); ich5_watchdog_on(); #if 0 dump_pci_devices(); Index: LinuxBIOSv2-array_size/src/mainboard/asus/p2b/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/asus/p2b/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/asus/p2b/auto.c (Arbeitskopie) @@ -67,6 +67,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Index: LinuxBIOSv2-array_size/src/mainboard/asus/p2b-f/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/asus/p2b-f/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/asus/p2b-f/auto.c (Arbeitskopie) @@ -70,6 +70,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Index: LinuxBIOSv2-array_size/src/mainboard/asus/p3b-f/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/asus/p3b-f/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/asus/p3b-f/auto.c (Arbeitskopie) @@ -70,6 +70,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Index: LinuxBIOSv2-array_size/src/mainboard/asus/mew-vm/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/asus/mew-vm/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/asus/mew-vm/auto.c (Arbeitskopie) @@ -77,7 +77,7 @@ /* dump_spd_registers(&memctrl[0]); */ /* sdram_initialize() runs out of registers. */ - /* sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); */ + /* sdram_initialize(ARRAY_SIZE(memctrl), memctrl); */ sdram_set_registers(memctrl); sdram_set_spd_registers(memctrl); Index: LinuxBIOSv2-array_size/src/mainboard/asus/a8n_e/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/asus/a8n_e/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/asus/a8n_e/get_bus_conf.c (Arbeitskopie) @@ -66,8 +66,8 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); - sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Index: LinuxBIOSv2-array_size/src/mainboard/agami/aruma/auto.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/agami/aruma/auto.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/agami/aruma/auto.c (Arbeitskopie) @@ -171,7 +171,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); #if 0 /* Check the first 1M */ Index: LinuxBIOSv2-array_size/src/mainboard/agami/aruma/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/agami/aruma/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/agami/aruma/resourcemap.c (Arbeitskopie) @@ -265,7 +265,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/mainboard/agami/aruma/get_bus_conf.c =================================================================== --- LinuxBIOSv2-array_size/src/mainboard/agami/aruma/get_bus_conf.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/mainboard/agami/aruma/get_bus_conf.c (Arbeitskopie) @@ -62,7 +62,7 @@ get_bus_conf_done = 1; - hc_possible_num = sizeof(pci1234) / sizeof(pci1234[0]); + hc_possible_num = ARRAY_SIZE(pci1234); get_sblk_pci1234(); Index: LinuxBIOSv2-array_size/src/northbridge/via/vt8601/northbridge.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/via/vt8601/northbridge.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/via/vt8601/northbridge.c (Arbeitskopie) @@ -115,7 +115,7 @@ unsigned char rambits; int i, idx; - for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) { + for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); /* these are ENDING addresses, not sizes. Index: LinuxBIOSv2-array_size/src/northbridge/via/vt8623/northbridge.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/via/vt8623/northbridge.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/via/vt8623/northbridge.c (Arbeitskopie) @@ -287,7 +287,7 @@ unsigned char rambits; int i, idx; - for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) { + for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); /* these are ENDING addresses, not sizes. Index: LinuxBIOSv2-array_size/src/northbridge/amd/gx2/chipsetinit.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/amd/gx2/chipsetinit.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/amd/gx2/chipsetinit.c (Arbeitskopie) @@ -177,7 +177,7 @@ { FLASH_TYPE_NONE, 0, 0 }, /* CS3, or Flash Device 3 */ }; -#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0])) +#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable)) uint32_t FlashPort[] = { MDD_LBAR_FLSH0, Index: LinuxBIOSv2-array_size/src/northbridge/amd/amdk8/coherent_ht.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/amd/amdk8/coherent_ht.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/amd/amdk8/coherent_ht.c (Arbeitskopie) @@ -510,7 +510,7 @@ print_spew("setup_remote_node: "); /* copy the default resource map from node 0 */ - for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) { + for(i = 0; i < ARRAY_SIZE(pci_reg); i++) { uint32_t value; uint8_t reg; reg = pci_reg[i]; @@ -802,7 +802,7 @@ }; #endif - setup_row_indirect_group(conn4_1, sizeof(conn4_1)/sizeof(conn4_1[0])); + setup_row_indirect_group(conn4_1, ARRAY_SIZE(conn4_1)); setup_temp_row(0,2); verify_connection(7); @@ -893,7 +893,7 @@ 3,0,1,1, }; #endif - setup_remote_row_indirect_group(conn4_3, sizeof(conn4_3)/sizeof(conn4_3[0])); + setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3)); /* ready to enable RT for Node 3 */ rename_temp_node(3); @@ -909,7 +909,7 @@ 2,1,0,1, }; #endif - setup_row_indirect_group(conn4_2, sizeof(conn4_2)/sizeof(conn4_2[0])); + setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2)); #if 0 /*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */ @@ -974,7 +974,7 @@ #endif }; - setup_row_indirect_group(conn6_1, sizeof(conn6_1)/sizeof(conn6_1[0])); + setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1)); for(byte=0; byte<4; byte+=2) { setup_temp_row(byte,byte+2); @@ -998,7 +998,7 @@ #endif }; - setup_remote_row_indirect_group(conn6_2, sizeof(conn6_2)/sizeof(conn6_2[0])); + setup_remote_row_indirect_group(conn6_2, ARRAY_SIZE(conn6_2)); rename_temp_node(4); enable_routing(4); @@ -1084,7 +1084,7 @@ #endif }; - setup_remote_row_indirect_group(conn6_3, sizeof(conn6_3)/sizeof(conn6_3[0])); + setup_remote_row_indirect_group(conn6_3, ARRAY_SIZE(conn6_3)); /* ready to enable RT for 5 */ rename_temp_node(5); @@ -1110,7 +1110,7 @@ #endif }; - setup_row_indirect_group(conn6_4, sizeof(conn6_4)/sizeof(conn6_4[0])); + setup_row_indirect_group(conn6_4, ARRAY_SIZE(conn6_4)); #if 0 /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5) @@ -1202,7 +1202,7 @@ #endif }; - setup_row_indirect_group(conn8_1,sizeof(conn8_1)/sizeof(conn8_1[0])); + setup_row_indirect_group(conn8_1,ARRAY_SIZE(conn8_1)); for(byte=0; byte<6; byte+=2) { setup_temp_row(byte,byte+2); @@ -1225,7 +1225,7 @@ #endif }; - setup_remote_row_indirect_group(conn8_2, sizeof(conn8_2)/sizeof(conn8_2[0])); + setup_remote_row_indirect_group(conn8_2, ARRAY_SIZE(conn8_2)); #if CROSS_BAR_47_56 //init 5, 6 here @@ -1414,7 +1414,7 @@ #endif }; - setup_row_indirect_group(conn8_3, sizeof(conn8_3)/sizeof(conn8_3[0])); + setup_row_indirect_group(conn8_3, ARRAY_SIZE(conn8_3)); #if CROSS_BAR_47_56 /* for 47, 56, 57, 75, 46, 64 we need to substract another link to @@ -1455,7 +1455,7 @@ 7, 3, 6, }; - opt_broadcast_rt_group(conn8_4, sizeof(conn8_4)/sizeof(conn8_4[0])); + opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4)); static const u8 conn8_5[] = { 2, 7, 0, @@ -1463,7 +1463,7 @@ 3, 6, 1, }; - opt_broadcast_rt_plus_group(conn8_5, sizeof(conn8_5)/sizeof(conn8_5[0])); + opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5)); #endif @@ -1770,7 +1770,7 @@ 1,3, 2,3, }; - needs_reset |= optimize_connection_group(opt_conn4, sizeof(opt_conn4)/sizeof(opt_conn4[0])); + needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4)); } #endif @@ -1783,7 +1783,7 @@ 4, 5, #endif }; - needs_reset |= optimize_connection_group(opt_conn6, sizeof(opt_conn6)/sizeof(opt_conn6[0])); + needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6)); } #endif @@ -1798,7 +1798,7 @@ 5, 7, 6, 7, }; - needs_reset |= optimize_connection_group(opt_conn8, sizeof(opt_conn8)/sizeof(opt_conn8[0])); + needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8)); } #endif Index: LinuxBIOSv2-array_size/src/northbridge/amd/amdk8/raminit_test.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/amd/amdk8/raminit_test.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/amd/amdk8/raminit_test.c (Arbeitskopie) @@ -341,7 +341,7 @@ }; console_init(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Index: LinuxBIOSv2-array_size/src/northbridge/amd/amdk8/raminit.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/amd/amdk8/raminit.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/amd/amdk8/raminit.c (Arbeitskopie) @@ -555,7 +555,7 @@ print_spew("setting up CPU"); print_spew_hex8(ctrl->node_id); print_spew(" northbridge registers\r\n"); - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); for(i = 0; i < max; i += 3) { device_t dev; unsigned where; @@ -1303,7 +1303,7 @@ } device0 = ctrl->channel0[i]; device1 = ctrl->channel1[i]; - for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) { + for(j = 0; j < ARRAY_SIZE(addresses); j++) { unsigned addr; addr = addresses[j]; value0 = spd_read_byte(device0, addr); Index: LinuxBIOSv2-array_size/src/northbridge/amd/amdk8/raminit_f.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/amd/amdk8/raminit_f.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/amd/amdk8/raminit_f.c (Arbeitskopie) @@ -643,7 +643,7 @@ print_spew("setting up CPU"); print_spew_hex8(ctrl->node_id); print_spew(" northbridge registers\r\n"); - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); for(i = 0; i < max; i += 3) { device_t dev; unsigned where; @@ -1356,7 +1356,7 @@ } device0 = ctrl->channel0[i]; device1 = ctrl->channel1[i]; - for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) { + for(j = 0; j < ARRAY_SIZE(addresses); j++) { unsigned addr; addr = addresses[j]; value0 = spd_read_byte(device0, addr); Index: LinuxBIOSv2-array_size/src/northbridge/amd/amdk8/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/amd/amdk8/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/amd/amdk8/resourcemap.c (Arbeitskopie) @@ -253,6 +253,6 @@ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/northbridge/amd/amdfam10/resourcemap.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/amd/amdfam10/resourcemap.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/amd/amdfam10/resourcemap.c (Arbeitskopie) @@ -281,7 +281,7 @@ }; u32 max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Index: LinuxBIOSv2-array_size/src/northbridge/intel/e7501/raminit.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/intel/e7501/raminit.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/intel/e7501/raminit.c (Arbeitskopie) @@ -1631,7 +1631,7 @@ static void ram_set_d0f0_regs(const struct mem_controller *ctrl) { int i; - int num_values = sizeof(constant_register_values)/sizeof(constant_register_values[0]); + int num_values = ARRAY_SIZE(constant_register_values); ASSERT((num_values % 3) == 0); // Bad table? Index: LinuxBIOSv2-array_size/src/northbridge/intel/e7520/raminit_test.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/intel/e7520/raminit_test.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/intel/e7520/raminit_test.c (Arbeitskopie) @@ -341,7 +341,7 @@ }; console_init(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Index: LinuxBIOSv2-array_size/src/northbridge/intel/e7520/raminit.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/intel/e7520/raminit.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/intel/e7520/raminit.c (Arbeitskopie) @@ -42,7 +42,7 @@ int i; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); for(i = 0; i < max; i += 3) { device_t dev; unsigned where; Index: LinuxBIOSv2-array_size/src/northbridge/intel/e7525/raminit_test.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/intel/e7525/raminit_test.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/intel/e7525/raminit_test.c (Arbeitskopie) @@ -313,7 +313,7 @@ }; console_init(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } #endif Index: LinuxBIOSv2-array_size/src/northbridge/intel/e7525/raminit.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/intel/e7525/raminit.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/intel/e7525/raminit.c (Arbeitskopie) @@ -42,7 +42,7 @@ int i; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); for(i = 0; i < max; i += 3) { device_t dev; unsigned where; Index: LinuxBIOSv2-array_size/src/northbridge/intel/i855pm/raminit.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/intel/i855pm/raminit.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/intel/i855pm/raminit.c (Arbeitskopie) @@ -384,7 +384,7 @@ #endif int i; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); for(i = 0; i < max; i += 3) { uint32_t reg; #if DEBUG_RAM_CONFIG >=2 Index: LinuxBIOSv2-array_size/src/northbridge/intel/i440bx/raminit.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/intel/i440bx/raminit.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/intel/i440bx/raminit.c (Arbeitskopie) @@ -430,7 +430,7 @@ PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n"); DUMPNORTH(); - max = sizeof(register_values) / sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); /* Set registers as specified in the register_values[] array. */ for (i = 0; i < max; i += 3) { Index: LinuxBIOSv2-array_size/src/northbridge/intel/i3100/raminit.c =================================================================== --- LinuxBIOSv2-array_size/src/northbridge/intel/i3100/raminit.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/northbridge/intel/i3100/raminit.c (Arbeitskopie) @@ -65,7 +65,7 @@ int i; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); for(i = 0; i < max; i += 3) { device_t dev; u32 where; Index: LinuxBIOSv2-array_size/src/arch/ppc/boot/coreboot_table.c =================================================================== --- LinuxBIOSv2-array_size/src/arch/ppc/boot/coreboot_table.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/arch/ppc/boot/coreboot_table.c (Arbeitskopie) @@ -116,7 +116,7 @@ { LB_TAG_ASSEMBLER, coreboot_assembler, }, }; unsigned int i; - for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) { + for(i = 0; i < ARRAY_SIZE(strings); i++) { struct lb_string *rec; size_t len; rec = (struct lb_string *)lb_new_record(header); Index: LinuxBIOSv2-array_size/src/arch/i386/smp/ioapic.c =================================================================== --- LinuxBIOSv2-array_size/src/arch/i386/smp/ioapic.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/arch/i386/smp/ioapic.c (Arbeitskopie) @@ -67,7 +67,7 @@ l[0] = 0x03; l[4] = 1; #endif /* i786 */ - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; Index: LinuxBIOSv2-array_size/src/arch/i386/boot/coreboot_table.c =================================================================== --- LinuxBIOSv2-array_size/src/arch/i386/boot/coreboot_table.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/arch/i386/boot/coreboot_table.c (Arbeitskopie) @@ -184,7 +184,7 @@ { LB_TAG_ASSEMBLER, coreboot_assembler, }, }; unsigned int i; - for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) { + for(i = 0; i < ARRAY_SIZE(strings); i++) { struct lb_string *rec; size_t len; rec = (struct lb_string *)lb_new_record(header); Index: LinuxBIOSv2-array_size/src/arch/i386/boot/acpi.c =================================================================== --- LinuxBIOSv2-array_size/src/arch/i386/boot/acpi.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/arch/i386/boot/acpi.c (Arbeitskopie) @@ -44,7 +44,7 @@ { int i; - int entries_num = sizeof(rsdt->entry)/sizeof(rsdt->entry[0]); + int entries_num = ARRAY_SIZE(rsdt->entry); for (i=0; i<entries_num; i++) { if(rsdt->entry[i]==0) { Index: LinuxBIOSv2-array_size/src/arch/i386/lib/exception.c =================================================================== --- LinuxBIOSv2-array_size/src/arch/i386/lib/exception.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/arch/i386/lib/exception.c (Arbeitskopie) @@ -377,7 +377,7 @@ gdb_stub_registers[CS] = info->cs; gdb_stub_registers[PS] = info->eflags; signo = GDB_UNKNOWN; - if (info->vector < sizeof(exception_to_signal)/sizeof(exception_to_signal[0])) { + if (info->vector < ARRAY_SIZE(exception_to_signal)) { signo = exception_to_signal[info->vector]; } Index: LinuxBIOSv2-array_size/src/arch/i386/lib/cpu.c =================================================================== --- LinuxBIOSv2-array_size/src/arch/i386/lib/cpu.c (Revision 3513) +++ LinuxBIOSv2-array_size/src/arch/i386/lib/cpu.c (Arbeitskopie) @@ -123,7 +123,7 @@ { const char *name; name = "<invalid cpu vendor>"; - if ((vendor < (sizeof(x86_vendor_name)/sizeof(x86_vendor_name[0]))) && + if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && (x86_vendor_name[vendor] != 0)) { name = x86_vendor_name[vendor]; @@ -185,7 +185,7 @@ } } cpu->vendor = X86_VENDOR_UNKNOWN; - for(i = 0; i < sizeof(x86_vendors)/sizeof(x86_vendors[0]); i++) { + for(i = 0; i < ARRAY_SIZE(x86_vendors); i++) { if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { cpu->vendor = x86_vendors[i].vendor; break; -- http://www.hailfinger.org/

3 4

r3624 - in trunk/coreboot-v2/src: arch/i386/boot arch/i386/lib arch/i386/smp arch/ppc/boot cpu/amd/model_10xxx cpu/amd/sc520 cpu/emulation/qemu-x86 drivers/ati/ragexl mainboard/a-trend/atc-6220 mainboard/agami/aruma mainboard/amd/dbm690t mainboard/amd/serengeti_cheetah mainboard/amd/serengeti_cheetah_fam10 mainboard/arima/hdama mainboard/artecgroup/dbe61 mainboard/asus/a8n_e mainboard/asus/mew-vm mainboard/asus/p2b mainboard/asus/p2b-f mainboard/asus/p3b-f mainboard/azza/pt-6ibd mainboard/biostar
by svn＠coreboot.org Oct. 1, 2008

Oct. 1, 2008

Author: hailfinger Date: 2008-10-01 14:52:52 +0200 (Wed, 01 Oct 2008) New Revision: 3624 Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c trunk/coreboot-v2/src/arch/i386/lib/cpu.c trunk/coreboot-v2/src/arch/i386/lib/exception.c trunk/coreboot-v2/src/arch/i386/smp/ioapic.c trunk/coreboot-v2/src/arch/ppc/boot/coreboot_table.c trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c trunk/coreboot-v2/src/drivers/ati/ragexl/xlinit.c trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c trunk/coreboot-v2/src/mainboard/agami/aruma/auto.c trunk/coreboot-v2/src/mainboard/agami/aruma/get_bus_conf.c trunk/coreboot-v2/src/mainboard/agami/aruma/resourcemap.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/resourcemap.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/resourcemap.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c trunk/coreboot-v2/src/mainboard/arima/hdama/auto.c trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c trunk/coreboot-v2/src/mainboard/broadcom/blast/get_bus_conf.c trunk/coreboot-v2/src/mainboard/broadcom/blast/resourcemap.c trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/auto.c trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/fanctl.c trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/get_bus_conf.c trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/resourcemap.c trunk/coreboot-v2/src/mainboard/ibm/e325/auto.c trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/ibm/e325/resourcemap.c trunk/coreboot-v2/src/mainboard/ibm/e326/auto.c trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/ibm/e326/resourcemap.c trunk/coreboot-v2/src/mainboard/intel/jarrell/auto.c trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/auto.c trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/get_bus_conf.c trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/resourcemap.c trunk/coreboot-v2/src/mainboard/iwill/dk8s2/auto.c trunk/coreboot-v2/src/mainboard/iwill/dk8x/auto.c trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c trunk/coreboot-v2/src/mainboard/msi/ms7135/get_bus_conf.c trunk/coreboot-v2/src/mainboard/msi/ms7260/get_bus_conf.c trunk/coreboot-v2/src/mainboard/msi/ms7260/resourcemap.c trunk/coreboot-v2/src/mainboard/msi/ms9185/get_bus_conf.c trunk/coreboot-v2/src/mainboard/msi/ms9185/resourcemap.c trunk/coreboot-v2/src/mainboard/msi/ms9282/get_bus_conf.c trunk/coreboot-v2/src/mainboard/msi/ms9282/resourcemap.c trunk/coreboot-v2/src/mainboard/newisys/khepri/auto.c trunk/coreboot-v2/src/mainboard/newisys/khepri/resourcemap.c trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/resourcemap.c trunk/coreboot-v2/src/mainboard/sunw/ultra40/auto.c trunk/coreboot-v2/src/mainboard/sunw/ultra40/get_bus_conf.c trunk/coreboot-v2/src/mainboard/sunw/ultra40/resourcemap.c trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/get_bus_conf.c trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/resourcemap.c trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/auto.c trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/auto.c trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.c trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.updated.c trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/auto.c trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/auto.c trunk/coreboot-v2/src/mainboard/tyan/s1846/auto.c trunk/coreboot-v2/src/mainboard/tyan/s2735/auto.c trunk/coreboot-v2/src/mainboard/tyan/s2850/auto.c trunk/coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2875/auto.c trunk/coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2881/auto.c trunk/coreboot-v2/src/mainboard/tyan/s2881/get_bus_conf.c trunk/coreboot-v2/src/mainboard/tyan/s2881/resourcemap.c trunk/coreboot-v2/src/mainboard/tyan/s2882/auto.c trunk/coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2885/auto.c trunk/coreboot-v2/src/mainboard/tyan/s2885/get_bus_conf.c trunk/coreboot-v2/src/mainboard/tyan/s2885/resourcemap.c trunk/coreboot-v2/src/mainboard/tyan/s2891/auto.c trunk/coreboot-v2/src/mainboard/tyan/s2891/get_bus_conf.c trunk/coreboot-v2/src/mainboard/tyan/s2891/resourcemap.c trunk/coreboot-v2/src/mainboard/tyan/s2892/auto.c trunk/coreboot-v2/src/mainboard/tyan/s2892/get_bus_conf.c trunk/coreboot-v2/src/mainboard/tyan/s2892/resourcemap.c trunk/coreboot-v2/src/mainboard/tyan/s2895/auto.c trunk/coreboot-v2/src/mainboard/tyan/s2895/get_bus_conf.c trunk/coreboot-v2/src/mainboard/tyan/s2895/resourcemap.c trunk/coreboot-v2/src/mainboard/tyan/s2912/get_bus_conf.c trunk/coreboot-v2/src/mainboard/tyan/s2912/resourcemap.c trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/get_bus_conf.c trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/resourcemap.c trunk/coreboot-v2/src/mainboard/tyan/s4880/auto.c trunk/coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s4880/resourcemap.c trunk/coreboot-v2/src/mainboard/tyan/s4882/auto.c trunk/coreboot-v2/src/mainboard/tyan/s4882/resourcemap.c trunk/coreboot-v2/src/mainboard/via/epia-m/auto.c trunk/coreboot-v2/src/mainboard/via/epia/auto.c trunk/coreboot-v2/src/northbridge/amd/amdfam10/resourcemap.c trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c trunk/coreboot-v2/src/northbridge/amd/amdk8/resourcemap.c trunk/coreboot-v2/src/northbridge/amd/gx2/chipsetinit.c trunk/coreboot-v2/src/northbridge/intel/e7501/raminit.c trunk/coreboot-v2/src/northbridge/intel/e7520/raminit.c trunk/coreboot-v2/src/northbridge/intel/e7520/raminit_test.c trunk/coreboot-v2/src/northbridge/intel/e7525/raminit.c trunk/coreboot-v2/src/northbridge/intel/e7525/raminit_test.c trunk/coreboot-v2/src/northbridge/intel/i3100/raminit.c trunk/coreboot-v2/src/northbridge/intel/i440bx/raminit.c trunk/coreboot-v2/src/northbridge/intel/i855pm/raminit.c trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c trunk/coreboot-v2/src/stream/fs/vfs.c trunk/coreboot-v2/src/superio/ite/it8661f/superio.c trunk/coreboot-v2/src/superio/ite/it8671f/superio.c trunk/coreboot-v2/src/superio/ite/it8673f/superio.c trunk/coreboot-v2/src/superio/ite/it8705f/superio.c trunk/coreboot-v2/src/superio/ite/it8712f/superio.c trunk/coreboot-v2/src/superio/ite/it8716f/superio.c trunk/coreboot-v2/src/superio/ite/it8718f/superio.c trunk/coreboot-v2/src/superio/nsc/pc8374/superio.c trunk/coreboot-v2/src/superio/nsc/pc87309/superio.c trunk/coreboot-v2/src/superio/nsc/pc87351/superio.c trunk/coreboot-v2/src/superio/nsc/pc87360/superio.c trunk/coreboot-v2/src/superio/nsc/pc87366/superio.c trunk/coreboot-v2/src/superio/nsc/pc87417/superio.c trunk/coreboot-v2/src/superio/nsc/pc87427/superio.c trunk/coreboot-v2/src/superio/nsc/pc97307/superio.c trunk/coreboot-v2/src/superio/nsc/pc97317/superio.c trunk/coreboot-v2/src/superio/smsc/fdc37m60x/superio.c trunk/coreboot-v2/src/superio/smsc/lpc47b272/superio.c trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c trunk/coreboot-v2/src/superio/smsc/lpc47m10x/superio.c trunk/coreboot-v2/src/superio/smsc/lpc47n217/superio.c trunk/coreboot-v2/src/superio/via/vt1211/vt1211.c trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c trunk/coreboot-v2/src/superio/winbond/w83627thf/superio.c trunk/coreboot-v2/src/superio/winbond/w83977f/superio.c trunk/coreboot-v2/src/superio/winbond/w83977tf/superio.c Log: The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of code to use it. That makes the code more readable and also less error-prone. Abuild tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -44,7 +44,7 @@ { int i; - int entries_num = sizeof(rsdt->entry)/sizeof(rsdt->entry[0]); + int entries_num = ARRAY_SIZE(rsdt->entry); for (i=0; i<entries_num; i++) { if(rsdt->entry[i]==0) { Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -184,7 +184,7 @@ { LB_TAG_ASSEMBLER, coreboot_assembler, }, }; unsigned int i; - for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) { + for(i = 0; i < ARRAY_SIZE(strings); i++) { struct lb_string *rec; size_t len; rec = (struct lb_string *)lb_new_record(header); Modified: trunk/coreboot-v2/src/arch/i386/lib/cpu.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/cpu.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/arch/i386/lib/cpu.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -123,7 +123,7 @@ { const char *name; name = "<invalid cpu vendor>"; - if ((vendor < (sizeof(x86_vendor_name)/sizeof(x86_vendor_name[0]))) && + if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && (x86_vendor_name[vendor] != 0)) { name = x86_vendor_name[vendor]; @@ -185,7 +185,7 @@ } } cpu->vendor = X86_VENDOR_UNKNOWN; - for(i = 0; i < sizeof(x86_vendors)/sizeof(x86_vendors[0]); i++) { + for(i = 0; i < ARRAY_SIZE(x86_vendors); i++) { if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { cpu->vendor = x86_vendors[i].vendor; break; Modified: trunk/coreboot-v2/src/arch/i386/lib/exception.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/exception.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/arch/i386/lib/exception.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -377,7 +377,7 @@ gdb_stub_registers[CS] = info->cs; gdb_stub_registers[PS] = info->eflags; signo = GDB_UNKNOWN; - if (info->vector < sizeof(exception_to_signal)/sizeof(exception_to_signal[0])) { + if (info->vector < ARRAY_SIZE(exception_to_signal)) { signo = exception_to_signal[info->vector]; } Modified: trunk/coreboot-v2/src/arch/i386/smp/ioapic.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/smp/ioapic.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/arch/i386/smp/ioapic.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -67,7 +67,7 @@ l[0] = 0x03; l[4] = 1; #endif /* i786 */ - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; Modified: trunk/coreboot-v2/src/arch/ppc/boot/coreboot_table.c =================================================================== --- trunk/coreboot-v2/src/arch/ppc/boot/coreboot_table.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/arch/ppc/boot/coreboot_table.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -116,7 +116,7 @@ { LB_TAG_ASSEMBLER, coreboot_assembler, }, }; unsigned int i; - for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) { + for(i = 0; i < ARRAY_SIZE(strings); i++) { struct lb_string *rec; size_t len; rec = (struct lb_string *)lb_new_record(header); Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -522,7 +522,7 @@ printk_debug("setup_remote_node: %02x", node); /* copy the default resource map from node 0 */ - for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) { + for(i = 0; i < ARRAY_SIZE(pci_reg); i++) { u32 value; u16 reg; reg = pci_reg[i]; @@ -852,7 +852,7 @@ revision = mctGetLogicalCPUID(0xFF); platform = get_platform_type(); - for(i = 0; i < sizeof(fam10_msr_default)/sizeof(fam10_msr_default[0]); i++) { + for(i = 0; i < ARRAY_SIZE(fam10_msr_default); i++) { if ((fam10_msr_default[i].revision & revision) && (fam10_msr_default[i].platform & platform)) { msr = rdmsr(fam10_msr_default[i].msr); @@ -889,7 +889,7 @@ AMD_SetupPSIVID_d(platform, node); /* Set PSIVID offset which is not table driven */ - for(i = 0; i < sizeof(fam10_pci_default)/sizeof(fam10_pci_default[0]); i++) { + for(i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) { if ((fam10_pci_default[i].revision & revision) && (fam10_pci_default[i].platform & platform)) { val = pci_read_config32(NODE_PCI(node, @@ -903,7 +903,7 @@ } } - for(i = 0; i < sizeof(fam10_htphy_default)/sizeof(fam10_htphy_default[0]); i++) { + for(i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) { if ((fam10_htphy_default[i].revision & revision) && (fam10_htphy_default[i].platform & platform)) { /* HT Phy settings either apply to both sublinks or have Modified: trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -151,7 +151,7 @@ // int i; int idx; #if 0 - for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) { + for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); /* these are ENDING addresses, not sizes. Modified: trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c =================================================================== --- trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -80,7 +80,7 @@ unsigned char rambits; int i, idx; - for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) { + for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); /* these are ENDING addresses, not sizes. Modified: trunk/coreboot-v2/src/drivers/ati/ragexl/xlinit.c =================================================================== --- trunk/coreboot-v2/src/drivers/ati/ragexl/xlinit.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/drivers/ati/ragexl/xlinit.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -281,7 +281,7 @@ aty_st_le32(0xEC, 0x00000000, info); aty_st_le32(0xFC, 0x00000000, info); - for (i=0; i<sizeof(lcd_tbl)/sizeof(lcd_tbl_t); i++) { + for (i=0; i<ARRAY_SIZE(lcd_tbl); i++) { aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, info); } @@ -547,7 +547,7 @@ chip_id = aty_ld_le32(CONFIG_CHIP_ID, info); type = chip_id & CFG_CHIP_TYPE; rev = (chip_id & CFG_CHIP_REV)>>24; - for (j = 0; j < (sizeof(aty_chips)/sizeof(*aty_chips)); j++) + for (j = 0; j < ARRAY_SIZE(aty_chips); j++) if (type == aty_chips[j].chip_type && (rev & aty_chips[j].rev_mask) == aty_chips[j].rev_val) { chipname = aty_chips[j].name; Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> +#include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -67,6 +68,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Modified: trunk/coreboot-v2/src/mainboard/agami/aruma/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/agami/aruma/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/agami/aruma/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -6,6 +6,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -171,7 +172,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); #if 0 /* Check the first 1M */ Modified: trunk/coreboot-v2/src/mainboard/agami/aruma/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/agami/aruma/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/agami/aruma/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -3,6 +3,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> +#include <stdlib.h> #if CONFIG_LOGICAL_CPUS==1 #include <cpu/amd/dualcore.h> #endif @@ -62,7 +63,7 @@ get_bus_conf_done = 1; - hc_possible_num = sizeof(pci1234) / sizeof(pci1234[0]); + hc_possible_num = ARRAY_SIZE(pci1234); get_sblk_pci1234(); Modified: trunk/coreboot-v2/src/mainboard/agami/aruma/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/agami/aruma/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/agami/aruma/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -265,7 +265,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -22,6 +22,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> +#include <stdlib.h> #if CONFIG_LOGICAL_CPUS==1 #include <cpu/amd/dualcore.h> #endif @@ -72,7 +73,7 @@ return; /* do it only once */ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -273,6 +273,6 @@ }; int max; - max = sizeof(register_values) / sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -9,6 +9,7 @@ #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables @@ -90,7 +91,7 @@ m = sysconf.mb; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -258,7 +258,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -28,6 +28,7 @@ #include <cpu/amd/amdfam10_sysconf.h> +#include <stdlib.h> #include "mb_sysconf.h" /* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */ @@ -111,7 +112,7 @@ m->bus_type[i] = 0; } - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -275,7 +275,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -6,6 +6,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -157,11 +158,11 @@ #endif enable_smbus(); #if 0 - dump_spd_registers(sizeof(cpu)/sizeof(cpu[0]), cpu); + dump_spd_registers(ARRAY_SIZE(cpu), cpu); #endif memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); #if 0 dump_pci_devices(); Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -7,6 +7,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -215,7 +216,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); post_cache_as_ram(); Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> +#include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -51,7 +52,7 @@ int i; if (device == DIMM0){ - for (i=0; i < (sizeof spd_table/sizeof spd_table[0]); i++){ + for (i=0; i < (ARRAY_SIZE(spd_table)); i++){ if (spd_table[i].address == address){ return spd_table[i].data; } Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -31,6 +31,7 @@ #include <cpu/amd/dualcore.h> #endif #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> /* * Global variables for MB layouts and these will be shared by irqtable, Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> +#include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -77,7 +78,7 @@ /* dump_spd_registers(&memctrl[0]); */ /* sdram_initialize() runs out of registers. */ - /* sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); */ + /* sdram_initialize(ARRAY_SIZE(memctrl), memctrl); */ sdram_set_registers(memctrl); sdram_set_spd_registers(memctrl); Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> +#include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -67,6 +68,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> +#include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -70,6 +71,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> +#include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -70,6 +71,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> +#include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -70,6 +71,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> +#include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -67,6 +68,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -8,6 +8,7 @@ #endif #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables @@ -61,7 +62,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -259,7 +259,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> +#include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -70,6 +71,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -5,6 +5,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -139,7 +140,7 @@ // dump_ipmi_registers(); mainboard_set_e7520_leds(); // memreset_setup(); - sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); #endif Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -10,6 +10,7 @@ #endif #include <arch/hlt.h> //#include "option_table.h" +#include <stdlib.h> #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" @@ -100,7 +101,7 @@ memreset_setup(); - sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } #if 0 Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -6,6 +6,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> +#include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -48,7 +49,7 @@ #endif }; int i; - for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) { + for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { ram_check(check_addrs[i].lo, check_addrs[i].hi); } #endif Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> +#include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -67,6 +68,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -31,6 +31,7 @@ #endif #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables @@ -82,7 +83,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -277,7 +277,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/fanctl.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/fanctl.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/fanctl.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -1,4 +1,5 @@ #include <arch/io.h> +#include <stdlib.h> static void write_index(uint16_t port_base, uint8_t reg, uint8_t value) { @@ -67,15 +68,13 @@ { 0x13, 0x77} }; -#define ARRAYSIZE(x) sizeof x/sizeof *x - /* * Called from superio.c */ void init_ec(uint16_t base) { int i; - for (i=0; i<ARRAYSIZE(sequence); i++) { + for (i=0; i<ARRAY_SIZE(sequence); i++) { write_index(base, sequence[i].index, sequence[i].value); } } Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -29,6 +29,7 @@ #endif #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables @@ -80,7 +81,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -277,7 +277,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -8,6 +8,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -163,7 +164,7 @@ #endif memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); #if 0 dump_pci_devices(); Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -7,6 +7,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -211,7 +212,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); post_cache_as_ram(); Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -266,6 +266,6 @@ PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -8,6 +8,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -163,7 +164,7 @@ #endif memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); #if 0 dump_pci_devices(); Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -7,6 +7,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -211,7 +212,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); post_cache_as_ram(); Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -266,6 +266,6 @@ PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -5,6 +5,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -120,7 +121,7 @@ power_down_reset_check(); // dump_ipmi_registers(); mainboard_set_e7520_leds(); - sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + sdram_initialize(ARRAY_SIZE(mch), mch); ich5_watchdog_on(); #if 0 dump_pci_devices(); Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -7,6 +7,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -83,7 +84,7 @@ // dump_smbus_registers(); // memreset_setup(); No-op for this chipset - sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } // NOTE: ROMCC dies with an internal compiler error Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -9,6 +9,7 @@ #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables @@ -90,7 +91,7 @@ m = sysconf.mb; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -258,7 +258,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -6,6 +6,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -149,7 +150,7 @@ #endif memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); #if 0 dump_pci_devices(); Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -6,6 +6,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -148,7 +149,7 @@ #endif memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); #if 1 dump_pci_devices(); @@ -181,7 +182,7 @@ #endif }; int i; - for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) { + for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { ram_check(check_addrs[i].lo, check_addrs[i].hi); } #endif Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> +#include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -65,6 +66,6 @@ console_init(); report_bist_failure(bist); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -32,6 +32,7 @@ #endif #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> /* Global variables for MB layouts and these will be shared by irqtable, * mptable and acpi_tables. @@ -67,8 +68,8 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); - sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -28,6 +28,7 @@ #include <cpu/amd/dualcore.h> #endif #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> /* Global variables for MB layouts (shared by irqtable/mptable/acpi_table). */ // busnum is default. @@ -81,7 +82,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -278,6 +278,6 @@ }; - int max = sizeof(register_values) / sizeof(register_values[0]); + int max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -32,6 +32,7 @@ #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables @@ -82,7 +83,7 @@ m = sysconf.mb; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -285,7 +285,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -33,6 +33,7 @@ #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables @@ -110,7 +111,7 @@ m = sysconf.mb; memset(m, 0, sizeof(struct mb_sysconf_t)); - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -293,7 +293,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -6,6 +6,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -138,7 +139,7 @@ dump_spd_registers(&cpu[0]); #endif memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); #if 0 dump_pci_devices(); Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -265,7 +265,7 @@ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -30,6 +30,7 @@ #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables @@ -108,7 +109,7 @@ m = sysconf.mb; memset(m, 0, sizeof(struct mb_sysconf_t)); - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -277,7 +277,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -7,6 +7,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -191,7 +192,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -6,6 +6,7 @@ #if CONFIG_LOGICAL_CPUS==1 #include <cpu/amd/dualcore.h> #endif +#include <stdlib.h> // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables @@ -75,7 +76,7 @@ get_bus_conf_done = 1; - hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]); + hc_possible_num = ARRAY_SIZE(pci1234); get_sblk_pci1234(); Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -260,7 +260,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -29,6 +29,7 @@ #endif #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables @@ -81,7 +82,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -277,7 +277,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -5,6 +5,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -113,7 +114,7 @@ } #endif disable_watchdogs(); - sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + sdram_initialize(ARRAY_SIZE(mch), mch); #if 1 dump_pci_device(PCI_DEV(0, 0x00, 0)); // dump_bar14(PCI_DEV(0, 0x00, 0)); Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -5,6 +5,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -138,7 +139,7 @@ // dump_ipmi_registers(); // mainboard_set_e7520_leds(); // memreset_setup(); - sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); #endif Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -5,6 +5,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -139,7 +140,7 @@ // dump_ipmi_registers(); // mainboard_set_e7520_leds(); // memreset_setup(); - sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); #endif Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.updated.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.updated.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.updated.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -5,6 +5,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -139,7 +140,7 @@ // dump_ipmi_registers(); // mainboard_set_e7520_leds(); // memreset_setup(); - sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); #endif Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -5,6 +5,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -139,7 +140,7 @@ // dump_ipmi_registers(); mainboard_set_e7520_leds(); // memreset_setup(); - sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + sdram_initialize(ARRAY_SIZE(mch), mch); #if 1 dump_pci_devices(); #endif Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -5,6 +5,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -139,7 +140,7 @@ // dump_ipmi_registers(); mainboard_set_e7520_leds(); // memreset_setup(); - sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); + sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); #endif Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s1846/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s1846/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> +#include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -67,6 +68,6 @@ report_bist_failure(bist); enable_smbus(); /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); /* ram_check(0, 640 * 1024); */ } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -7,6 +7,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -96,7 +97,7 @@ #endif memreset_setup(); - sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } #if 0 else { Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -6,6 +6,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -197,6 +198,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -7,6 +7,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -206,7 +207,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); post_cache_as_ram(); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -7,6 +7,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -167,6 +168,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -7,6 +7,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -203,7 +204,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); post_cache_as_ram(); Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -7,6 +7,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -205,7 +206,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); post_cache_as_ram(); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -7,6 +7,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -172,6 +173,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -8,6 +8,7 @@ #endif #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables @@ -63,7 +64,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -258,7 +258,7 @@ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -7,6 +7,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -176,6 +177,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -7,6 +7,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -208,7 +209,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); post_cache_as_ram(); Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -6,6 +6,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -178,7 +179,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -8,6 +8,7 @@ #endif #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default @@ -65,7 +66,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -259,7 +259,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -6,6 +6,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -145,6 +146,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -8,6 +8,7 @@ #endif #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default @@ -71,7 +72,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -260,7 +260,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -6,6 +6,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -147,6 +148,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -8,6 +8,7 @@ #endif #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default @@ -68,7 +69,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -260,7 +260,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -7,6 +7,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -172,6 +173,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -8,6 +8,7 @@ #endif #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default @@ -76,7 +77,7 @@ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -261,7 +261,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -30,6 +30,7 @@ #include <cpu/amd/amdk8_sysconf.h> +#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables @@ -107,7 +108,7 @@ m = sysconf.mb; memset(m, 0, sizeof(struct mb_sysconf_t)); - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -277,7 +277,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/get_bus_conf.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/get_bus_conf.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -30,6 +30,7 @@ #include <cpu/amd/amdfam10_sysconf.h> +#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables @@ -83,7 +84,7 @@ m = sysconf.mb; memset(m, 0, sizeof(struct mb_sysconf_t)); - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -277,7 +277,7 @@ }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -7,6 +7,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -227,6 +228,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -7,6 +7,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -254,7 +255,7 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); post_cache_as_ram(); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -258,7 +258,7 @@ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -6,6 +6,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -227,6 +228,6 @@ enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -258,7 +258,7 @@ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/mainboard/via/epia/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/via/epia/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -6,6 +6,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> +#include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -107,7 +108,7 @@ /* this is way more generic than we need. - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); */ sdram_set_registers((const struct mem_controller *) 0); sdram_set_spd_registers((const struct mem_controller *) 0); @@ -129,7 +130,7 @@ #endif }; int i; - for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) { + for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { ram_check(check_addrs[i].lo, check_addrs[i].hi); } #endif Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/auto.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/auto.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -10,6 +10,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> +#include <stdlib.h> #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -146,7 +147,7 @@ #endif }; int i; - for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) { + for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { ram_check(check_addrs[i].lo, check_addrs[i].hi); } #endif Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -281,7 +281,7 @@ }; u32 max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -66,6 +66,7 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/hypertransport_def.h> +#include <stdlib.h> #include "arch/romcc_io.h" #include "amdk8.h" @@ -510,7 +511,7 @@ print_spew("setup_remote_node: "); /* copy the default resource map from node 0 */ - for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) { + for(i = 0; i < ARRAY_SIZE(pci_reg); i++) { uint32_t value; uint8_t reg; reg = pci_reg[i]; @@ -802,7 +803,7 @@ }; #endif - setup_row_indirect_group(conn4_1, sizeof(conn4_1)/sizeof(conn4_1[0])); + setup_row_indirect_group(conn4_1, ARRAY_SIZE(conn4_1)); setup_temp_row(0,2); verify_connection(7); @@ -893,7 +894,7 @@ 3,0,1,1, }; #endif - setup_remote_row_indirect_group(conn4_3, sizeof(conn4_3)/sizeof(conn4_3[0])); + setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3)); /* ready to enable RT for Node 3 */ rename_temp_node(3); @@ -909,7 +910,7 @@ 2,1,0,1, }; #endif - setup_row_indirect_group(conn4_2, sizeof(conn4_2)/sizeof(conn4_2[0])); + setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2)); #if 0 /*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */ @@ -974,7 +975,7 @@ #endif }; - setup_row_indirect_group(conn6_1, sizeof(conn6_1)/sizeof(conn6_1[0])); + setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1)); for(byte=0; byte<4; byte+=2) { setup_temp_row(byte,byte+2); @@ -998,7 +999,7 @@ #endif }; - setup_remote_row_indirect_group(conn6_2, sizeof(conn6_2)/sizeof(conn6_2[0])); + setup_remote_row_indirect_group(conn6_2, ARRAY_SIZE(conn6_2)); rename_temp_node(4); enable_routing(4); @@ -1084,7 +1085,7 @@ #endif }; - setup_remote_row_indirect_group(conn6_3, sizeof(conn6_3)/sizeof(conn6_3[0])); + setup_remote_row_indirect_group(conn6_3, ARRAY_SIZE(conn6_3)); /* ready to enable RT for 5 */ rename_temp_node(5); @@ -1110,7 +1111,7 @@ #endif }; - setup_row_indirect_group(conn6_4, sizeof(conn6_4)/sizeof(conn6_4[0])); + setup_row_indirect_group(conn6_4, ARRAY_SIZE(conn6_4)); #if 0 /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5) @@ -1202,7 +1203,7 @@ #endif }; - setup_row_indirect_group(conn8_1,sizeof(conn8_1)/sizeof(conn8_1[0])); + setup_row_indirect_group(conn8_1,ARRAY_SIZE(conn8_1)); for(byte=0; byte<6; byte+=2) { setup_temp_row(byte,byte+2); @@ -1225,7 +1226,7 @@ #endif }; - setup_remote_row_indirect_group(conn8_2, sizeof(conn8_2)/sizeof(conn8_2[0])); + setup_remote_row_indirect_group(conn8_2, ARRAY_SIZE(conn8_2)); #if CROSS_BAR_47_56 //init 5, 6 here @@ -1414,7 +1415,7 @@ #endif }; - setup_row_indirect_group(conn8_3, sizeof(conn8_3)/sizeof(conn8_3[0])); + setup_row_indirect_group(conn8_3, ARRAY_SIZE(conn8_3)); #if CROSS_BAR_47_56 /* for 47, 56, 57, 75, 46, 64 we need to substract another link to @@ -1455,7 +1456,7 @@ 7, 3, 6, }; - opt_broadcast_rt_group(conn8_4, sizeof(conn8_4)/sizeof(conn8_4[0])); + opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4)); static const u8 conn8_5[] = { 2, 7, 0, @@ -1463,7 +1464,7 @@ 3, 6, 1, }; - opt_broadcast_rt_plus_group(conn8_5, sizeof(conn8_5)/sizeof(conn8_5[0])); + opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5)); #endif @@ -1770,7 +1771,7 @@ 1,3, 2,3, }; - needs_reset |= optimize_connection_group(opt_conn4, sizeof(opt_conn4)/sizeof(opt_conn4[0])); + needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4)); } #endif @@ -1783,7 +1784,7 @@ 4, 5, #endif }; - needs_reset |= optimize_connection_group(opt_conn6, sizeof(opt_conn6)/sizeof(opt_conn6[0])); + needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6)); } #endif @@ -1798,7 +1799,7 @@ 5, 7, 6, 7, }; - needs_reset |= optimize_connection_group(opt_conn8, sizeof(opt_conn8)/sizeof(opt_conn8[0])); + needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8)); } #endif Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -10,6 +10,7 @@ #include <cpu/x86/mem.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> +#include <stdlib.h> #include "raminit.h" #include "amdk8.h" @@ -555,7 +556,7 @@ print_spew("setting up CPU"); print_spew_hex8(ctrl->node_id); print_spew(" northbridge registers\r\n"); - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); for(i = 0; i < max; i += 3) { device_t dev; unsigned where; @@ -1303,7 +1304,7 @@ } device0 = ctrl->channel0[i]; device1 = ctrl->channel1[i]; - for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) { + for(j = 0; j < ARRAY_SIZE(addresses); j++) { unsigned addr; addr = addresses[j]; value0 = spd_read_byte(device0, addr); Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -25,6 +25,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/tsc.h> +#include <stdlib.h> #include "raminit.h" #include "amdk8_f.h" #include "spd_ddr2.h" @@ -715,7 +716,7 @@ print_spew("setting up CPU"); print_spew_hex8(ctrl->node_id); print_spew(" northbridge registers\r\n"); - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); for (i = 0; i < max; i += 3) { device_t dev; unsigned where; @@ -1496,7 +1497,7 @@ } device0 = ctrl->channel0[i]; device1 = ctrl->channel1[i]; - for (j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) { + for (j = 0; j < ARRAY_SIZE(addresses); j++) { unsigned addr; addr = addresses[j]; value0 = spd_read_byte(device0, addr); Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -4,6 +4,7 @@ #include <string.h> #include <setjmp.h> #include <device/pci_def.h> +#include <stdlib.h> #include "amdk8.h" jmp_buf end_buf; @@ -341,7 +342,7 @@ }; console_init(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/resourcemap.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/resourcemap.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -253,6 +253,6 @@ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } Modified: trunk/coreboot-v2/src/northbridge/amd/gx2/chipsetinit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx2/chipsetinit.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/amd/gx2/chipsetinit.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -177,7 +177,7 @@ { FLASH_TYPE_NONE, 0, 0 }, /* CS3, or Flash Device 3 */ }; -#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0])) +#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable)) uint32_t FlashPort[] = { MDD_LBAR_FLSH0, Modified: trunk/coreboot-v2/src/northbridge/intel/e7501/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7501/raminit.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/intel/e7501/raminit.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -14,6 +14,7 @@ #include <assert.h> #include <spd.h> #include <sdram_mode.h> +#include <stdlib.h> #include "e7501.h" // Uncomment this to enable run-time checking of DIMM parameters @@ -1631,7 +1632,7 @@ static void ram_set_d0f0_regs(const struct mem_controller *ctrl) { int i; - int num_values = sizeof(constant_register_values)/sizeof(constant_register_values[0]); + int num_values = ARRAY_SIZE(constant_register_values); ASSERT((num_values % 3) == 0); // Bad table? Modified: trunk/coreboot-v2/src/northbridge/intel/e7520/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7520/raminit.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/intel/e7520/raminit.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -21,6 +21,7 @@ #include <cpu/x86/mem.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <stdlib.h> #include "raminit.h" #include "e7520.h" @@ -62,7 +63,7 @@ int i; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); for(i = 0; i < max; i += 3) { device_t dev; unsigned where; Modified: trunk/coreboot-v2/src/northbridge/intel/e7520/raminit_test.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7520/raminit_test.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/intel/e7520/raminit_test.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -4,6 +4,7 @@ #include <string.h> #include <setjmp.h> #include <device/pci_def.h> +#include <stdlib.h> #include "e7520.h" jmp_buf end_buf; @@ -341,7 +342,7 @@ }; console_init(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } Modified: trunk/coreboot-v2/src/northbridge/intel/e7525/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7525/raminit.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/intel/e7525/raminit.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -21,6 +21,7 @@ #include <cpu/x86/mem.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <stdlib.h> #include "raminit.h" #include "e7525.h" @@ -62,7 +63,7 @@ int i; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); for(i = 0; i < max; i += 3) { device_t dev; unsigned where; Modified: trunk/coreboot-v2/src/northbridge/intel/e7525/raminit_test.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7525/raminit_test.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/intel/e7525/raminit_test.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -4,6 +4,7 @@ #include <string.h> #include <setjmp.h> #include <device/pci_def.h> +#include <stdlib.h> #include "e7525.h" jmp_buf end_buf; @@ -313,7 +314,7 @@ }; console_init(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + sdram_initialize(ARRAY_SIZE(cpu), cpu); } #endif Modified: trunk/coreboot-v2/src/northbridge/intel/i3100/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i3100/raminit.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/intel/i3100/raminit.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -22,6 +22,7 @@ #include <cpu/x86/mem.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <stdlib.h> #include "raminit.h" #include "i3100.h" @@ -64,7 +65,7 @@ int i; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); for(i = 0; i < max; i += 3) { device_t dev; u32 where; Modified: trunk/coreboot-v2/src/northbridge/intel/i440bx/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i440bx/raminit.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/intel/i440bx/raminit.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -21,6 +21,7 @@ #include <spd.h> #include <sdram_mode.h> #include <delay.h> +#include <stdlib.h> #include "i440bx.h" /*----------------------------------------------------------------------------- @@ -430,7 +431,7 @@ PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n"); DUMPNORTH(); - max = sizeof(register_values) / sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); /* Set registers as specified in the register_values[] array. */ for (i = 0; i < max; i += 3) { Modified: trunk/coreboot-v2/src/northbridge/intel/i855pm/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i855pm/raminit.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/intel/i855pm/raminit.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -384,7 +384,7 @@ #endif int i; int max; - max = sizeof(register_values)/sizeof(register_values[0]); + max = ARRAY_SIZE(register_values); for(i = 0; i < max; i += 3) { uint32_t reg; #if DEBUG_RAM_CONFIG >=2 Modified: trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -115,7 +115,7 @@ unsigned char rambits; int i, idx; - for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) { + for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); /* these are ENDING addresses, not sizes. Modified: trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -287,7 +287,7 @@ unsigned char rambits; int i, idx; - for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) { + for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); /* these are ENDING addresses, not sizes. Modified: trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -10,6 +10,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "amd8111.h" #define NMI_OFF 0 @@ -77,7 +78,7 @@ ioapicregvalues[0].value_high = bsp_apicid<<(56-32); printk_debug("amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid); - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; Modified: trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -29,6 +29,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/vr.h> #include <cpu/amd/geode_post_code.h> +#include <stdlib.h> #include "chip.h" #include "cs5536.h" @@ -93,7 +94,7 @@ {FLASH_TYPE_NONE, 0, 0}, /* CS3, or Flash Device 3 */ }; -#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0])) +#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable)) uint32_t FlashPort[] = { MDD_LBAR_FLSH0, Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -27,6 +27,7 @@ #include <bitops.h> #include <arch/io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "sb600.h" #include "sb600_smbus.c" @@ -101,7 +102,7 @@ l = (unsigned long *)ioapic_base; - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -102,7 +102,7 @@ #endif }; - setup_resource_map(ctrl_devport_conf, sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0])); + setup_resource_map(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf)); } @@ -121,7 +121,7 @@ #endif }; - setup_resource_map(ctrl_devport_conf_clear, sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0])); + setup_resource_map(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear)); } @@ -324,7 +324,7 @@ - setup_resource_map_x(ctrl_conf, sizeof(ctrl_conf)/sizeof(ctrl_conf[0])); + setup_resource_map_x(ctrl_conf, ARRAY_SIZE(ctrl_conf)); setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64); setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64); Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -105,12 +105,12 @@ for(j = 0; j < ck804_num; j++ ) { if(busn[j]==0) { //sb chain setup_resource_map_offset(ctrl_devport_conf, - sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]), + ARRAY_SIZE(ctrl_devport_conf), PCI_DEV(busn[j], 0, 0) , io_base[j]); continue; } setup_resource_map_offset(ctrl_devport_conf_b, - sizeof(ctrl_devport_conf_b)/sizeof(ctrl_devport_conf_b[0]), + ARRAY_SIZE(ctrl_devport_conf_b), PCI_DEV(busn[j], 0, 0) , io_base[j]); } } @@ -132,12 +132,12 @@ for(j = 0; j < ck804_num; j++ ) { if(busn[j]==0) { //sb chain setup_resource_map_offset(ctrl_devport_conf_clear, - sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]), + ARRAY_SIZE(ctrl_devport_conf_clear), PCI_DEV(busn[j], 0, 0) , io_base[j]); continue; } setup_resource_map_offset(ctrl_devport_conf_clear_b, - sizeof(ctrl_devport_conf_clear_b)/sizeof(ctrl_devport_conf_clear_b[0]), + ARRAY_SIZE(ctrl_devport_conf_clear_b), PCI_DEV(busn[j], 0, 0) , io_base[j]); } @@ -327,13 +327,13 @@ for(j=0; j<ck804_num; j++) { if(busn[j] == 0) { - setup_resource_map_x_offset(ctrl_conf_master, sizeof(ctrl_conf_master)/sizeof(ctrl_conf_master[0]), + setup_resource_map_x_offset(ctrl_conf_master, ARRAY_SIZE(ctrl_conf_master), PCI_DEV(busn[0],0,0), io_base[0]); continue; } - setup_resource_map_x_offset(ctrl_conf_slave, sizeof(ctrl_conf_slave)/sizeof(ctrl_conf_slave[0]), + setup_resource_map_x_offset(ctrl_conf_slave, ARRAY_SIZE(ctrl_conf_slave), PCI_DEV(busn[j],0,0), io_base[j]); } Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -15,6 +15,7 @@ #include <bitops.h> #include <arch/io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "ck804.h" #define CK804_CHIP_REV 2 @@ -82,7 +83,7 @@ l = (unsigned long *) ioapic_base; - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -106,7 +106,7 @@ int j; for(j = 0; j < mcp55_num; j++ ) { setup_resource_map_offset(ctrl_devport_conf, - sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]), + ARRAY_SIZE(ctrl_devport_conf), PCI_DEV(busn[j], devn[j], 0) , io_base[j]); } } @@ -123,7 +123,7 @@ int j; for(j = 0; j < mcp55_num; j++ ) { setup_resource_map_offset(ctrl_devport_conf_clear, - sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]), + ARRAY_SIZE(ctrl_devport_conf_clear), PCI_DEV(busn[j], devn[j], 0) , io_base[j]); } @@ -327,23 +327,23 @@ for(j=0; j<mcp55_num; j++) { mcp55_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]); - setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]), + setup_resource_map_x_offset(ctrl_conf_1, ARRAY_SIZE(ctrl_conf_1), PCI_DEV(busn[j], devn[j], 0), io_base[j]); for(i=0; i<3; i++) { // three SATA - setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]), + setup_resource_map_x_offset(ctrl_conf_1_1, ARRAY_SIZE(ctrl_conf_1_1), PCI_DEV(busn[j], devn[j], i), io_base[j]); } if(busn[j] == 0) { - setup_resource_map_x_offset(ctrl_conf_mcp55_only, sizeof(ctrl_conf_mcp55_only)/sizeof(ctrl_conf_mcp55_only[0]), + setup_resource_map_x_offset(ctrl_conf_mcp55_only, ARRAY_SIZE(ctrl_conf_mcp55_only), PCI_DEV(busn[j], devn[j], 0), io_base[j]); } if( (busn[j] == 0) && (mcp55_num>1) ) { - setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]), + setup_resource_map_x_offset(ctrl_conf_master_only, ARRAY_SIZE(ctrl_conf_master_only), PCI_DEV(busn[j], devn[j], 0), io_base[j]); } - setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]), + setup_resource_map_x_offset(ctrl_conf_2, ARRAY_SIZE(ctrl_conf_2), PCI_DEV(busn[j], devn[j], 0), io_base[j]); } Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -34,6 +34,7 @@ #include <bitops.h> #include <arch/io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "mcp55.h" #define NMI_OFF 0 @@ -106,7 +107,7 @@ l = (unsigned long *) ioapic_base; - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; Modified: trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -36,6 +36,7 @@ #include <bitops.h> #include <arch/io.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #include "sis966.h" #include <pc80/keyboard.h> @@ -102,7 +103,7 @@ l = (unsigned long *) ioapic_base; - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; Modified: trunk/coreboot-v2/src/stream/fs/vfs.c =================================================================== --- trunk/coreboot-v2/src/stream/fs/vfs.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/stream/fs/vfs.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -70,7 +70,7 @@ { int i; - for (i = 0; i < sizeof(fsys_table)/sizeof(fsys_table[0]); i++) { + for (i = 0; i < ARRAY_SIZE(fsys_table); i++) { if (fsys_table[i].mount_func()) { fsys = &fsys_table[i]; printk_info("Mounted %s\n", fsys->name); Modified: trunk/coreboot-v2/src/superio/ite/it8661f/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8661f/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/ite/it8661f/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -23,6 +23,7 @@ #include <device/device.h> #include <device/pnp.h> #include <uart8250.h> +#include <stdlib.h> #include "chip.h" #include "it8661f.h" @@ -72,7 +73,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8661f_ops = { Modified: trunk/coreboot-v2/src/superio/ite/it8671f/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8671f/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/ite/it8671f/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -22,6 +22,7 @@ #include <device/pnp.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <stdlib.h> #include "chip.h" #include "it8671f.h" @@ -77,7 +78,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8671f_ops = { Modified: trunk/coreboot-v2/src/superio/ite/it8673f/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8673f/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/ite/it8673f/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -22,6 +22,7 @@ #include <device/pnp.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <stdlib.h> #include "chip.h" #include "it8673f.h" @@ -79,7 +80,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8673f_ops = { Modified: trunk/coreboot-v2/src/superio/ite/it8705f/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8705f/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/ite/it8705f/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -23,6 +23,7 @@ #include <device/device.h> #include <device/pnp.h> #include <uart8250.h> +#include <stdlib.h> #include "chip.h" #include "it8705f.h" @@ -80,7 +81,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8705f_ops = { Modified: trunk/coreboot-v2/src/superio/ite/it8712f/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8712f/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/ite/it8712f/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -24,6 +24,7 @@ #include <uart8250.h> #include <pc80/keyboard.h> #include <arch/io.h> +#include <stdlib.h> #include "chip.h" #include "it8712f.h" @@ -134,7 +135,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8712f_ops = { Modified: trunk/coreboot-v2/src/superio/ite/it8716f/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8716f/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/ite/it8716f/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -27,6 +27,7 @@ #include <uart8250.h> #include <pc80/keyboard.h> #include <arch/io.h> +#include <stdlib.h> #include "chip.h" #include "it8716f.h" @@ -165,7 +166,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info) / sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8716f_ops = { Modified: trunk/coreboot-v2/src/superio/ite/it8718f/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8718f/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/ite/it8718f/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -22,6 +22,7 @@ #include <device/pnp.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <stdlib.h> #include "chip.h" #include "it8718f.h" @@ -81,7 +82,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8718f_ops = { Modified: trunk/coreboot-v2/src/superio/nsc/pc8374/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc8374/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/nsc/pc8374/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -10,6 +10,7 @@ #include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <stdlib.h> #include "chip.h" #include "pc8374.h" @@ -64,7 +65,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc8374_ops = { Modified: trunk/coreboot-v2/src/superio/nsc/pc87309/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc87309/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/nsc/pc87309/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -23,6 +23,7 @@ #include <device/pnp.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <stdlib.h> #include "chip.h" #include "pc87309.h" @@ -73,7 +74,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info) / sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc87309_ops = { Modified: trunk/coreboot-v2/src/superio/nsc/pc87351/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc87351/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/nsc/pc87351/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -16,6 +16,7 @@ #include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <stdlib.h> #include "chip.h" #include "pc87351.h" @@ -71,7 +72,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc87351_ops = { Modified: trunk/coreboot-v2/src/superio/nsc/pc87360/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc87360/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/nsc/pc87360/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -10,6 +10,7 @@ #include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <stdlib.h> #include "chip.h" #include "pc87360.h" @@ -67,7 +68,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc87360_ops = { Modified: trunk/coreboot-v2/src/superio/nsc/pc87366/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc87366/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/nsc/pc87366/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -10,6 +10,7 @@ #include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <stdlib.h> #include "chip.h" #include "pc87366.h" @@ -67,7 +68,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc87366_ops = { Modified: trunk/coreboot-v2/src/superio/nsc/pc87417/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc87417/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/nsc/pc87417/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -12,6 +12,7 @@ #include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <stdlib.h> #include "chip.h" #include "pc87417.h" @@ -68,7 +69,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc87417_ops = { Modified: trunk/coreboot-v2/src/superio/nsc/pc87427/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc87427/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/nsc/pc87427/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -8,6 +8,7 @@ #include <console/console.h> #include <string.h> #include <bitops.h> +#include <stdlib.h> #include "chip.h" #include "pc87427.h" @@ -68,7 +69,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc87427_ops = { Modified: trunk/coreboot-v2/src/superio/nsc/pc97307/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc97307/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/nsc/pc97307/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -5,6 +5,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pnp.h> +#include <stdlib.h> #include "chip.h" #include "pc97307.h" @@ -79,7 +80,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc97307_ops = { Modified: trunk/coreboot-v2/src/superio/nsc/pc97317/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc97317/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/nsc/pc97317/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -5,6 +5,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pnp.h> +#include <stdlib.h> #include "chip.h" #include "pc97317.h" @@ -81,7 +82,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc97317_ops = { Modified: trunk/coreboot-v2/src/superio/smsc/fdc37m60x/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/smsc/fdc37m60x/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/smsc/fdc37m60x/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -22,6 +22,7 @@ #include <device/pnp.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <stdlib.h> #include "chip.h" #include "fdc37m60x.h" @@ -77,7 +78,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_smsc_fdc37m60x_ops = { Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b272/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/smsc/lpc47b272/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/smsc/lpc47b272/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -32,6 +32,7 @@ #include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <stdlib.h> #include "chip.h" #include "lpc47b272.h" @@ -84,7 +85,7 @@ static void enable_dev(device_t dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -14,6 +14,7 @@ #include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <stdlib.h> #include "chip.h" #include "lpc47b397.h" @@ -207,7 +208,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_smsc_lpc47b397_ops = { Modified: trunk/coreboot-v2/src/superio/smsc/lpc47m10x/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/smsc/lpc47m10x/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/smsc/lpc47m10x/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -31,6 +31,7 @@ #include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <stdlib.h> #include "chip.h" #include "lpc47m10x.h" @@ -82,7 +83,7 @@ static void enable_dev(device_t dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } Modified: trunk/coreboot-v2/src/superio/smsc/lpc47n217/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/smsc/lpc47n217/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/smsc/lpc47n217/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -33,6 +33,7 @@ #include <bitops.h> #include <uart8250.h> #include <assert.h> +#include <stdlib.h> #include "chip.h" #include "lpc47n217.h" @@ -86,7 +87,7 @@ static void enable_dev(device_t dev) { pnp_enable_devices(dev, &pnp_ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } Modified: trunk/coreboot-v2/src/superio/via/vt1211/vt1211.c =================================================================== --- trunk/coreboot-v2/src/superio/via/vt1211/vt1211.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/via/vt1211/vt1211.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -26,6 +26,7 @@ #include <device/device.h> #include <device/pnp.h> #include <uart8250.h> +#include <stdlib.h> #include "vt1211.h" #include "chip.h" @@ -212,7 +213,7 @@ printk_debug("vt1211 enabling PNP devices.\n"); pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info) / sizeof(pnp_dev_info[0]), + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } Modified: trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -30,6 +30,7 @@ #include <uart8250.h> #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> +#include <stdlib.h> #include "chip.h" #include "w83627ehg.h" @@ -93,7 +94,7 @@ 0x48, 0x7f, 0x2a, /* Set SMBus base to 0x54 >> 1. */ }; - for(i = 0; i < sizeof(hwm_reg_values)/sizeof(hwm_reg_values[0]); i += 3) { + for(i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) { reg = hwm_reg_values[i]; value = pnp_read_index(base, reg); value &= 0xff & (~(hwm_reg_values[i + 1])); @@ -200,7 +201,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_winbond_w83627ehg_ops = { Modified: trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -13,6 +13,7 @@ #include <uart8250.h> #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> +#include <stdlib.h> #include "chip.h" #include "w83627hf.h" @@ -83,7 +84,7 @@ }; - for(i = 0; i< sizeof(hwm_reg_values)/sizeof(hwm_reg_values[0]); i+=3 ) { + for(i = 0; i< ARRAY_SIZE(hwm_reg_values); i+=3 ) { reg = hwm_reg_values[i]; value = pnp_read_index(base, reg); value &= 0xff & hwm_reg_values[i+1]; @@ -189,7 +190,7 @@ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_winbond_w83627hf_ops = { Modified: trunk/coreboot-v2/src/superio/winbond/w83627thf/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627thf/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/winbond/w83627thf/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -12,6 +12,7 @@ #include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <stdlib.h> #include "chip.h" #include "w83627thf.h" @@ -101,7 +102,7 @@ static void enable_dev(device_t dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_winbond_w83627thf_ops = { Modified: trunk/coreboot-v2/src/superio/winbond/w83977f/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83977f/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/winbond/w83977f/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -26,6 +26,7 @@ #include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <stdlib.h> #include "chip.h" #include "w83977f.h" @@ -109,7 +110,7 @@ static void enable_dev(device_t dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_winbond_w83977f_ops = { Modified: trunk/coreboot-v2/src/superio/winbond/w83977tf/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83977tf/superio.c 2008-09-30 17:09:44 UTC (rev 3623) +++ trunk/coreboot-v2/src/superio/winbond/w83977tf/superio.c 2008-10-01 12:52:52 UTC (rev 3624) @@ -19,6 +19,7 @@ #include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <stdlib.h> #include "chip.h" #include "w83977tf.h" @@ -105,7 +106,7 @@ static void enable_dev(device_t dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_winbond_w83977tf_ops = {

1 0

r877 - in coreboot-v3: arch/x86/amd/model_fxx mainboard/gigabyte/m57sli northbridge/amd/k8 southbridge/nvidia/mcp55
by svn＠coreboot.org Oct. 1, 2008

Oct. 1, 2008

Author: rminnich Date: 2008-10-01 09:23:05 +0200 (Wed, 01 Oct 2008) New Revision: 877 Modified: coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h coreboot-v3/northbridge/amd/k8/dqs.c coreboot-v3/northbridge/amd/k8/raminit.c coreboot-v3/southbridge/nvidia/mcp55/ide.c coreboot-v3/southbridge/nvidia/mcp55/lpc.c coreboot-v3/southbridge/nvidia/mcp55/mcp55.c coreboot-v3/southbridge/nvidia/mcp55/pci.c coreboot-v3/southbridge/nvidia/mcp55/pcie.c coreboot-v3/southbridge/nvidia/mcp55/sata.c coreboot-v3/southbridge/nvidia/mcp55/usb2.c Log: m57sli mostly builds again. The stage0 is too large at 24k. We need to figure out if we should just grow stage0. My inclination is to say 'yes'. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c =================================================================== --- coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c 2008-10-01 06:47:51 UTC (rev 876) +++ coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c 2008-10-01 07:23:05 UTC (rev 877) @@ -300,9 +300,9 @@ #if MEM_TRAIN_SEQ == 1 -static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, +void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, - unsigned retcall); + void * retcall); #endif /** @@ -479,7 +479,7 @@ /* this is not done on Serengeti. */ #if MEM_TRAIN_SEQ == 1 train_ram_on_node(id.nodeid, id.coreid, sysinfo, - STOP_CAR_AND_CPU); + (void *)STOP_CAR_AND_CPU); #endif /* this is inline and there is no return. */ STOP_CAR_AND_CPU(); Modified: coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h 2008-10-01 06:47:51 UTC (rev 876) +++ coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h 2008-10-01 07:23:05 UTC (rev 877) @@ -43,3 +43,6 @@ /* architecture stuff which ought to be set "somewhere" "SOMEHOW" */ /* preferably by asking the CPU, not be a DEFINE! */ #define CPU_ADDR_BITS 40 + +/* you don't want to set this in Kconfig or dts either. It's dangerous! */ +#define CONFIG_AP_CODE_IN_CAR 0 Modified: coreboot-v3/northbridge/amd/k8/dqs.c =================================================================== --- coreboot-v3/northbridge/amd/k8/dqs.c 2008-10-01 06:47:51 UTC (rev 876) +++ coreboot-v3/northbridge/amd/k8/dqs.c 2008-10-01 07:23:05 UTC (rev 877) @@ -26,6 +26,7 @@ #include <macros.h> #include <spd.h> #include <cpu.h> +#include <globalvars.h> #include <msr.h> #include <device/pci.h> #include <pci_ops.h> @@ -1938,10 +1939,11 @@ #if MEM_TRAIN_SEQ > 0 -static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info *sysinfo, unsigned int v) +void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info *sysinfo) { int ii; + int v = 1; /* used to be a parameter; consider making it one again */ u64 tsc[4]; @@ -1972,9 +1974,8 @@ } tsc[1] = cycles(); if (DQS_TRAIN_DEBUG) { - printk(BIOS_DEBUG, "set DQS timing:DQSPos: "); + printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x", i); } - print_debug_hex8(i); } if(train_DqsPos(ctrl, sysinfo)) { @@ -1987,9 +1988,8 @@ tsc[2] = cycles(); if (DQS_TRAIN_DEBUG) { - printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: "); + printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i); } - print_debug_hex8(i); } if(train_DqsRcvrEn(ctrl, 2, sysinfo)){ sysinfo->mem_trained[i]=0x83; // @@ -2011,7 +2011,7 @@ if(v) { for(ii=0;ii<4;ii++) { - print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo); + printk(BIOS_ERR, "Total DQS Training : tsc %d: %llx", ii, tsc[ii]); } } @@ -2025,17 +2025,21 @@ #if MEM_TRAIN_SEQ == 1 static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info *sysinfox) { - dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo, 0); // keep the output tidy + dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo); // keep the output tidy // memcpy(&sysinfox->dqs_rcvr_dly_a[nodeid * 2 * 8],&sysinfo->dqs_rcvr_dly_a[nodeid * 2 * 8], 2*8); // memcpy(&sysinfox->dqs_delay_a[nodeid * 2 * 2 * 9], &sysinfo->dqs_delay_a[nodeid * 2 * 2 * 9], 2 * 2 * 9); sysinfox->mem_trained[nodeid] = sysinfo->mem_trained[nodeid]; } static void copy_and_run_ap_code_in_car(unsigned ret_addr); -static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) +void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, void * retcall) { if(coreid) return; // only do it on core0 - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); + /* this is a little weird. We're going to get the address of the global vars. But we're in CAR, so + * it's really private. We're going to copy from global memory, which is node 0 memory, which + * is working at this point. + */ + struct sys_info *sysinfox = & global_vars()->sys_info; wait_till_sysinfo_in_ram(); // use pci to get it if(sysinfox->mem_trained[nodeid] == 0x80) { @@ -2046,7 +2050,7 @@ sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid]; memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller)); #else - memcpy(sysinfo, sysinfox, DCACHE_RAM_GLOBAL_VAR_SIZE); + memcpy(sysinfo, sysinfox, sizeof(*sysinfo)); #endif set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's #if CONFIG_AP_CODE_IN_CAR == 0 @@ -2056,7 +2060,9 @@ #else /* Can copy dqs_timing to ap cache and run from cache? * we need coreboot_ap_car.rom? and treat it as coreboot_ram.rom for ap ? + * not sure how we'll return. */ +#warning resolve issues about returning from the copy_and_run_ap_code_in_car. copy_and_run_ap_code_in_car(retcall); // will go back by jump #endif Modified: coreboot-v3/northbridge/amd/k8/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/k8/raminit.c 2008-10-01 06:47:51 UTC (rev 876) +++ coreboot-v3/northbridge/amd/k8/raminit.c 2008-10-01 07:23:05 UTC (rev 877) @@ -2653,10 +2653,10 @@ #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 //We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some - u32 basek_pri; + u32 basek_pri = 0; for(i=0; i<controllers; i++) { u32 base; - unsigned base_k; + u32 base_k; base = pci_conf1_read_config32(ctrl[0].f1, 0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; Modified: coreboot-v3/southbridge/nvidia/mcp55/ide.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/ide.c 2008-10-01 06:47:51 UTC (rev 876) +++ coreboot-v3/southbridge/nvidia/mcp55/ide.c 2008-10-01 07:23:05 UTC (rev 877) @@ -41,7 +41,7 @@ u16 word; u8 byte; - word = pci_conf1_read_config16(dev, 0x50); + word = pci_read_config16(dev, 0x50); /* Ensure prefetch is disabled */ word &= ~((1 << 15) | (1 << 13)); if (conf->ide1_enable) { @@ -56,15 +56,15 @@ word |= (1<<12); word |= (1<<14); - pci_conf1_write_config16(dev, 0x50, word); + pci_write_config16(dev, 0x50, word); byte = 0x20 ; // Latency: 64-->32 - pci_conf1_write_config8(dev, 0xd, byte); + pci_write_config8(dev, 0xd, byte); - dword = pci_conf1_read_config32(dev, 0xf8); + dword = pci_read_config32(dev, 0xf8); dword |= 12; - pci_conf1_write_config32(dev, 0xf8, dword); + pci_write_config32(dev, 0xf8, dword); #ifdef CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif Modified: coreboot-v3/southbridge/nvidia/mcp55/lpc.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-10-01 06:47:51 UTC (rev 876) +++ coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-10-01 07:23:05 UTC (rev 877) @@ -144,10 +144,10 @@ u32 dword; /* IO APIC initialization */ - byte = pci_conf1_read_config8(dev, 0x74); + byte = pci_read_config8(dev, 0x74); byte |= (1<<0); // enable APIC - pci_conf1_write_config8(dev, 0x74, byte); - dword = pci_conf1_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14 + pci_write_config8(dev, 0x74, byte); + dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14 setup_ioapic(dword, master); } @@ -162,8 +162,8 @@ { unsigned long hpet_address; - pci_conf1_write_config32(dev,0x44, 0xfed00001); - hpet_address=pci_conf1_read_config32(dev,0x44)& 0xfffffffe; + pci_write_config32(dev,0x44, 0xfed00001); + hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe; printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address); } #endif @@ -180,20 +180,20 @@ #warning posted memory write enable disabled in mcp55 lpc? #if 0 /* posted memory write enable */ - byte = pci_conf1_read_config8(dev, 0x46); - pci_conf1_write_config8(dev, 0x46, byte | (1<<0)); + byte = pci_read_config8(dev, 0x46); + pci_write_config8(dev, 0x46, byte | (1<<0)); #endif /* power after power fail */ #if 1 on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); - byte = pci_conf1_read_config8(dev, PREVIOUS_POWER_STATE); + byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; if (!on) { byte |= 0x40; } - pci_conf1_write_config8(dev, PREVIOUS_POWER_STATE, byte); + pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off"); #endif /* Throttle the CPU speed down for testing */ @@ -202,7 +202,7 @@ if(on) { u16 pm10_bar; u32 dword; - pm10_bar = (pci_conf1_read_config16(dev, 0x60)&0xff00); + pm10_bar = (pci_read_config16(dev, 0x60)&0xff00); outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); dword = inl(pm10_bar + 0x10); on = 8-on; @@ -213,16 +213,16 @@ #if 0 // default is enabled /* Enable Port 92 fast reset */ - byte = pci_conf1_read_config8(dev, 0xe8); + byte = pci_read_config8(dev, 0xe8); byte |= ~(1 << 3); - pci_conf1_write_config8(dev, 0xe8, byte); + pci_write_config8(dev, 0xe8, byte); #endif /* Enable Error reporting */ /* Set up sync flood detected */ - byte = pci_conf1_read_config8(dev, 0x47); + byte = pci_read_config8(dev, 0x47); byte |= (1 << 1); - pci_conf1_write_config8(dev, 0x47, byte); + pci_write_config8(dev, 0x47, byte); /* Set up NMI on errors */ byte = inb(0x70); // RTC70 @@ -286,7 +286,7 @@ int i; int var_num = 0; - reg = pci_conf1_read_config32(dev, 0xa0); + reg = pci_read_config32(dev, 0xa0); for (link = 0; link < dev->links; link++) { struct device *child; @@ -324,9 +324,9 @@ } } } - pci_conf1_write_config32(dev, 0xa0, reg); + pci_write_config32(dev, 0xa0, reg); for(i=0;i<var_num;i++) { - pci_conf1_write_config32(dev, 0xa8 + i*4, reg_var[i]); + pci_write_config32(dev, 0xa8 + i*4, reg_var[i]); } Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-10-01 06:47:51 UTC (rev 876) +++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-10-01 07:23:05 UTC (rev 877) @@ -52,7 +52,7 @@ (lpc_dev->id.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO) ) ) { u32 id; - id = pci_conf1_read_config32(lpc_dev, PCI_VENDOR_ID); + id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); if ( (id < (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) || (id > (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16))) ) { @@ -82,7 +82,7 @@ /* sorry. Again, anonymous unions etc. would make this easier. */ if(dev->id.pci.device==0x0000) { - vendorid = pci_conf1_read_config32(dev, PCI_VENDOR_ID); + vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid>>16) & 0xffff; // vendorid &= 0xffff; } else { @@ -180,14 +180,14 @@ if(!sm_dev) return; if ( sm_dev ) { - reg_old = reg = pci_conf1_read_config32(sm_dev, 0xe4); + reg_old = reg = pci_read_config32(sm_dev, 0xe4); if (!dev->enabled) { //disable it reg |= (1<<index2); } if (reg != reg_old) { - pci_conf1_write_config32(sm_dev, 0xe4, reg); + pci_write_config32(sm_dev, 0xe4, reg); } } @@ -199,14 +199,14 @@ if ( index == 0) { // for LPC // expose ioapic base - byte = pci_conf1_read_config8(lpc_dev, 0x74); + byte = pci_read_config8(lpc_dev, 0x74); byte |= ((1<<1)); // expose the BAR - pci_conf1_write_config8(dev, 0x74, byte); + pci_write_config8(dev, 0x74, byte); // expose trap base - byte = pci_conf1_read_config8(lpc_dev, 0xdd); + byte = pci_read_config8(lpc_dev, 0xdd); byte |= ((1<<0)|(1<<3)); // expose the BAR and enable write - pci_conf1_write_config8(dev, 0xdd, byte); + pci_write_config8(dev, 0xdd, byte); return; @@ -216,16 +216,16 @@ sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1); if(!sm_dev) return; - final_reg = pci_conf1_read_config32(sm_dev, 0xe8); + final_reg = pci_read_config32(sm_dev, 0xe8); final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9)); - pci_conf1_write_config32(sm_dev, 0xe8, final_reg); //enable all at first + pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first #if 0 - reg_old = reg = pci_conf1_read_config32(sm_dev, 0xe4); + reg_old = reg = pci_read_config32(sm_dev, 0xe4); // reg |= (1<<0); reg &= ~(0x3f<<4); if (reg != reg_old) { printk_debug("mcp55.c pcie enabled\n"); - pci_conf1_write_config32(sm_dev, 0xe4, reg); + pci_write_config32(sm_dev, 0xe4, reg); } #endif } @@ -238,9 +238,9 @@ if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8 sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1); if(!sm_dev) return; - reg_old = pci_conf1_read_config32(sm_dev, 0xe8); + reg_old = pci_read_config32(sm_dev, 0xe8); if (final_reg != reg_old) { - pci_conf1_write_config32(sm_dev, 0xe8, final_reg); + pci_write_config32(sm_dev, 0xe8, final_reg); } } @@ -251,7 +251,7 @@ void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { - pci_conf1_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } Modified: coreboot-v3/southbridge/nvidia/mcp55/pci.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/pci.c 2008-10-01 06:47:51 UTC (rev 876) +++ coreboot-v3/southbridge/nvidia/mcp55/pci.c 2008-10-01 07:23:05 UTC (rev 877) @@ -43,23 +43,23 @@ #endif /* System error enable */ - dword = pci_conf1_read_config32(dev, 0x04); + dword = pci_read_config32(dev, 0x04); dword |= (1<<8); /* System error enable */ dword |= (1<<30); /* Clear possible errors */ - pci_conf1_write_config32(dev, 0x04, dword); + pci_write_config32(dev, 0x04, dword); #if 1 //only need (a01,xx] - word = pci_conf1_read_config16(dev, 0x48); + word = pci_read_config16(dev, 0x48); word |= (1<<0); /* MRL2MRM */ word |= (1<<2); /* MR2MRM */ - pci_conf1_write_config16(dev, 0x48, word); + pci_write_config16(dev, 0x48, word); #endif #if 1 - dword = pci_conf1_read_config32(dev, 0x4c); + dword = pci_read_config32(dev, 0x4c); dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/ - pci_conf1_write_config32(dev, 0x4c, dword); + pci_write_config32(dev, 0x4c, dword); #endif #ifdef CONFIG_PCI_64BIT_PREF_MEM @@ -84,7 +84,7 @@ printk(BIOS_DEBUG, "dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base); #endif printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword); - pci_conf1_write_config32(dev, 0x50, dword); //TOM + pci_write_config32(dev, 0x50, dword); //TOM } Modified: coreboot-v3/southbridge/nvidia/mcp55/pcie.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/pcie.c 2008-10-01 06:47:51 UTC (rev 876) +++ coreboot-v3/southbridge/nvidia/mcp55/pcie.c 2008-10-01 07:23:05 UTC (rev 877) @@ -39,10 +39,10 @@ u32 dword; /* System error enable */ - dword = pci_conf1_read_config32(dev, 0x04); + dword = pci_read_config32(dev, 0x04); dword |= (1<<8); /* System error enable */ dword |= (1<<30); /* Clear possible errors */ - pci_conf1_write_config32(dev, 0x04, dword); + pci_write_config32(dev, 0x04, dword); } Modified: coreboot-v3/southbridge/nvidia/mcp55/sata.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/sata.c 2008-10-01 06:47:51 UTC (rev 876) +++ coreboot-v3/southbridge/nvidia/mcp55/sata.c 2008-10-01 07:23:05 UTC (rev 877) @@ -40,7 +40,7 @@ struct southbridge_nvidia_mcp55_sata_config *conf = (struct southbridge_nvidia_mcp55_sata_config *)dev->device_configuration; - dword = pci_conf1_read_config32(dev, 0x50); + dword = pci_read_config32(dev, 0x50); /* Ensure prefetch is disabled */ dword &= ~((1 << 15) | (1 << 13)); if(conf) { @@ -62,11 +62,11 @@ dword &= ~(0x1f<<24); dword |= (0x15<<24); #endif - pci_conf1_write_config32(dev, 0x50, dword); + pci_write_config32(dev, 0x50, dword); - dword = pci_conf1_read_config32(dev, 0xf8); + dword = pci_read_config32(dev, 0xf8); dword |= 2; - pci_conf1_write_config32(dev, 0xf8, dword); + pci_write_config32(dev, 0xf8, dword); } struct device_operations mcp55_sata = { Modified: coreboot-v3/southbridge/nvidia/mcp55/usb2.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/usb2.c 2008-10-01 06:47:51 UTC (rev 876) +++ coreboot-v3/southbridge/nvidia/mcp55/usb2.c 2008-10-01 07:23:05 UTC (rev 877) @@ -41,9 +41,9 @@ static void usb2_init(struct device *dev) { u32 dword; - dword = pci_conf1_read_config32(dev, 0xf8); + dword = pci_read_config32(dev, 0xf8); dword |= 40; - pci_conf1_write_config32(dev, 0xf8, dword); + pci_write_config32(dev, 0xf8, dword); } static void usb2_set_resources(struct device *dev)

1 0

r876 - in coreboot-v3: device include/device mainboard/gigabyte/m57sli southbridge/nvidia/mcp55 superio/ite/it8716f
by svn＠coreboot.org Sept. 30, 2008

Sept. 30, 2008

Author: rminnich Date: 2008-10-01 08:47:51 +0200 (Wed, 01 Oct 2008) New Revision: 876 Added: coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h Modified: coreboot-v3/device/pnp_raw.c coreboot-v3/include/device/pnp.h coreboot-v3/mainboard/gigabyte/m57sli/Makefile coreboot-v3/mainboard/gigabyte/m57sli/initram.c coreboot-v3/mainboard/gigabyte/m57sli/stage1.c coreboot-v3/southbridge/nvidia/mcp55/stage1.c coreboot-v3/superio/ite/it8716f/it8716f.h Log: Bringing the m57sli to life. This includes changes to mcp55 and mainboard that we learned with the serengeti that we needed. New function in pnp that is for reading. new prototype in pnp.h. New constants for ite8716f. This board does not build yet; we are exercising code in k8 north that the serengeti did not enable. More tomorrow. Now that we have two boards under way we can hopefully see our way to getting more put in. The 690 is the obvious next choice. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/device/pnp_raw.c =================================================================== --- coreboot-v3/device/pnp_raw.c 2008-09-29 17:24:44 UTC (rev 875) +++ coreboot-v3/device/pnp_raw.c 2008-10-01 06:47:51 UTC (rev 876) @@ -52,7 +52,8 @@ * * This is done by writing the register number to the port, and the value * into port + 1. This code assumes that the data port is always the - * config-port plus 1, but luckily this is true for pretty much all devices. + * config-port plus 1, but luckily this is true for pretty much all devices, since + * it is part of the standard. * * @param port The device I/O port. * @param reg The register number. @@ -65,6 +66,24 @@ } /** + * Read an 8-bit pnp config value + * + * This is done by writing the register number to the port, and the value + * into port + 1. This code assumes that the data port is always the + * config-port plus 1, but luckily this is true for pretty much all devices, since + * it is part of the standard. + * + * @param port The device I/O port. + * @param reg The register number. + * @returns value of the register + */ +u8 rawpnp_read_config(u16 port, u8 reg) +{ + outb(reg, port); + return inb(port + 1); +} + +/** * Select a logical device. * * PNP has up to 16 logical devices. They are selected by writing the Modified: coreboot-v3/include/device/pnp.h =================================================================== --- coreboot-v3/include/device/pnp.h 2008-09-29 17:24:44 UTC (rev 875) +++ coreboot-v3/include/device/pnp.h 2008-10-01 06:47:51 UTC (rev 876) @@ -27,6 +27,7 @@ void rawpnp_enter_ext_func_mode(u16 port); void rawpnp_exit_ext_func_mode(u16 port); void rawpnp_write_config(u16 port, u8 reg, u8 value); +u8 rawpnp_read_config(u16 port, u8 reg); void rawpnp_set_logical_device(u16 port, u8 ldn); void rawpnp_set_enable(u16 port, int enable); void rawpnp_set_iobase(u16 port, u8 index, u16 iobase); Modified: coreboot-v3/mainboard/gigabyte/m57sli/Makefile =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-09-29 17:24:44 UTC (rev 875) +++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-10-01 06:47:51 UTC (rev 876) @@ -19,17 +19,25 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ +STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \ + $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ $(src)/mainboard/$(MAINBOARDDIR)/option_table.c \ + $(src)/arch/x86/stage1_mtrr.c \ + $(src)/arch/x86/amd/model_fxx/dualcore_id.c \ + $(src)/arch/x86/amd/model_fxx/stage1.c \ $(src)/southbridge/nvidia/mcp55/stage1_smbus.c \ $(src)/northbridge/amd/k8/coherent_ht.c \ $(src)/northbridge/amd/k8/incoherent_ht.c \ - $(src)/lib/clog2.c + $(src)/northbridge/amd/k8/libstage1.c \ INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/k8/raminit.c \ $(src)/northbridge/amd/k8/dqs.c \ + $(src)/northbridge/amd/k8/reset_test.c \ $(src)/southbridge/nvidia/mcp55/stage1_smbus.c \ + $(src)/arch/x86/amd/model_fxx/dualcore.c \ + $(src)/arch/x86/amd/model_fxx/fidvid.c \ + $(src)/arch/x86/amd/model_fxx/init_cpus.c \ $(src)/lib/clog2.c Modified: coreboot-v3/mainboard/gigabyte/m57sli/initram.c =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/initram.c 2008-09-29 17:24:44 UTC (rev 875) +++ coreboot-v3/mainboard/gigabyte/m57sli/initram.c 2008-10-01 06:47:51 UTC (rev 876) @@ -20,7 +20,7 @@ */ #define _MAINOBJECT - +#include <mainboard.h> #include <types.h> #include <lib.h> #include <console.h> Added: coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h (rev 0) +++ coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h 2008-10-01 06:47:51 UTC (rev 876) @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * Constants that are mainboard-defined and do not belong in Kconfig. + * We really do not want this stuff to be visible -- it will make it appear that they can be + * changed, and they can not. + * + * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* we are unsure of these */ +#define DIMM_SOCKETS 4 +#define NODE_NUMS 16 +#define CPU_SOCKET_TYPE SOCKET_AM2 +/* these have been checked against v2 */ +#define MEM_TRAIN_SEQ 1 +#define HW_MEM_HOLE_SIZE_AUTO_INC 1 +#define HW_MEM_HOLE_SIZEK 0x100000 +#define HT_CHAIN_UNITID_BASE 0 +#define HT_CHAIN_END_UNITID_BASE 0x6 +#define SB_HT_CHAIN_ON_BUS0 2 +#define SB_HT_CHAIN_UNITID_OFFSET_ONLY 0 +#define ENABLE_APIC_EXT_ID 0 +#define LIFT_BSP_APIC_ID 1 +#define K8_SET_FIDVID 1 +/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, + * so may don't need to do twice */ +#define K8_SET_FIDVID_CORE0_ONLY 1 + +/* architecture stuff which ought to be set "somewhere" "SOMEHOW" */ +/* preferably by asking the CPU, not be a DEFINE! */ +#define CPU_ADDR_BITS 40 Modified: coreboot-v3/mainboard/gigabyte/m57sli/stage1.c =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/stage1.c 2008-09-29 17:24:44 UTC (rev 875) +++ coreboot-v3/mainboard/gigabyte/m57sli/stage1.c 2008-10-01 06:47:51 UTC (rev 876) @@ -19,22 +19,313 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <mainboard.h> #include <types.h> #include <lib.h> #include <console.h> #include <device/device.h> +#include <device/pnp.h> #include <cpu.h> -#include <amd/k8/k8.h> -#include <amd/k8/sysconf.h> #include <device/pci.h> #include <string.h> #include <msr.h> #include <io.h> #include <arch/x86/msr.h> +#include <superio/ite/it8716f/it8716f.h> +#include <amd/k8/k8.h> +#include <amd/k8/sysconf.h> +#define SUPERIO_DEV 0x2e +#define SERIAL_DEV IT8716F_SP1 +#define GPIO_DEV IT8716F_GPIO +#define SERIAL_IOBASE 0x3f8 +static const struct rmap register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCM(0, 0x18, 1, 0x44 , 0x0000f8f8, 0x00000000), + PCM(0, 0x18, 1, 0x4C , 0x0000f8f8, 0x00000001), + PCM(0, 0x18, 1, 0x54 , 0x0000f8f8, 0x00000002), + PCM(0, 0x18, 1, 0x5C , 0x0000f8f8, 0x00000003), + PCM(0, 0x18, 1, 0x64 , 0x0000f8f8, 0x00000004), + PCM(0, 0x18, 1, 0x6C , 0x0000f8f8, 0x00000005), + PCM(0, 0x18, 1, 0x74 , 0x0000f8f8, 0x00000006), + PCM(0, 0x18, 1, 0x7C , 0x0000f8f8, 0x00000007), + + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCM(0, 0x18, 1, 0x40 , 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x48 , 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x50 , 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x58 , 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x60 , 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x68 , 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x70 , 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x78 , 0x0000f8fc, 0x00000000), + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCM(0, 0x18, 1, 0x84 , 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0x8C , 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0x94 , 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0x9C , 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0xA4 , 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0xAC , 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0xB4 , 0x00000048, 0x00000000), +// PCM(0, 0x18, 1, 0xBC , 0x00000048, 0x00ffff00), + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCM(0, 0x18, 1, 0x80 , 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0x88 , 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0x90 , 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0x98 , 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0xA0 , 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0xA8 , 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0xB0 , 0x000000f0, 0x00000000), +// PCM(0, 0x18, 1, 0xB8 , 0x000000f0, 0x00fc0003), + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ +// PCM(0, 0x18, 1, 0xC4 , 0xFE000FC8, 0x00007000), + PCM(0, 0x18, 1, 0xCC , 0xFE000FC8, 0x00000000), + PCM(0, 0x18, 1, 0xD4 , 0xFE000FC8, 0x00000000), + PCM(0, 0x18, 1, 0xDC , 0xFE000FC8, 0x00000000), + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ +// PCM(0, 0x18, 1, 0xC0 , 0xFE000FCC, 0x00000033), + PCM(0, 0x18, 1, 0xC8 , 0xFE000FCC, 0x00000000), + PCM(0, 0x18, 1, 0xD0 , 0xFE000FCC, 0x00000000), + PCM(0, 0x18, 1, 0xD8 , 0xFE000FCC, 0x00000000), + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration region i + */ +// PCM(0, 0x18, 1, 0xE0 , 0x0000FC88, 0xff000003), /* link 0 of cpu 0 --> Nvidia MCP55 */ + PCM(0, 0x18, 1, 0xE4 , 0x0000FC88, 0x00000000), + PCM(0, 0x18, 1, 0xE8 , 0x0000FC88, 0x00000000), + PCM(0, 0x18, 1, 0xEC , 0x0000FC88, 0x00000000), + + }; + + void hardware_stage1(void) { + void it8716f_enable_serial(u8 dev, u8 serial, u16 iobase); + void enumerate_ht_chain(void); + int max; + u8 tmp; + + printk(BIOS_ERR, "Stage1: enable rom ...\n"); + max = ARRAY_SIZE(register_values); + rawpnp_enter_ext_func_mode(SUPERIO_DEV); + /* The following line will set CLKIN to 24 MHz, external */ + rawpnp_write_config(SUPERIO_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11); + tmp = rawpnp_read_config(SUPERIO_DEV, IT8716F_CONFIG_REG_SWSUSP); + /* Is serial flash enabled? Then enable writing to serial flash. */ + if (tmp & 0x0e) { + rawpnp_write_config(SUPERIO_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10); + rawpnp_set_logical_device(SUPERIO_DEV, GPIO_DEV); + /* Set Serial Flash interface to 0x0820 */ + rawpnp_write_config(SUPERIO_DEV, 0x64, 0x08); + rawpnp_write_config(SUPERIO_DEV, 0x65, 0x20); + /* We can get away with not resetting the logical device because + * it8716f_enable_serial will do that. + */ + } + it8716f_enable_serial(SUPERIO_DEV, SERIAL_DEV, SERIAL_IOBASE); + rawpnp_exit_ext_func_mode(SERIAL_DEV); + + setup_resource_map(register_values, max); + enumerate_ht_chain(); + printk(BIOS_ERR, "Done.\n"); post_code(POST_START_OF_MAIN); } Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-09-29 17:24:44 UTC (rev 875) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-10-01 06:47:51 UTC (rev 876) @@ -18,7 +18,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#include <mainboard.h> #include <console.h> #include <lib.h> #include <io.h> Modified: coreboot-v3/superio/ite/it8716f/it8716f.h =================================================================== --- coreboot-v3/superio/ite/it8716f/it8716f.h 2008-09-29 17:24:44 UTC (rev 875) +++ coreboot-v3/superio/ite/it8716f/it8716f.h 2008-10-01 06:47:51 UTC (rev 876) @@ -37,4 +37,12 @@ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */ +/* Global configuration registers. */ +#define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8716F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ +#define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ +#define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ + + #endif /* SUPERIO_ITE_IT8716F_IT8716F_H */

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coreboot gpxe
by ron minnich Sept. 30, 2008

Sept. 30, 2008

is this better or are we still unable to use gpxe? What does it require? Just the elf file creation? ron

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