September 2003 - coreboot - mail.coreboot.org

Level 2 cache activation code?
by Svante Signell Dec. 4, 2003

Dec. 4, 2003

Hello, I have recently upgraded my dual MSI-6120 from 2xCeleron (Mendocino) 300@450MHz with 2xMSI-6905 slot 370 to slot 1 adapters to one Celeron2 1.3GHz (Tualatin) using a Slot-T adapter card. The plan is to equip the mobo with 2xPIII or preferably 2xVIA C3 Nehemiah (when SMP capable). The problem is that the latest MSI BIOS (v2.0) for the mobo does not support Coppermine/Tualatin processors. The single GNU/Linux kernels boot without problems but _extremely_ slowly, at least with a speed reduction by a factor 10. hdparm -tT gives around 20/2 compared with 250/25 with the Mendocino CPU(s). For example uncompressing the kernel takes minute(s) compared to seconds. After some trials and web searching I suspect that the problem is with the level 2 cache not activated by the BIOS. I see the you have code in the linuxbios for activating caches. i) Does this code work for 440BX motherboards? ii) Is it possible to extract this code and try out after the kernel has booted (slowly), to verify my assumption? iii) Is there some other tool available for cache activation? iv) One interesting continuation would be to try to replace the MSI (AMI) BIOS with linuxbios, but as a first step I think this would be a little risky. Any ideas? Thanks, Svante

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LINUXBIOS can boot any variety OS
by mount me Dec. 1, 2003

Dec. 1, 2003

Hi linuxbiosians, Heard and Read that Windows 2000 can be booted using Linuxbios. Keeeeeeen and Interested in entering linuxbios. Could i get the list of OS's booted using LINUXBIOS and a brief explanation document along with it ? or links plz.... I am stilll looking for a motherboard in Chennai,INDIA Has anyone tried linuxbios in CHENNAI,INDIA ? need your support to start linuxbios with. Regards, karthik bala guru ________________________________________________________________________ Yahoo! India Promos: Win TVs, Bikes, DVD players & more! Go to http://in.promos.yahoo.com

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V2 VIA EPIA
by ron minnich Oct. 2, 2003

Oct. 2, 2003

OK, I've committed code that turns on shadow dram in F segment, so PIRQ will work; also committed what should be working SMBUS code in vt8231_early_smbus.c; now the fun begins. I could use advice on: - what SMBUS bytes we need to care about - what we should program the north with using those bytes. - how to do it. Which is to say, I think I know, but let's get this done in a speedy fashion. Momentum is on our side here. The EPIA will be a good demo platform. Why this sudden burst of EPIA work from me? Two reasons: - I want to encourage people to look at V2, so we need a demo system less complex than the K8 systems. - We are teaching a tutorial on linuxbios, bproc, etc. and will be doing it hands-on with a roomful of EPIAs, 2 or 3 per tutorial attendee. See: http://lacsi.lanl.gov/symposium/agenda.shtml Come if you want. You can see how we build clusters that boot in seconds. The software we're showing is the same stuff that is running on our 1024-node Pink cluster, and will run on our 1408-node K8 cluster. ron

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V2 and EPIA
by ron minnich Oct. 1, 2003

Oct. 1, 2003

OK, I just loaded from flash. Next step is to fix the PIRQ, then look at SPD and memory setup. The fix, for now, is this in auto.c static void enable_mainboard_devices(void) { device_t dev; /* dev 0 for southbridge */ dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); if (dev == PCI_DEV_INVALID) { die("Southbridge not found!!!\n"); } pci_write_config8(dev, 0x50, 7); pci_write_config8(dev, 0x51, 0xff); } This is a mainboard-specific setting for the VIA EPIA. and in main: static void main(void) { unsigned long x; /* init_timer();*/ outb(5, 0x80); enable_vt8231_serial(); enable_mainboard_devices(); uart_init(); console_init(); . . . So at the moment I am loading from FLASH! Ethernet is up, etc: Linux is happy. Just need PIRQ. ron

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A limit in V2 for PCI setup
by ron minnich Sept. 30, 2003

Sept. 30, 2003

In v2, it is pretty much impossible to do PCI setup BEFORE the PCI scan is called and device trees are built. Sometimes, however, you need to be able to work on PCI before the scan, e.g. to enable certain functions. I don't want this code in mainboard auto.c -- that's a bad way to go. See the below comment. /* we need to do things in this function so that PCI scan will find * them. One problem here is that we can't use ANY of the new device * stuff. This work here precedes all that. * Fundamental problem with linuxbios V2 architecture. * You can't do pci control in the C code without having done a PCI scan. * But in some cases you need to to pci control in the c code before doing * a PCI scan. But you can't use arch/romcc_io.h (the code you need) * because * that has functions with the same name but different type signatures * (e.g. device_t is a struct in C code, and is an unsigned long in * romcc code). * This needs to get fixed. We need low-level pci scans * in the C code. */ I think my fix is to make a copy of romcc_io.h, with different names and type signatures, for use by functions that need to work with PCI before the PCI scan has been done. comments welcome. I'll do this after lunch unless I hear strong counterarguments that will get me what I need. Thanks ron

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VIA EPIA SPD
by ron minnich Sept. 30, 2003

Sept. 30, 2003

I'm getting a bad feeling about SPD on EPIA. I have tried to scan SPD on both a normal bios and linuxbios, and I don't get any real data back. The SMBUS hardware all acts correctly, but on linuxbios every SPD byte reads back as 0, and on the normal bios every spd byte reads back as 3. now, on earlier VIA platforms I have had, SPD has only been connected to one slot, not all slots. I have some concern that SPD is not wired at all on EPIA. VIA had expressed concern to me about the many errors in low-end SEEROMs used on DRAM, and felt that SPD was not always a good way to go. Can anyone out there confirm or deny my speculation on SPD on EPIA? SPD scan code available on request. ron

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mptables and missing devices
by Stefan Reinauer Sept. 30, 2003

Sept. 30, 2003

Hi, is there a reason why the mptable creation uses dev_find_slot() to find the bridges instead of dev_find_device()? Since it does not even check whether the device it finds is the one it wants this sounds rather dangerous. Taking the PCI_CLASS field into regard, it should be possible to search for all bridges in the system and generate the necessary mptable entries from the information gathered from the devices (SUBORDINATE_BUS, SECONDARY_BUS) Am I digging in the dark? Stefan -- Architecture Team SuSE Linux AG

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Re: snapshots (fwd)
by ron minnich Sept. 30, 2003

Sept. 30, 2003

Thanks to Stefan Reinauer we now have a fix for the linuxbios sourceforge problems. You can now get snapshots at: http://snapshots.linuxbios.org/. Thanks to the OpenBIOS organization too for setting up this excellent facility. sourceforge may someday be fixed but we can't wait. Now all you VIA EPIA hackers: no excuses! there's you snapshot! ron

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Reboot after setting MTRRs
by Stefan Reinauer Sept. 30, 2003

Sept. 30, 2003

Hi, the latest AMD Solo builds reboot after setting variable MTRRs: mmio_base: 3670016KB totalram: 256M Initializing CPU #0 cpufixup RAM: 0x00040000 KB Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-88) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 256MB, type WB Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.4.0-Fallback Di Sep 30 12:19:45 CEST 2003 rebooting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: NSC 87360 This did not happen until somewhen after 1.1.4 What could cause this? It does not happen on other machines as far as I can tell... :-(((( Stefan -- Architecture Team SuSE Linux AG

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"best" supported hardware
by Zachary Miller Sept. 30, 2003

Sept. 30, 2003

hi all, i'm new to this list although i have some experience with linuxbios. about a year ago (somewhere in the 2.4.12 kernel era) i got everything working no problem on a matsonic/ms7308e motherboard, with a disk-on-chip filesystem and all. my boot time from power off is about 6 seconds until the mp3 player kicks in. i must say i'm very impressed! it seems that many more types of motherboards are now listed as stable since i last checked. sure, i could go and look up the specs of every single one, and i probably will, but i thought i would suggest putting some basic specs for each on the status page or perhaps an entry in the faq that answers my basic question: which of the "stable" motherboards supports the fastest processor? cheers, -zach

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