December 2003 - coreboot - mail.coreboot.org

FILO 0.4
by SONE Takeshi April 6, 2004

April 6, 2004

I just released FILO 0.4. http://te.to/~ts1/filo/ It can boot distro CDs if you give a proper command line. SuSE 8.2 LiveEval CD worked without a glitch, I enjoyed the KDE desktop, OpenOffice, etc, from the CD on an EPIA booted from LinuxBIOS. Also added support for booting from BIOS flash, to boot an alternative bootloader like Etherboot. PCI support in IDE driver is also added (or recovered), but the native PCI mode is not fully tested. I tried to configure EPIA (V1) code to use native mode, and the ports read something not 0xff, but the drive doesn't respond to soft reset. I don't know the bug is in FILO, LinuxBIOS, or the hardware. I'll work on config file support next time. Version 0.4 ts1 2003-10-15 * Support for ATAPI CD-ROM. * ISO-9660 filesystem is taken from a GRUB patch by Leonid Lisovskiy <lly(a)pisem.net>. The filesystem code was originally written by Kousuke Takai <tak(a)kmc.gr.jp> for GRUB/98 project. * Support for mounting boot disk image of El Torito bootable CD-ROM. ("hdc1" means the boot disk image of the CD-ROM at hdc.) * Support for memory as device, raw device as image, and user-specifiable device offset and length. (eg. boot: mem@0xfffd0000,0x10000) * PCI support in IDE driver. Now it by default uses PCI enumeration to find the PCI IDE controller, and can use native PCI mode if the controller is configured to this mode by BIOS. To disable this, turn off SUPPORT_PCI. * Fixed Linux loader to boot RedHat 9 kernel properly. -- Takeshi

8 23

NXTV's current linuxbios patch
by Dave Ashley March 8, 2004

March 8, 2004

I did a clean cvs checkout of freebios, then updated to 2003/7/5, and did a diff between what's in our cvs and that, and this is the result. It appears to be everything I touched. I got rid of all the CVS tree differences. Hope this is useful...I'm including a uuencoded gzip file. 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M.TLI5JQ`ZVS4A.I1]_&$DW$&-[N=9=G.>8M=(I:RL<?N:JQN65Q\$NCRD\S] M+<"KG'Q>NQ]Y^8LU9_"M<#O$JG#U*7S=_5:W"M?L2^[L\7E7^$_.X;/[T3:> MR1E=6#O=V^1C78@'V.D].U!GX5A=:GVPY;_3XW?VVILXSWS;[LA\=7QY]+?3 M<R+;E+=CE=_U_BS[8`XX%/'>A87JMO@_/'-+>0-LVHS3@FREJ@&PTV(`)Z32 MJ".=.71N;#-S8X><,*0ZDJ[X4>VV`TD#50=:P54HN.IMSAF'_GUG\3B\5_H6 M9.6'P;P?(OL#G['8X[/CNB5US30/<C)!NFCUDGRU7(YL<V%UA?B=H-I)MRN= M@,+^#X+JW1\VEU&U;&FHBOV9^L/N#ZO0U8#891#4C7N'E)WG21[_:TH^U?WL M_'9W&$#<JAEM9<(_-&1/*K-T[6!TBYK!8"CZ(-NCU\<U:!8BMUOF9K.]=J/; M52]Z>XU>9U8DNYJ-6E8D+WC).OQPKZ*<0O\56+4K7+*S,X=5]>\N:OW?A?UZ M.S6H%]O&CF9#3!N9_VR\+V-]^^X<%3.\/>38[ERM10C82]FM"*&*^-P;/C)` MMF2A+,ONOQ*WE5==6".Y><FHV-_`4,Q!YWR&&:E!>:@-D5I[>?SFX-<-%&,$ M#G8/3)!^3F[0$"?AKCR!8'.5@;2K`Y%^SR[>+^V@XV((I[&U6D-G^L_DD?8H M]<,-?/'.<T_UJ]XH2''[0(26YJD_8J?MCI39F#Z=]DZO]5"<F?1F)M);.(\M M?P2MWK(1F'GW%DR[MWC6+^K[G(\EGY^*+\9003U#'1V^5T?W%&`O[69'L]5[ M$*/'H7RQHE1U%DA5&U*U`HR=)X"Q^P0PND\`8^$8%1Y]#$P?G@"&.$R&(_0 M7#(a)RJ87ZGZ.#"_6&(@A8Z@"U/^1XT"_>X^:NKQ,ZNROI-FI6CGO@JY^R>46) MM4K@JKZ]-FARN/N%^,78/#9OSKMPUNRQ:Z5;9.Z.V&E];^\DT5%N>?G"S$^X M&(0-JQL&R>&IXA'8:JC0E$/-#DQ<B5X7`UL4,(T'O18.5/\-)\13F/6Q>D)Y M38,Y(5%-2QVKX"([7#^Y(V<N+XN!'@M(KL/;PV%,>_HZO,?_V7OES&VYSFCX M'KU`7X>)J_3HHXSI<^[1JYGVPR[-FP?`S(0O`0A5,>;K"^3,?'&W%#7F.R'D M)CU<0#PHY)((WO.8H6HO&2$9B8L/L$/V9I3=V:WWS0?P&*H/%S.9M%B)RZ3I M[&6)JQQW_VA(<L0]GW"_IP^XWZ[C%0$Y[]+%H/5TS&)[>C2W.!`,NS!K@!?X M]A!U(a)_.C4]E%BP-S^")J!;I@PX`ZC$?J_"HD+H"[<QY/<O4S?<JS#_%@1?9` M#@BG?L[ECK+!,N8H6WXF;SP0T,(;.7UX7Y@OO(X>PQ85`(8KB-CR_\4DIHCT MK*E>Q<.TCZ*:/Q=X]->;N`AQ(MU/WQPF(UPNR[U4J#6=).GVP<LW[V@<@V'! F=X9L$\/9BSW`179@2UN#O^)\48?NI2$>;/<'#>;?4(N]P*"&```` ` end

2 1

Re: IDE on s2885 and LinuxBIOS -- FILO
by YhLu Feb. 10, 2004

Feb. 10, 2004

Ron, I have checked pci.c in fifo. It need to be changes as follow. It seems otherwise it can not scan the peer root bus. Maybe someone need to make it can handle peer root bus refer to the code in Linux kernel or Etherboot. Regards YH. void pci_init(void) { /* Count devices */ dev_list = 0; debug("Scanning PCI: "); pci_scan_bus(0); pci_scan_bus(1); // For Tyan s2880,s2881,s2882,s2885,s4880 // pci_scan_bus(3); //For Tyan s2885 debug("found %d devices\n", n_devs); /* Make the list */ dev_list = malloc(n_devs * sizeof(struct pci_dev)); n_devs = 0; pci_scan_bus(0); pci_scan_bus(1); // For Tyan s2880,s2881,s2882,s2885,s4880 // pci_scan_bus(3); //For Tyan s2885 #if DEBUG { int i; for (i = 0; i < n_devs; i++) { debug("%02x:%02x.%x %04x:%04x %04x %02x\n", PCI_BUS(dev_list[i].addr), PCI_DEV(dev_list[i].addr), PCI_FN(dev_list[i].addr), dev_list[i].vendor, dev_list[i].device, dev_list[i].devclass, dev_list[i].prog_if); } } #endif } -----邮件原件----- 发件人: YhLu 发送时间: 2003年12月10日 9:27 收件人: 'ron minnich' 抄送: Hendricks David W. 主题: Re: IDE on s2885 and LinuxBIOS Is it working with On current tree or using old source tree to make sure all 8111/8131 on bus 0? Yinghai Lu -----邮件原件----- 发件人: ron minnich [mailto:rminnich@lanl.gov] 发送时间: 2003年12月10日 7:25 收件人: YhLu 抄送: Hendricks David W. 主题: Re: IDE on s2885 and LinuxBIOS I wonder what differes from HDAMA to s2885? filo works fine on HDAMA ron

5 8

How to use Filo as a payload ?
by Peter Fox Jan. 23, 2004

Jan. 23, 2004

I'm trying to get the STPC Elite development board to use linuxbios with Filo, but after elfboot announces itself the board reboots: ---------------------- ..... Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 LinuxBIOS-1.0.0 Thu Nov 6 16:13:37 GMT 2003 starting... Copying LinuxBIOS to ram. .... ------------------------ My config file looks like this: target /home/fox/build/freebios1/stpc mainboard stpc/elite biosbase 0xffff0000 option CONFIG_COMPRESS=0 option SERIAL_CONSOLE=1 option TTYS0_BAUD=38400 option DEFAULT_CONSOLE_LOGLEVEL=9 option DEBUG=1 # option ROM_IMAGE_SIZE=131072 option ROM_SIZE=131072 option USE_ELF_BOOT=1 option PAYLOAD_SIZE=65536 payload /home/fox/build/filo-0.4/filo.elf Any ideas as to what I've missed ? -- Peter Fox <peter.fox(a)aeroflex.com> Aeroflex Test Solutions Principal Design Engineer Stevenage Any opinions expressed above are http://www.aeroflex.com/ not necessarily those of Aeroflex. Tel: + 44 (0) 1438 742200

3 13

IDEA: Linux kernel and pcbios compatibility...
by ebiederman＠lnxi.com Jan. 4, 2004

Jan. 4, 2004

Brainstorming earlier today I think I have found a way to use an linux kernel for the boot loader and to implement pcbios compatibility without too much cost. The idea is to use a uclinux kernel. And implement a ``user space'' aplication that is a user space shim that makes kernel calls. There are a few nasty details to work out like how to handle services that are expected to work in vm86 mode. But I'm not certain I care. Other thoughts? After I come back from my christmas vacation I am going to have to try it and see how will it will actually work. Eric

10 39

ide emulation based on network block device for arbitrary OSes?
by Adam Megacz Dec. 31, 2003

Dec. 31, 2003

I've heard that you can use LinuxBIOS to bootload other operating systems (like Windows, etc). Is it possible for LinuxBIOS to boot the device and install a block of code in memory that handles BIOS disk requests using some sort of network block device protocol? Failing this, does anybody know of a cheap hardware device that would do the same thing? Thanks. - a -- "If Darl McBride [the CEO of SCO, who claims the GPL 'destroys intellectual property'] was in charge, he'd probably make marriage unconstitutional too, since clearly it de-emphasizes the commercial nature of normal human interaction, and probably is a major impediment to the commercial growth of prostitution" -- Linus Torvalds

2 1

Filesystem for DOCM?
by Devi Priya Dec. 31, 2003

Dec. 31, 2003

Hi, Which file system should I use for diskonchip millennium while using with linuxbios? _________________________________________________________________ Free transactions in any ATM across India. http://server1.msn.co.in/msnleads/suvidha/dec03.asp?type=hottag Click here.

3 2

Re: Flash mapped to lower address?
by Bari Ari Dec. 26, 2003

Dec. 26, 2003

Devi Priya wrote: > I like to use either Flash memory or DOC and not both. I want to know if > I have my Flash memory or DOC mapped to lower address what modification > should I do to the linuxbios coding. like regarding setiing the RAMBASE, > ROMBASE........... > The power-up reset address for the Geode is FFFFFFF0h, you can't change that. Your only strapping options are: (1) Enable either an 8 bit or 16 bit boot ROM access (2) Enable either a LPC or ISA boot ROM access. -Bari > Regards, > Priya. > > >> From: Bari Ari <bari(a)onelabs.com> >> To: Devi Priya <ijpriya(a)hotmail.com> >> CC: linuxbios(a)clustermatic.org >> Subject: Re: Flash mapped to lower address? >> Date: Fri, 26 Dec 2003 20:45:41 -0600 >> >> >> >> Devi Priya wrote: >> >>> If i have my Flash memory mapped to the lower address >>> (0x0000-0x3FFFFF), then what modification should be made to linux bios? >> >> >> Are you using NAND Flash or DOC or both ? Are you trying to boot from >> the DOC? >> >> You may also want to look at the >> >> Geode™ IA on a Chip Devices: Booting from the M-Systems DiskOnChip >> Millennium Application Note >> >> http://www.m-sys.com/files/documentation/doc/App_Note_047_Des_DOC_FD_Boot_R… >> >> >> http://www.m-sys.com/files/documentation/doc/App_Note_031_PC_Rev_2.2.pdf >> >> -Bari >> >> >> >> _______________________________________________ >> Linuxbios mailing list >> Linuxbios(a)clustermatic.org >> http://www.clustermatic.org/mailman/listinfo/linuxbios > > > _________________________________________________________________ > NRI’s, Free Money transfer to India. > http://server1.msn.co.in/msnleads/citibankrca/citibankrca2.asp?type=hottag > Click here. > > >

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Flash mapped to lower address?
by Devi Priya Dec. 26, 2003

Dec. 26, 2003

If i have my Flash memory mapped to the lower address (0x0000-0x3FFFFF), then what modification should be made to linux bios? _________________________________________________________________ NRIs, Free Money transfer to India. http://server1.msn.co.in/msnleads/citibankrca/citibankrca2.asp?type=hottag Click here.

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Re: Flash mapped to lower address?
by Devi Priya Dec. 26, 2003

Dec. 26, 2003

Hi, >From the AMD data sheet: The Core Logic module positively decodes memory addresses 000F0000h-000FFFFFh (64 KB) and FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory cycles cause the Core Logic module to claim the cycle, and generate an ISA bus memory cycle with ROMCS# asserted. The Core Logic module can also be configured to respond to memory addresses FF000000h-FFFFFFFFh (16 MB) and 000E0000h-000FFFFFh (128 KB). 8- or 16-bit wide ROM is supported. BOOT16 strap determines the width after reset. MCR[14,3] (Offset 34h) in the General Configuration Block allows program control of the width. Flash ROM is supported in the Core Logic module by enabling the ROMCS# signal on write accesses to the ROM region. Normally only read cycles are passed to the ISA bus, and the ROMCS# signal is suppressed for write cycles. When the ROM Write Enable bit (F0 Index 52h[1]) is set, a write access to the ROM address region causes a write cycle to occur with MEMW#,WR# and ROMCS# asserted. The Boot Flash supported by the SC1200/SC1201 can be up to 16 MB. It is supported with the ROMCS# signal. As the corelogic module positively decodes the memory addresses 000F0000h-000FFFFFh (64 KB) and FFFC0000h-FFFFFFFFh (256 KB) at reset, I can have my Flash memory mapped to the lower address. Is it? >From: ron minnich <rminnich(a)lanl.gov> >To: Devi Priya <ijpriya(a)hotmail.com> >CC: linuxbios(a)clustermatic.org >Subject: Re: Flash mapped to lower address? >Date: Wed, 24 Dec 2003 18:39:20 -0700 (MST) > >On Tue, 23 Dec 2003, Devi Priya wrote: > > > If i have my Flash memory mapped to the lower address (0x0000-0x3FFFFF), > > then what modification should be made to linux bios? > >why on earth would you map flash to this address? it makes no sense to me. > >ron > >_______________________________________________ >Linuxbios mailing list >Linuxbios(a)clustermatic.org >http://www.clustermatic.org/mailman/listinfo/linuxbios _________________________________________________________________ NRIs, Free Money transfer to India. http://server1.msn.co.in/msnleads/citibankrca/citibankrca2.asp?type=hottag Click here.

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EPIA + non-standard flash chip
by Surjan Singh Dec. 24, 2003

Dec. 24, 2003

Hello, Wondering if anyone can help me with this one: I have a basic EPIA board (http://www.viavpsd.com/product/epia_mini_itx_spec.jsp?motherboardId=21) , the one with the 533MHz CPU. Anyway, I managed to find myself a PLCC Flash chip which seems like it will work (http://www.farnell.com/datasheets/23247.pdf) but when I run the flash program it complains that it does not recognise the chip. So, I added an entry for the chip in "flash.h" hoping I could use the regular routines for the EPIA, but it says it cannot unlock the chip. Can someone help me with this one pls? Could someone supply a diff, using the above datasheet, that would enable me to use the chip? Even some tips on what I'd need to do if I had to write the code would be appreciated. Thanks, Surj

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Re: Success stories
by Hendricks David W. Dec. 24, 2003

Dec. 24, 2003

Can you be more specific about your mainboard? Chaintech makes dozens of models. Copy / paste your lspci output if possible.

2 1

Success stories
by Kees Meijs Dec. 21, 2003

Dec. 21, 2003

Hello there, I'd like to flash my ChainTech motherboard with a Linux kernel or just grub. Did anyone did this before? And if so, how did you do it? Cheers, Kees P.S. It's a pity the documentation on the web is very sparse, maybe I can write some?

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Re: EPIA-M serial port 1/2 baud rate insanity
by Dave Ashley Dec. 19, 2003

Dec. 19, 2003

Andrew Ip wrote: >Have you checked out the clock connected to LPC? On W311, FS2 can be >set to 24 or 48 MHz. It could be the problem, since I have similar problem >with USB on a custom cle266 board. FYI, it can be programmed thru smb. >Here is from we have done to program the USB clock. >... >You may want to put similar code in serial init. Hope this help. I tried this and...it worked! My simple test program is below. Linuxbios puts the smb stuff at 0xf00 and it is already enabled (at least in my patch). So all I had to do was do the outb's to get it to work. Thanks *very* much. Note to Ron: Let me know if you want the epia-m, I'll still send one off if you want it. I've got a spare 10000 (1 gig) that you can have. Note I don't read email sent to the address I'm posting from...best send to dash(a)xdr.com to get to me. #include <stdio.h> #include <string.h> #include <unistd.h> #include <sys/io.h> #include <stdlib.h> #define SMB_STATUS (base + 0) #define SMB_CONTROL (base + 2) #define SMB_COMMAND (base + 3) #define SMB_ADDRESS (base + 4) #define SMB_DATA (base + 5) #define I2C_TRANS_CMD 0x40 #define CLOCK_SLAVE_ADDRESS 0x69 int main(int argc, char **argv) { int res; int base=0xf00; res=iopl(3); if(res) { perror("iopl"); exit(-1); } outb( 0xff, SMB_STATUS ); // USB out 48MHz outb( 0x7f, SMB_DATA ); outb( 0x83, SMB_COMMAND ); outb( (CLOCK_SLAVE_ADDRESS<<1), SMB_ADDRESS ); outb( 0x8|I2C_TRANS_CMD, SMB_CONTROL ); while( inb(SMB_STATUS) & 0x01 ); } -Dave

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Intel 82845G/GL
by Brian Thomason Dec. 19, 2003

Dec. 19, 2003

I scanned the entire mailing and website for LinuxBIOS and didn't see a single reference to the Intel 82845G/GL. Is this configuration supported? If not, would it be "easy" to add support for it? I'm very new to LinuxBIOS (just discovered the website a month or so ago and still don't fully grok it) but have two machines with this chipset I'd like to get setup as sample boxes to show my boss the increase in boot time. (From what I hear, it speeds up boot time CONSIDERABLY) Thanks in advance for your time, Brian Thomason Lindows.com Developer Relations

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Re: EPIA-M serial port 1/2 baud rate insanity
by Dave Ashley Dec. 18, 2003

Dec. 18, 2003

Here is what I did to integrate this into linuxbios. I created the following file src/mainboard/via/epia-m/smbusenable.inc /* Useful macros PCIBUS, and SMBUS functions for getting DRAM going. */ /* courtesy Eric Biederman of linuxnetworx.com */ #define CS_WRITE_BYTE(addr, byte) \ movl $addr, %eax ; \ movl $byte, %edx ; \ PCI_WRITE_CONFIG_BYTE #define CS_WRITE_WORD(addr, word) \ movl $addr, %eax ; \ movl $word, %ecx ; \ PCI_WRITE_CONFIG_WORD #define CS_WRITE_LONG(addr, dword) \ movl $addr, %eax ; \ movl $dword, %ecx ; \ PCI_WRITE_CONFIG_DWORD #define DEVFN(device, function) (((device) << 3) + (function)) #ifndef CONFIG_ADDR #define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where)) #endif /* generic SMB routines that work for many systems. The only one that might * not work is the enable_smbus. * you have to define PM_FUNCTION for this to work. */#define SMBUS_IO_BASE 0xf00 #define SMBHSTSTAT 0 #define SMBHSTCTL 2 #define SMBHSTCMD 3 #define SMBHSTADD 4 #define SMBHSTDAT0 5 #define SMBHSTDAT1 6 #define SMBBLKDAT 7 /* (DA) Lines added to get this to compile */ #define PM_DEVFN CONFIG_ADDR(0,0x11*8,0) #define DRAM_CONFIG_PORT 0x5a #define SMBUS_MEM_DEVICE_0 0x50 #define LAST_SMBUS_MEM_DEVICE SMBUS_MEM_DEVICE_0 #define REGISTERED_DRAM_REGISTER $0x69 #define REGISTERED_DRAM $0x2d #define NONREGISTERED_DRAM $0 /* put the SMBUS at port 0xf00 + enable*/ CS_WRITE_WORD(PM_DEVFN+ 0xd0, SMBUS_IO_BASE|1) /* iobase addr */ CS_WRITE_BYTE(PM_DEVFN + 0xd2, (0x4 << 1) | 1) /* smbus enable */ CS_WRITE_WORD(PM_DEVFN + 0x4, 1) /* iospace enable */ /* The VT1211 serial port needs 48 mhz clock, on power up it is getting only 24 mhz, there is some mysterious device on the smbus that can fix this...this code below does it. */ #define MYOUTB(val, port) movb val, %al; movw port, %dx ; outb %al, %dx #define I2C_TRANS_CMD 0x40 #define CLOCK_SLAVE_ADDRESS 0x69 MYOUTB( $0xff, $(SMBUS_IO_BASE+SMBHSTSTAT)) MYOUTB( $0x7f, $(SMBUS_IO_BASE+SMBHSTDAT0)) MYOUTB( $0x83, $(SMBUS_IO_BASE+SMBHSTCMD)) MYOUTB( $(CLOCK_SLAVE_ADDRESS<<1), $(SMBUS_IO_BASE+SMBHSTADD)) MYOUTB( $(8 | I2C_TRANS_CMD), $(SMBUS_IO_BASE+SMBHSTCTL)) movw $(SMBUS_IO_BASE+SMBHSTSTAT), %dx smbwait1: inb %dx, %al and $1, %al jnz smbwait1 ----- Now in src/mainboard/via/epia-m/Config we need to include the above file, so it ends up looking like this: mainboardinit mainboard/via/epia-m/smbusenable.inc mainboardinit superio/via/vt1211/setup_serial.inc mainboardinit pc80/serial.inc -Dave

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Re: sc1200?
by Devi Priya Dec. 18, 2003

Dec. 18, 2003

Thanks for ur suggestion. My flash is 4 MB. My processor can address up to 4 GB physical address space. That means after power-on, in shematic should I map the flash memory like 0xFFC00000-0xFFFFFFFF and 0x00000000-0x003FFFFF? 0r in upper address, is it enough to map the 256KB region to the Flash ie 0xFFFC0000-0xFFFFFFFF? and the lower address to 0x00000000-0x003FFFFF >From: ron minnich <rminnich(a)lanl.gov> >To: Devi Priya <ijpriya(a)hotmail.com> >CC: linuxbios(a)clustermatic.org >Subject: Re: sc1200? >Date: Wed, 17 Dec 2003 22:07:00 -0700 (MST) > >at power-on, on all chipsets for PCs I have used, FLASH is mapped at BOTH >0xffffff0 and 0xffff0. > >ron > >_______________________________________________ >Linuxbios mailing list >Linuxbios(a)clustermatic.org >http://www.clustermatic.org/mailman/listinfo/linuxbios _________________________________________________________________ Dont miss out on jobs that are not advertised. http://go.msnserver.com/IN/38902.asp Post your CV on naukri.com today.

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sc1200?
by Devi Priya Dec. 18, 2003

Dec. 18, 2003

Hi, After power-on, the x86 processor is placed in real mode. That means the CPU looks for the instruction at the address 0xffff0. Is it correct? In SC1200 datasheet, it is given that, "Approximately 150 to 250 external clock cycles after RESET is deasserted, the processor begins executing instructions at the top of physical memory (address location FFFFFFF0h). The actual number of clock cycles depends on the clock scaling in use. Also, before execution begins, an additional 220 clock cycles are needed when self-test is requested. Typically, an intersegment jump is placed at FFFFFFF0h. This instruction will force the processor to begin execution in the lowest 1 MB of address space." In real mode, the CPU can address only 1 MB. Then how this address could be addressed by the CPU? To which address does my Flash memory gets mapped to at power-on? _________________________________________________________________ Dont miss out on jobs that are not advertised. http://go.msnserver.com/IN/38902.asp Post your CV on naukri.com today.

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EPIA-M serial port 1/2 baud rate insanity
by Dave Ashley Dec. 17, 2003

Dec. 17, 2003

I am at my wits end regarding how to get the serial ports on the epia-m to run at full 115,200 baud rate. Here is a summary of what is known: 1) The serial ports are driven by the VT1211 superio chip. 2) Under AWARD bios the serial ports are capable of 115,200 operation. 3) Under linuxbios they can only run at 57,600 max. 4) Booting up with AWARD then soft reset (or hit reset button on motherboard) into linuxbios still maintains 115,200 baud 5) Hard reset (power off then on) into linuxbios reduces maximum baud rate to 57,600. 6) All registers of the VT1211 are identical after linuxbios bootup, whether from award -> softreset -> linuxbios bootup or hardreset -> linuxbios bootup. I am speaking of all registers of all logical devices of the VT1211, including all the global registers. I wrote a program to dump everything then diff'd the two outputs, they're identical. I have repeatedly tried asking VIA for help, in various different ways. The VT1211 datasheet and the VT1211 bios porting guide have not resolved the issue. VIA has proven incapable of addressing the problem. I have one last idea. There is an emulator to test VGA bios's, I was messing with it a few months back. Is there an emulator for the full BIOS? I'd like to be able to watch all io port accesses of the award bios, maybe I can trap when it goes to write to the 0x2e + 0x2f io ports to configure the vt1211 serial ports, then look for something near there that might be related. The idea would be to figure out what magical thing the AWARD bios is doing to initialize the serial port. Failing that is there any way to disassemble a BIOS image? Any ideas welcome. BTW if anyone has figured out how to fix the problem, please just f*cking out with it, I think I've been very generous in the past with enhancements and turnabout is fair play. Thanks-- Dave

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Re: EPIA-M serial port 1/2 baud rate insanity
by Dave Ashley Dec. 17, 2003

Dec. 17, 2003

>I don't know what the problem is, I don't have an EPIA-M yet. >... >Are your sure the clock source for the superio or uart is the same for >linuxbios and award? >The "emulator for VGA bios" will actually run anything... If sending you an epia-m would mean you'd begin looking at it I'll get you one. Let me know. I'm not sure of the clock source, VIA hasn't provided a schematic for the board. The datasheet indicates 2 clock sources, one is for the LPC interface and the other is for the main clock. LPC is the 33 mhz pci clock. The other clock is 48 mhz. I had a scope on the chip and as near as I can tell the 48 mhz clock was in fact 48 mhz. I didn't look at the 33 mhz clock at all. -Dave

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EPIA-M + second serial port enabler
by Dave Ashley Dec. 15, 2003

Dec. 15, 2003

In a previous email message http://www.clustermatic.org/pipermail/linuxbios/2003-November/005891.html I wrote In V1 the file to modify is src/superio/via/vt1211/setup_serial.inc That code sets up ttyS0 which is the VT1211's logical device 2. You want to add some similiar code for logical device 3 to get ttyS1 working. Assuming you want it to be at 2f8 you'd merge in these lines: OUTPNPADDR($7) OUTPNPDATA($3) /* set the enable in reg. 0x30 */ OUTPNPADDR($0x30) OUTPNPDATA($0x1) /* Serial Port 2 Base Address (BEh) */ OUTPNPADDR($0x60) OUTPNPDATA($0xbe) /* Serial Port 2 IRQ (03h) */ OUTPNPADDR($0x70) OUTPNPDATA($0x3) /* Serial Port 2 Control */ OUTPNPADDR($0xf0) OUTPNPDATA($0x2) ...then do the turn off pnp /* turn off PnP */ OUTPNPADDR($0xaa) ...then duplicate the serial setup except the address goes from 3f8 -> 2f8 There is a piece missing. I had to enable the second serial port on the VT1211 and although linux recognized it, there was no serial activity on the lines. These lines need to be added during the vt1211 configuration: /* Allow serial port 2 (ldn 3) pins to come out */ OUTPNPADDR($0x27) OUTPNPDATA($00) This has to be before the $0xaa write to turn off configuration mode. The default value on powerup for this register on the vt1211 is 0xff. There are multi purpose pins on the chip and this connects them to the second serial port. -Dave

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Re: VIA EPIA mini-ITX mainboards
by Hendricks David W. Dec. 15, 2003

Dec. 15, 2003

Yeah, Slasdot obviously is not intended to be used as a message forum for lingering discussion. Ron has a working image that was used for what I gather is a similar mainboard. Output from lspci would also be helpful so that we can make sure the hardware on your board is the same as the hardware on ours (Whatever came in the ITuner Minibox M-100's). P.S. I cc'd this e-mail to the mailing list ( http://www.clustermatic.org/pipermail/linuxbios/2003-December/ ) since the EPIA is a rather popular platform and others might be able to offer help in this matter. Etherboot can boot a kernel over a LAN, and IDE disk, floppy, and probably some others too. Are you using an ethernet bridge like a Linksys WET11 or an add-in PCI or USB wireless device? On Thu, 11 Dec 2003, Sonam Chauhan wrote: > [ Re: http://bsd.slashdot.org/comments.pl?sid=87041&cid=7567224 ] > > Hi - Thanks for offering to help with your experience flashing VIA EPIA > mini-ITX mainboards. Sorry, I didn't see your reply until recently. :) > > You wrote: > > If you're using the 500MHz/800MHz normal SDRAM version, I'll send > > you a ROM I used with the old freebios tree and an Etherboot > > payload. > That'd be great! Yes, I have the 533 MHz fanless EPIA ESP 5000 board > with PC 133 SDRAM. > > By etherboot, do you mean that the board can boot remotely from LAN, > using the onboard ethernet port? If so, that's excellent! Out of > curiosity, do you see any problem with the Mini-ITX board etherbooting > via a 802.11 wireless access point it is connected to with it's ethernet > interface? > > With best regards, > Sonam Chauhan >

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Re: serial programming
by Parit Wattanasin Dec. 14, 2003

Dec. 14, 2003

--- linuxbios-request(a)clustermatic.org wrote: > Send Linuxbios mailing list submissions to > linuxbios(a)clustermatic.org > > To subscribe or unsubscribe via the World Wide Web, > visit > > http://www.clustermatic.org/mailman/listinfo/linuxbios > or, via email, send a message with subject or body > 'help' to > linuxbios-request(a)clustermatic.org > > You can reach the person managing the list at > linuxbios-admin(a)clustermatic.org > > When replying, please edit your Subject line so it > is more specific > than "Re: Contents of Linuxbios digest..." > > > Today's Topics: > > 1. serial programming (Parit Wattanasin) > 2. Re: serial programming (Peter Stuge) > 3. Re: serial programming (ron minnich) > 4. Re: serial programming (Peter Stuge) > > --__--__-- > > Message: 1 > Date: Sat, 13 Dec 2003 20:39:44 -0800 (PST) > From: Parit Wattanasin <parit_top(a)yahoo.com> > Subject: serial programming > To: linuxbios(a)clustermatic.org > > hi, I'm new for LinuxBIOS. I have problem about my > mainboard(VIA-EPIA) Now I'm use LinuxBIOS but I > want > to customized it to chang payload from etherboot > with > my program about serial port(now this mainboard use > serial console) how can I'change it(my program use > assembly). Thank you for answer > > __________________________________ > Do you Yahoo!? > New Yahoo! Photos - easier uploading and sharing. > http://photos.yahoo.com/ > > --__--__-- > > Message: 2 > Date: Sun, 14 Dec 2003 06:14:45 +0100 > From: Peter Stuge <stuge-linuxbios(a)cdy.org> > To: linuxbios(a)clustermatic.org > Subject: Re: serial programming > > On Sat, Dec 13, 2003 at 08:39:44PM -0800, Parit > Wattanasin wrote: > > hi, I'm new for LinuxBIOS. I have problem about my > > mainboard(VIA-EPIA) Now I'm use LinuxBIOS but I > want > > to customized it to chang payload from etherboot > with > > my program about serial port(now this mainboard > use > > serial console) how can I'change it(my program use > > assembly). Thank you for answer > > The payload can be exchanged from Etherboot to > another self-contained ELF > file simply by recompiling LinuxBIOS. > > I'm not quite sure about the status of the EPIA port > in the version 2 CVS > tree, but it's there and there's been work put into > it so it should probably > compile and work just fine. > > The best bet is to check the mailing list archives > for information, and then > grab the CVS code, or a snapshot, and make your own > build. > > While making your own build you can also take out > all serial port activity > not needed for your application, of course. > > > //Peter > > --__--__-- > > Message: 3 > Date: Sat, 13 Dec 2003 22:52:20 -0700 (MST) > From: ron minnich <rminnich(a)lanl.gov> > To: Peter Stuge <stuge-linuxbios(a)cdy.org> > cc: linuxbios(a)clustermatic.org > Subject: Re: serial programming > > On Sun, 14 Dec 2003, Peter Stuge wrote: > > > I'm not quite sure about the status of the EPIA > port in the version 2 CVS > > tree, but it's there and there's been work put > into it so it should probably > > compile and work just fine. > > EPIA is fine in V2, not perfect but FAR better than > EPIA in v1. > > We want to clean up EPIA completely, then fix up > EPIA-M, but there have > been some distractions (SC '03). > > ron > > > --__--__-- > > Message: 4 > Date: Sun, 14 Dec 2003 08:37:08 +0100 > From: Peter Stuge <stuge-linuxbios(a)cdy.org> > To: linuxbios(a)clustermatic.org > Subject: Re: serial programming > > On Sat, Dec 13, 2003 at 10:52:20PM -0700, ron > minnich wrote: > > On Sun, 14 Dec 2003, Peter Stuge wrote: > > > > > I'm not quite sure about the status of the EPIA > port in the version 2 CVS > > > tree, but it's there and there's been work put > into it so it should probably > > > compile and work just fine. > > > > EPIA is fine in V2, not perfect but FAR better > than EPIA in v1. > > > > We want to clean up EPIA completely, then fix up > EPIA-M, but there have > > been some distractions (SC '03). > > Ah, yes, that's right. > > I can't wait until I actually have the time to sit > down and do something > with LinuxBIOS, last time was over two years ago, > there's been an amazing > evolution of the code. I can easily imagine running > LinuxBIOS 3 or 4 on > _MANY_ systems in another year or two. It seems > vendors (like Tyan) are > picking up too, which is great. Just don't take over > all of their competent > people over at LANL, at least not until there's > support for all of their > boards in the tree.. >:) > > Just a short note to celebrate your success. :) > > > //Peter > > > --__--__-- > > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios > > > End of Linuxbios Digest I'm assemble my serial program to elf-format and exchange for etherboot.It has error =LinuxBIOS-1.0.0 Wed Dec 3 11:26:55 ICT 2003 starting.. =Enabled first bank of RAM: 0x08000000 bytes =Copying LinuxBIOS to ram. =Jumping to LinuxBIOS. =POST: 0x39 =LinuxBIOS-1.0.0 Wed Dec 3 11:26:55 ICT 2003 booting... =POST: 0x40 =... =... =... =Copying IRQ routing tables to 0xf0000...done. =Verifing priq routing tables copy at 0xf0000...succeed =POST: 0x96 =Wrote linuxbios table at: 00000500 - 000006b0 =checksum 8255 = =Welcome to elfboot, the open sourced starter. =January 2002, Eric Biederman. =Version 1.2 = =POST: 0xf8 37:init_bytes() - zkernel_start:0xfff00000 =zkernel_mask:0x0000ffff =Found ELF candiate at offset 0 =New segment addr 0x8048000 size 0xa6 offset 0x0 =filesize 0xa6 =(cleaned up) New segment addr 0x8048000 size 0xa6 =offset 0x0 filesize 0xa6 =Cannot Load ELF Image =POST: 0xff= __________________________________ Do you Yahoo!? New Yahoo! Photos - easier uploading and sharing. http://photos.yahoo.com/

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serial programming
by Parit Wattanasin Dec. 14, 2003

Dec. 14, 2003

hi, I'm new for LinuxBIOS. I have problem about my mainboard(VIA-EPIA) Now I'm use LinuxBIOS but I want to customized it to chang payload from etherboot with my program about serial port(now this mainboard use serial console) how can I'change it(my program use assembly). Thank you for answer __________________________________ Do you Yahoo!? New Yahoo! Photos - easier uploading and sharing. http://photos.yahoo.com/

3 3

Re: Please help
by Devi Priya Dec. 10, 2003

Dec. 10, 2003

I am using SC1200. >From: ron minnich <rminnich(a)lanl.gov> >To: Devi Priya <ijpriya(a)hotmail.com> >CC: linuxbios(a)clustermatic.org >Subject: Re: Please help >Date: Wed, 10 Dec 2003 20:40:51 -0700 (MST) > >On Thu, 11 Dec 2003, Devi Priya wrote: > > > diskonchip millennium. If I have to use diskonchip millennium with > > linuxbios, to which physical address should the DOCM should be mapped in > > hardware ? Is any driver should be loaded before the OS gets loaded? I >have > > mapped in hardware 0xFFFFFFFF-0xFF800000. Is this correct? Does any > > remapping is to be done in hardware afer this? > > Which file system should I use? > >I would like to help but your questions indicate you are somewhat >unfamiliar with many things. Are you using some standard motherboard or >designing one? > >If you are not designing one, consider buying an existing DOC-based mobo >from cwlinux.com and learning from that. > >ron > _________________________________________________________________ Contact brides & grooms FREE! Only on www.shaadi.com. http://www.shaadi.com/ptnr.php?ptnr=hmltag Register now!

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Please help
by Devi Priya Dec. 10, 2003

Dec. 10, 2003

Hi, I like to have my linuxbios, linux OS, filesystem in the same diskonchip millennium. If I have to use diskonchip millennium with linuxbios, to which physical address should the DOCM should be mapped in hardware ? Is any driver should be loaded before the OS gets loaded? I have mapped in hardware 0xFFFFFFFF-0xFF800000. Is this correct? Does any remapping is to be done in hardware afer this? Which file system should I use? _________________________________________________________________ Download cool KHNH ringtones. Add style to your mobile. http://server1.msn.co.in/sp03/gprs/howcani_ring.asp Simply click here.

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Re: IDE on s2885 and LinuxBIOS -- FILO
by YhLu Dec. 10, 2003

Dec. 10, 2003

> How is this done on the HDAMA and other boards? The 8111/8131 in bus 0 or bus1 if it works with filo?

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Is net4501 of soekris engineering supported?
by Ravi Dec. 10, 2003

Dec. 10, 2003

Hi, This is my first posting to this list. Before posting this mail I searched for any support of net 4501 soekris box. Is net 4501 soekris box is supported by linuxbios? Thanks in advance, Best Regards, Ravi

2 1

DOCM mapping address?
by Devi Priya Dec. 10, 2003

Dec. 10, 2003

Hi, I like to have my linuxbios, linux OS, filesystem in the same diskonchip millennium. If I have to use diskonchip millennium with linuxbios, to which physical address should the DOCM should be mapped in hardware ? Is any driver should be loaded before the OS gets loaded? I have mapped in hardware 0xFFFFFFFF-0xFF800000. Is this correct? Does any remapping is to be done in hardware afer this? Which file system should I use? Regards, Priya. _________________________________________________________________ Discover India. Celebrate her diversity. http://server1.msn.co.in/features/tourism/ Come, fall in love!

1 0

Promise PDC20275 IDE controller
by Jia Jianwei Dec. 9, 2003

Dec. 9, 2003

I'm working on a BIOS with Promise PDC20275 IDE controller, But the Ultra DMA mode can't work anyway. I can't get the datasheet of the controller.Anybody knows how to initialize the controller? or give me some advices, Thanks very much! Regards, Jia Jianwei

1 0

legacy BIOS usage
by Ryan Underwood Dec. 8, 2003

Dec. 8, 2003

Hi, I had the idea of using LinuxBIOS but also maintaining a legacy BIOS for debugging and dual boot scenarios. It would be linked into the LinuxBIOS image and jumped to alternatively depending on the user input. However, thinking about this gave me 2 questions: 1. Are there any forms of user input possible into LinuxBIOS loader? Is the system initialized enough to accept a keyboard input, or ACPI system button, or even something sillier like checking if a PS/2 mouse is plugged in (the user can unplug the mouse to signal LinuxBIOS to jump to the legacy BIOS instead). 2. Is it possible to get the machine into a state where it can check whatever form of user input is possible, but still be able to then put the machine back into a state where the legacy BIOS won't be confused. Or could something like this be done via the reboot vector instead? Power on clean gets you LinuxBIOS, but reboot goes to legacy BIOS... I guess the problem there again would be putting the hardware back into a state that the legacy BIOS can use. any ideas on that topic? It would be nice to use FreeDOS occasionally for testing some external hardware control programs, but FreeDOS requires a PC BIOS, of which there are no open source implementations that I know of. :( Maybe that can be a project for the future, but somehow I see a lack of interest in putting any new effort into a dead platform, so using the legacy proprietary BIOS might be the only real world choice. p.s. there is a broken Microsoft link in the FAQ, it is here now: http://www.microsoft.com/whdc/hwdev/archive/BUSBIOS/pciirq.mspx -- Ryan Underwood, <nemesis(a)icequake.net>

3 3

答复: for all k8 builders
by YhLu Dec. 8, 2003

Dec. 8, 2003

Eric, I mean in the amdk8_scan_chains, you need to put > config_busses &= 0x000fc88; > config_busses |= > (3 << 0) | /* rw enable, no device compare */ > (( nodeid & 7) << 4) | > (( link & 3 ) << 8) | > ((dev->link[link].secondary) << 16) | > ((dev->link[link].subordinate) << 24); > f1_write_config32(config_reg, config_busses); before /* Now we can scan all of the subordinate busses i.e. the > chain on the hypertranport link */ > max = hypertransport_scan_chain(&dev->link[link], max); YH.

2 1

Re: for all k8 builders
by YhLu Dec. 8, 2003

Dec. 8, 2003

Eric, Please check the northbridge.c attached. It seems you should modify the e0 before you do the hypertransport_scan_chain. Otherwise you can not access the buses. YH. config_busses &= 0x000fc88; config_busses |= (3 << 0) | /* rw enable, no device compare */ (( nodeid & 7) << 4) | (( link & 3 ) << 8) | ((dev->link[link].secondary) << 16) | ((dev->link[link].subordinate) << 24); f1_write_config32(config_reg, config_busses); #if 1 printk_debug("Hyper transport scan link: %d max: %d\n", link, max); #endif /* Now we can scan all of the subordinate busses i.e. the chain on the hypertranport link */ max = hypertransport_scan_chain(&dev->link[link], max);

2 1

Re: for all k8 builders
by YhLu Dec. 8, 2003

Dec. 8, 2003

If only - Fix amdk8_scan_root_bus and amdk8_scan_chains so multiple HT chains can be scanned in any order it will not break the code. There must some other file changes cause that. YH. -----邮件原件----- 发件人: ron minnich [mailto:rminnich@lanl.gov] 发送时间: 2003年12月8日 12:12 收件人: Eric W. Biederman 抄送: linuxbios(a)clustermatic.org 主题: Re: for all k8 builders On 8 Dec 2003, Eric W. Biederman wrote: > Grumble. You are pushing out my changes before we have finished > testing them. I don't mind to much but I do know some of that code > was not fully generalized, so there could be problems if you have > not looked through it carefully. The problem was that builds that worked friday stopped working this morning, due apparently to this: Revision 1.9 - (download), view (text) (markup) (annotate) - [select for diffs] Sat Dec 6 00:11:56 2003 UTC (2 days, 19 hours ago) by ebiederm CVS Tags: HEAD Changes since 1.8: +21 -8 lines Diff to previous 1.8 - Fix amdk8_scan_root_bus and amdk8_scan_chains so multiple HT chains can be scanned in any order === it was your push, not mine. It broke all the K8 builds. I would normally not have pushed your stuff out but this was kind of an emergency. Trust me, I'm not going to push your changes out before we test 'em, but I can't stop you from doing it :-) thanks ron _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

3 3

Re: for all k8 builders
by YhLu Dec. 8, 2003

Dec. 8, 2003

I will check the code.

1 0

for all k8 builders
by ron minnich Dec. 8, 2003

Dec. 8, 2003

your builds are broken today due to the missing amdk8.h file in src/northbridge/amd/amdk8. Do an update; I just added it. ron

2 3

Hardware Help with diskonchip?
by Devi Priya Dec. 8, 2003

Dec. 8, 2003

Hi, In the application note (AP044) from Msystems it is given as: "The DiskOnChip Millennium is mapped into an 8KB memory window in the host platforms memory map. This 8KB window consists of four 2KB windows." Why is this mapping done? Is this mapping done in hardware? I use diskonchip millennium (8MByte MD2800). Then shouldn't the entire 8MB shall be mapped in hardware to the physical address space? The steps for BIOS is summarised as 1. After DiskOnChip Millennium BUSY# signal is negated, the CPU fetches the Reset Vector from the Boot-Block area, fetches the Boot Code stored there, and starts to execute the code. 2. Boot Code runs the first part of BIOS, initializing the basic hardware functionality. 3. Boot Codes loads the rest of the BIOS from the flash memory to the DRAM, and transfer control (jumps) there. 4. Chip Select of DiskOnChip Millennium is remapped from Reset Vector to BIOS expansion area. 5. CPU executes the rest of the BIOS code, including ROM expansion devices (among them, the DiskOnChip Millennium itself). 6. CPU calls OS bootstrap loader (INT19). 7. OS is loaded, and recognizes the DiskOnChip Millennium as the boot device. 8. OS loads the application code from the DiskOnChip Millennium and executes it. 9. Application software uses DiskOnChip Millennium exactly as if it were using a regular hard disk. In step 4 why is this remapping done? Is this mapping done in hardware? In my setup, the diskonchip is mapped in hardware to the higher order address (0xFFFFFFFF-0xFF800000). SDRAM mapped to lower address (0x00000000-0x1FFFFFF). What else modification do i require in HARDWARE to use diskonchip millennium? _________________________________________________________________ Add zing to Hotmail. Get FREE newsletters. http://server1.msn.co.in/features/general/Newsletters/index.asp Subscribe now!

1 0

Will this work ??
by Stefan Dec. 7, 2003

Dec. 7, 2003

Hi there, I've a Gigabyte GA-7NNXP with nForce II Chipset, and a BIOS with a size of 512 KB. Will I be able to get a open source "bios" work on that mainboard ? thx for your helping!!

5 4

Re: Tyan S2885
by YhLu Dec. 5, 2003

Dec. 5, 2003

S2885 updated to 1.1.5 Only reset once.

1 0

Re: Tyan S2885
by YhLu Dec. 5, 2003

Dec. 5, 2003

Eric, Great, it works. Even normal scan it can find out 8151. But the bus number is funny, I may need to update bus number mptable.c and irq_table.c and reset.c I wonder if 8151 on CPU 1 and 8131/8111 on CPU0. is the amdk8_scan_root_bus called two times? If so, you may keep the > for(reg = 0xe0; reg <= 0xec; reg += 4) { > value = f1_read_config32(reg); > printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", > reg,value,max); > if((value>>24)>max) > f1_write_config32(reg, 0); > } Regards YH. -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2003年12月5日 15:26 收件人: YhLu 抄送: ron minnich; Stefan Reinauer; linuxbios(a)clustermatic.org 主题: Re: Tyan S2885 YhLu <YhLu(a)tyan.com> writes: > Eric, > > I change amdk8_scan_root_bus to: > > unsigned int amdk8_scan_root_bus(device_t root, unsigned int max) > { > unsigned reg; > uint32_t value; > /* Unmap all of the other pci busses */ > printk_debug("\nbefore pci_scan_bus\n"); > for(reg = 0xe0; reg <= 0xec; reg += 4) { > value = f1_read_config32(reg); > printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", > reg,value,max); > if((value>>24)>max) > f1_write_config32(reg, 0); > } > for(reg = 0xe0; reg <= 0xec; reg += 4) { > value = f1_read_config32(reg); > printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", > reg,value,max); > } > > max = pci_scan_bus(&root->link[0], PCI_DEVFN(0x18, 0), 0xff, max); > > printk_debug("after pci_scan_bus\n"); > for(reg = 0xe0; reg <= 0xec; reg += 4) { > value = f1_read_config32(reg); > printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", > reg,value,max); > } > > return max; > } > > I think as least you only need to clear the regs that contain bigger bus > number than the next bus for scanning. > > The result will be in the end. > > The problems: > 1. It can not access 8151 on CPU link0 and so can not scan it > 2. The HT scan seems can not figure out and set the link and read/write > enable bit in e0. It set the e0 to 0x05050000 Doh. The Opteron is too forgiving when you only have one link. It makes this kind of debugging a pain. What I am doing should not work but it does in that case... My apologies, for missing this. In amdk8_scan_chains() there is the snippet: config_busses &= 0x0000ffff; config_busses |= ((dev->link[link].secondary) << 16) | ((dev->link[link].subordinate) << 24); f1_write_config32(config_reg, config_busses); Which is the offending piece of code. It neither sets the link that we are supposed to go out, nor does it set the r/w enable bits. Ouch. It only works if those registers are pre programmed. So I think this should be: config_busses &= 0x000fc88; config_busses |= (3 << 0) | /* rw enable, no device compare */ (( nodeid & 7) << 4) | (( link & 3 ) << 8) | ((dev->link[link].secondary) << 16) | ((dev->link[link].subordinate) << 24); f1_write_config32(config_reg, config_busses); Eric

2 1

Re: Tyan S2885
by YhLu Dec. 5, 2003

Dec. 5, 2003

Eric, I change amdk8_scan_root_bus to: unsigned int amdk8_scan_root_bus(device_t root, unsigned int max) { unsigned reg; uint32_t value; /* Unmap all of the other pci busses */ printk_debug("\nbefore pci_scan_bus\n"); for(reg = 0xe0; reg <= 0xec; reg += 4) { value = f1_read_config32(reg); printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", reg,value,max); if((value>>24)>max) f1_write_config32(reg, 0); } for(reg = 0xe0; reg <= 0xec; reg += 4) { value = f1_read_config32(reg); printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", reg,value,max); } max = pci_scan_bus(&root->link[0], PCI_DEVFN(0x18, 0), 0xff, max); printk_debug("after pci_scan_bus\n"); for(reg = 0xe0; reg <= 0xec; reg += 4) { value = f1_read_config32(reg); printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", reg,value,max); } return max; } I think as least you only need to clear the regs that contain bigger bus number than the next bus for scanning. The result will be in the end. The problems: 1. It can not access 8151 on CPU link0 and so can not scan it 2. The HT scan seems can not figure out and set the link and read/write enable bit in e0. It set the e0 to 0x05050000 Regards Yinghai Lu Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.52.0_Fallback Fri Dec 5 14:29:03 EST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD 8111 Enumerating buses... before pci_scan_bus amdk8_scan_root_bus e0 = 4000203 max = 0 amdk8_scan_root_bus e4 = 6050003 max = 0 amdk8_scan_root_bus e8 = 0 max = 0 amdk8_scan_root_bus ec = 0 max = 0 amdk8_scan_root_bus e0 = 0 max = 0 amdk8_scan_root_bus e4 = 0 max = 0 amdk8_scan_root_bus e8 = 0 max = 0 amdk8_scan_root_bus ec = 0 max = 0 PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed PCI: pci_scan_bus for bus 1 PCI: 01:01.0 [1022/7450] bus ops PCI: 01:01.0 [1022/7450] enabled PCI: 01:01.1 [1022/7451] ops PCI: 01:01.1 [1022/7451] enabled PCI: 01:02.0 [1022/7450] bus ops PCI: 01:02.0 [1022/7450] enabled PCI: 01:02.1 [1022/7451] ops PCI: 01:02.1 [1022/7451] enabled PCI: 01:03.0 [1022/7460] enabled PCI: 01:04.0 [1022/7468] bus ops PCI: 01:04.0 [1022/7468] enabled PCI: 01:04.1 [1022/7469] ops PCI: 01:04.1 [1022/7469] enabled PCI: 01:04.2 [1022/746a] enabled PCI: 01:04.3 [1022/746b] ops PCI: 01:04.3 [1022/746b] enabled PCI: 01:04.5 [1022/746d] enabled amd8111_enable dev: PCI: 01:04.6 lpc_dev: PCI: 01:04.0 index: 6 reg: ffff -> ffbf done PCI: 01:04.6 [ffff/ffff] disabled PCI: pci_scan_bus for bus 2 PCI: 02:09.0 [14e4/16a7] ops PCI: 02:09.0 [14e4/16a7] enabled PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus for bus 3 PCI: pci_scan_bus returning with max=03 PCI: pci_scan_bus for bus 4 PCI: 04:00.0 [1022/7464] ops PCI: 04:00.0 [1022/7464] enabled PCI: 04:00.1 [1022/7464] ops PCI: 04:00.1 [1022/7464] enabled PCI: 04:00.2 [1022/7463] ops PCI: 04:00.2 [1022/7463] enabled amd8111_enable dev: PCI: 04:01.0 lpc_dev: PCI: 01:04.0 index: 9 reg: ffbf -> fdbf done PCI: 04:01.0 [ffff/ffff] disabled PCI: 04:0b.0 [1095/3114] ops PCI: 04:0b.0 [1095/3114] enabled PCI: 04:0c.0 [104c/8023] ops PCI: 04:0c.0 [104c/8023] enabled PCI: pci_scan_bus returning with max=04 PCI: pci_scan_bus returning with max=04 Hyper transport scan link: 2 new max: 4 Hypertransport scan link done Hyper transport scan link: 0 max: 5 Missing static device: PCI: 05:00.0 HyperT reset not needed PCI: pci_scan_bus for bus 5 PCI: 05:00.0 [ffff/ffff/00ffff] has unknown header type ff, ignoring. PCI: 05:00.0 No device operations PCI: 05:01.0 [ffff/ffff/00ffff] has unknown header type ff, ignoring. PCI: 05:01.0 No device operations PCI: pci_scan_bus returning with max=05 Hyper transport scan link: 0 new max: 5 Hypertransport scan link done amdk8_scan_chains max: 5 done amdk8_scan_chains max: 5 starting... amdk8_scan_chains max: 5 done PCI: pci_scan_bus returning with max=05 after pci_scan_bus amdk8_scan_root_bus e0 = 5050000 max = 5 amdk8_scan_root_bus e4 = 0 max = 5 amdk8_scan_root_bus e8 = 0 max = 5 amdk8_scan_root_bus ec = 0 max = 5 done Allocating resources... PCI: 05:00.0 missing read_resources PCI: 05:01.0 missing read_resources PCI: 05:00.0 missing read_resources PCI: 05:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 01:04.6 missing read_resources PCI: 01:04.6 missing read_resources ASSIGN RESOURCES, bus 0 PCI: 05:00.0 missing read_resources PCI: 05:01.0 missing read_resources PCI: 00:18.0 c8 <- [0x00003000 - 0x00002fff] node 0 link 0 io PCI: 05:00.0 missing read_resources PCI: 05:01.0 missing read_resources PCI: 00:18.0 80 <- [0xfec00000 - 0xfebfffff] node 0 link 0 mem PCI: 01:04.6 missing read_resources PCI: 00:18.0 c0 <- [0x00001000 - 0x00002fff] node 0 link 2 io PCI: 01:04.6 missing read_resources PCI: 00:18.0 b8 <- [0xfe900000 - 0xfebfffff] node 0 link 2 mem ASSIGN RESOURCES, bus 5 PCI: 05:00.0 missing set_resources PCI: 05:01.0 missing set_resources ASSIGNED RESOURCES, bus 5 ASSIGN RESOURCES, bus 1 PCI: 01:01.0 1c <- [0x00002000 - 0x00001fff] bus 2 io PCI: 01:01.0 24 <- [0xfeb00000 - 0xfeafffff] bus 2 prefmem PCI: 01:01.0 20 <- [0xfe900000 - 0xfe9fffff] bus 2 mem ASSIGN RESOURCES, bus 2 PCI: 02:09.0 10 <- [0xfe900000 - 0xfe90ffff] mem ASSIGNED RESOURCES, bus 2 PCI: 01:01.1 10 <- [0xfeb00000 - 0xfeb00fff] mem PCI: 01:02.0 1c <- [0x00002000 - 0x00001fff] bus 3 io PCI: 01:02.0 24 <- [0xfeb00000 - 0xfeafffff] bus 3 prefmem PCI: 01:02.0 20 <- [0xfeb00000 - 0xfeafffff] bus 3 mem PCI: 01:02.1 10 <- [0xfeb01000 - 0xfeb01fff] mem PCI: 04:01.0 missing read_resources PCI: 01:03.0 1c <- [0x00001000 - 0x00001fff] bus 4 io PCI: 04:01.0 missing read_resources PCI: 01:03.0 24 <- [0xfeb00000 - 0xfeafffff] bus 4 prefmem PCI: 04:01.0 missing read_resources PCI: 01:03.0 20 <- [0xfea00000 - 0xfeafffff] bus 4 mem ASSIGN RESOURCES, bus 4 PCI: 04:00.0 10 <- [0xfea04000 - 0xfea04fff] mem PCI: 04:00.1 10 <- [0xfea05000 - 0xfea05fff] mem PCI: 04:00.2 10 <- [0xfea08000 - 0xfea080ff] mem PCI: 04:00.2 14 <- [0xfea09000 - 0xfea0901f] mem PCI: 04:01.0 missing set_resources PCI: 04:0b.0 10 <- [0x00001010 - 0x00001017] io PCI: 04:0b.0 14 <- [0x00001030 - 0x00001033] io PCI: 04:0b.0 18 <- [0x00001020 - 0x00001027] io PCI: 04:0b.0 1c <- [0x00001040 - 0x00001043] io PCI: 04:0b.0 20 <- [0x00001000 - 0x0000100f] io PCI: 04:0b.0 24 <- [0xfea07000 - 0xfea073ff] mem PCI: 04:0c.0 10 <- [0xfea06000 - 0xfea067ff] mem PCI: 04:0c.0 14 <- [0xfea00000 - 0xfea03fff] mem ASSIGNED RESOURCES, bus 4 PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] io PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] mem PCI: 01:04.1 20 <- [0x00002460 - 0x0000246f] io PCI: 01:04.2 10 <- [0x00002440 - 0x0000245f] io PCI: 01:04.5 10 <- [0x00002000 - 0x000020ff] io PCI: 01:04.5 14 <- [0x00002400 - 0x0000243f] io PCI: 01:04.6 missing set_resources ASSIGNED RESOURCES, bus 1 ASSIGNED RESOURCES, bus 0 done. Enabling resourcess... PCI: 00:18.0 cmd <- 00 PCI: 05:00.0 missing enable_resources PCI: 05:01.0 missing enable_resources PCI: 01:01.0 bridge ctrl <- 0000 PCI: 01:01.0 cmd <- 07 PCI: 02:09.0 cmd <- 02 PCI: 01:01.1 cmd <- 06 PCI: 01:02.0 bridge ctrl <- 0000 PCI: 01:02.0 cmd <- 07 PCI: 01:02.1 cmd <- 06 PCI: 01:03.0 bridge ctrl <- 0000 PCI: 01:03.0 cmd <- 07 PCI: 04:00.0 cmd <- 02 PCI: 04:00.1 cmd <- 02 PCI: 04:00.2 cmd <- 02 PCI: 04:01.0 missing enable_resources PCI: 04:0b.0 cmd <- 03 PCI: 04:0c.0 cmd <- 02 PCI: 01:04.0 cmd <- 0f PCI: 01:04.1 cmd <- 01 PCI: 01:04.2 cmd <- 01 PCI: 01:04.3 cmd <- 00 PCI: 01:04.5 cmd <- 01 PCI: 01:04.6 missing enable_resources PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:19.0 cmd <- 00 PCI: 00:19.1 cmd <- 00 PCI: 00:19.2 cmd <- 00 PCI: 00:19.3 cmd <- 00 done. Initializing devices... PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:19.3 init NB: Function 3 Misc Control.. resetting cpu

2 1

Re: Tyan S2885
by YhLu Dec. 5, 2003

Dec. 5, 2003

Eric, If don't clear the regs, the result will be: Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.52.0_Fallback Fri Dec 5 15:05:21 EST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD 8111 Enumerating buses... before pci_scan_bus amdk8_scan_root_bus e0 = 4000203 max = 0 amdk8_scan_root_bus e4 = 6050003 max = 0 amdk8_scan_root_bus e8 = 0 max = 0 amdk8_scan_root_bus ec = 0 max = 0 PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed PCI: pci_scan_bus for bus 1 PCI: 01:01.0 [1022/7450] bus ops PCI: 01:01.0 [1022/7450] enabled PCI: 01:01.1 [1022/7451] ops PCI: 01:01.1 [1022/7451] enabled PCI: 01:02.0 [1022/7450] bus ops PCI: 01:02.0 [1022/7450] enabled PCI: 01:02.1 [1022/7451] ops PCI: 01:02.1 [1022/7451] enabled PCI: 01:03.0 [1022/7460] enabled PCI: 01:04.0 [1022/7468] bus ops PCI: 01:04.0 [1022/7468] enabled PCI: 01:04.1 [1022/7469] ops PCI: 01:04.1 [1022/7469] enabled PCI: 01:04.2 [1022/746a] enabled PCI: 01:04.3 [1022/746b] ops PCI: 01:04.3 [1022/746b] enabled PCI: 01:04.5 [1022/746d] enabled amd8111_enable dev: PCI: 01:04.6 lpc_dev: PCI: 01:04.0 index: 6 reg: ffff -> ffbf done PCI: 01:04.6 [ffff/ffff] disabled PCI: pci_scan_bus for bus 2 PCI: 02:09.0 [14e4/16a7] ops PCI: 02:09.0 [14e4/16a7] enabled PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus for bus 3 PCI: pci_scan_bus returning with max=03 PCI: pci_scan_bus for bus 4 PCI: 04:00.0 [1022/7464] ops PCI: 04:00.0 [1022/7464] enabled PCI: 04:00.1 [1022/7464] ops PCI: 04:00.1 [1022/7464] enabled PCI: 04:00.2 [1022/7463] ops PCI: 04:00.2 [1022/7463] enabled amd8111_enable dev: PCI: 04:01.0 lpc_dev: PCI: 01:04.0 index: 9 reg: ffbf -> fdbf done PCI: 04:01.0 [ffff/ffff] disabled PCI: 04:0b.0 [1095/3114] ops PCI: 04:0b.0 [1095/3114] enabled PCI: 04:0c.0 [104c/8023] ops PCI: 04:0c.0 [104c/8023] enabled PCI: pci_scan_bus returning with max=04 PCI: pci_scan_bus returning with max=04 Hyper transport scan link: 2 new max: 4 Hypertransport scan link done Hyper transport scan link: 0 max: 5 PCI: 05:01.0 [1022/7454] enabled next_unitid: 0004 HyperT reset needed PCI: pci_scan_bus for bus 5 PCI: 05:01.0 [1022/7454] ops PCI: 05:01.0 [1022/7454] enabled PCI: 05:02.0 [1022/7455] bus ops PCI: 05:02.0 [1022/7455] enabled PCI: pci_scan_bus for bus 6 PCI: 06:00.0 [10de/0322] enabled PCI: pci_scan_bus returning with max=06 PCI: pci_scan_bus returning with max=06 Hyper transport scan link: 0 new max: 6 Hypertransport scan link done amdk8_scan_chains max: 6 done amdk8_scan_chains max: 6 starting... amdk8_scan_chains max: 6 done PCI: pci_scan_bus returning with max=06 after pci_scan_bus amdk8_scan_root_bus e0 = 4010203 max = 6 amdk8_scan_root_bus e4 = 6050003 max = 6 amdk8_scan_root_bus e8 = 0 max = 6 amdk8_scan_root_bus ec = 0 max = 6 done Allocating resources... PCI: 04:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 01:04.6 missing read_resources PCI: 01:04.6 missing read_resources ASSIGN RESOURCES, bus 0 PCI: 00:18.0 c8 <- [0x00003000 - 0x00002fff] node 0 link 0 io PCI: 00:18.0 80 <- [0xe0000000 - 0xf8ffffff] node 0 link 0 mem PCI: 01:04.6 missing read_resources PCI: 00:18.0 c0 <- [0x00001000 - 0x00002fff] node 0 link 2 io PCI: 01:04.6 missing read_resources PCI: 00:18.0 b8 <- [0xf9000000 - 0xf92fffff] node 0 link 2 mem ASSIGN RESOURCES, bus 5 PCI: 05:01.0 10 <- [0xe0000000 - 0xefffffff] prefmem PCI: 05:02.0 1c <- [0x00003000 - 0x00002fff] bus 6 io PCI: 05:02.0 24 <- [0xf0000000 - 0xf7ffffff] bus 6 prefmem PCI: 05:02.0 20 <- [0xf8000000 - 0xf8ffffff] bus 6 mem ASSIGN RESOURCES, bus 6 PCI: 06:00.0 10 <- [0xf8000000 - 0xf8ffffff] mem PCI: 06:00.0 14 <- [0xf0000000 - 0xf7ffffff] prefmem ASSIGNED RESOURCES, bus 6 ASSIGNED RESOURCES, bus 5 ASSIGN RESOURCES, bus 1 PCI: 01:01.0 1c <- [0x00002000 - 0x00001fff] bus 2 io PCI: 01:01.0 24 <- [0xf9200000 - 0xf91fffff] bus 2 prefmem PCI: 01:01.0 20 <- [0xf9000000 - 0xf90fffff] bus 2 mem ASSIGN RESOURCES, bus 2 PCI: 02:09.0 10 <- [0xf9000000 - 0xf900ffff] mem ASSIGNED RESOURCES, bus 2 PCI: 01:01.1 10 <- [0xf9200000 - 0xf9200fff] mem PCI: 01:02.0 1c <- [0x00002000 - 0x00001fff] bus 3 io PCI: 01:02.0 24 <- [0xf9200000 - 0xf91fffff] bus 3 prefmem PCI: 01:02.0 20 <- [0xf9200000 - 0xf91fffff] bus 3 mem PCI: 01:02.1 10 <- [0xf9201000 - 0xf9201fff] mem PCI: 04:01.0 missing read_resources PCI: 01:03.0 1c <- [0x00001000 - 0x00001fff] bus 4 io PCI: 04:01.0 missing read_resources PCI: 01:03.0 24 <- [0xf9200000 - 0xf91fffff] bus 4 prefmem PCI: 04:01.0 missing read_resources PCI: 01:03.0 20 <- [0xf9100000 - 0xf91fffff] bus 4 mem ASSIGN RESOURCES, bus 4 PCI: 04:00.0 10 <- [0xf9104000 - 0xf9104fff] mem PCI: 04:00.1 10 <- [0xf9105000 - 0xf9105fff] mem PCI: 04:00.2 10 <- [0xf9108000 - 0xf91080ff] mem PCI: 04:00.2 14 <- [0xf9109000 - 0xf910901f] mem PCI: 04:01.0 missing set_resources PCI: 04:0b.0 10 <- [0x00001010 - 0x00001017] io PCI: 04:0b.0 14 <- [0x00001030 - 0x00001033] io PCI: 04:0b.0 18 <- [0x00001020 - 0x00001027] io PCI: 04:0b.0 1c <- [0x00001040 - 0x00001043] io PCI: 04:0b.0 20 <- [0x00001000 - 0x0000100f] io PCI: 04:0b.0 24 <- [0xf9107000 - 0xf91073ff] mem PCI: 04:0c.0 10 <- [0xf9106000 - 0xf91067ff] mem PCI: 04:0c.0 14 <- [0xf9100000 - 0xf9103fff] mem ASSIGNED RESOURCES, bus 4 PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] io PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] mem PCI: 01:04.1 20 <- [0x00002460 - 0x0000246f] io PCI: 01:04.2 10 <- [0x00002440 - 0x0000245f] io PCI: 01:04.5 10 <- [0x00002000 - 0x000020ff] io PCI: 01:04.5 14 <- [0x00002400 - 0x0000243f] io PCI: 01:04.6 missing set_resources ASSIGNED RESOURCES, bus 1 ASSIGNED RESOURCES, bus 0 Allocating VGA resource done. Enabling resourcess... PCI: 00:18.0 cmd <- 00 PCI: 05:01.0 cmd <- 06 PCI: 05:02.0 bridge ctrl <- 003e PCI: 05:02.0 cmd <- 07 PCI: 06:00.0 cmd <- 03 PCI: 01:01.0 bridge ctrl <- 0000 PCI: 01:01.0 cmd <- 07 PCI: 02:09.0 cmd <- 02 PCI: 01:01.1 cmd <- 06 PCI: 01:02.0 bridge ctrl <- 0000 PCI: 01:02.0 cmd <- 07 PCI: 01:02.1 cmd <- 06 PCI: 01:03.0 bridge ctrl <- 0000 PCI: 01:03.0 cmd <- 07 PCI: 04:00.0 cmd <- 02 PCI: 04:00.1 cmd <- 02 PCI: 04:00.2 cmd <- 02 PCI: 04:01.0 missing enable_resources PCI: 04:0b.0 cmd <- 03 PCI: 04:0c.0 cmd <- 02 PCI: 01:04.0 cmd <- 0f PCI: 01:04.1 cmd <- 01 PCI: 01:04.2 cmd <- 01 PCI: 01:04.3 cmd <- 00 PCI: 01:04.5 cmd <- 01 PCI: 01:04.6 missing enable_resources PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:19.0 cmd <- 00 PCI: 00:19.1 cmd <- 00 PCI: 00:19.2 cmd <- 00 PCI: 00:19.3 cmd <- 00 done. Initializing devices... PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:19.3 init NB: Function 3 Misc Control.. resetting cpu

1 0

Update to pirq_routing
by Jordan Archer Dec. 5, 2003

Dec. 5, 2003

The following is the diff for a change I made. I think the HAVE_PIRQ_TABLE is always defined and this allowed me to turn off the existence of a routing table. Jordan RCS file: /cvsroot/freebios/freebios2/src/arch/i386/include/arch/pirq_routing.h,v retrieving revision 1.1 diff -r1.1 pirq_routing.h 42c42,43 < #if defined(DEBUG) && defined(HAVE_PIRQ_TABLE) --- > //#if defined(DEBUG) && defined(HAVE_PIRQ_TABLE) > #if defined(DEBUG) && HAVE_PIRQ_TABLE // JORDAN: This needs to be dependent on value, not existence. 48c49,50 < #if defined(HAVE_PIRQ_TABLE) --- > //#if defined(HAVE_PIRQ_TABLE) > #if HAVE_PIRQ_TABLE // JORDAN: This needs to be dependent on value, not Index: romcc_io.h ===================================================================

1 0

Re: Tyan S4880
by YhLu Dec. 5, 2003

Dec. 5, 2003

Ron, Please check in the Tyan s2850/2880/2881/2882/4880 updates into the CVS Tree. 1. northbridge/amd/amdk8/raminit.h: change uint8_t to uint16_t 2. southbridge/amd/amd8111/amd8111_early_smbus.c: update smbus_write_byte 3. southbridge/amd/amd8131/amd8131_bridge.c: update ioapic_anable to enable PCI-X MASTER Mode. 4. other in /src/mainboard/tyan/ and /targets/tyan Stefan, With update 1 and 2, you can get ride of FAKE_SPD_ROM. You need to change some lines in auto.c for quartet. 1. I2C HUB address: 0x30 --> 0x18, 2. RC0-> (1<<1)<<8, RC1-> (1<<2)<<8, RC2-> (1<<3)<<8, RC3-> (1<<4)<<8. Regards YH.

6 13

Re: Tyan S2885
by YhLu Dec. 5, 2003

Dec. 5, 2003

I will try the code and use normal scan. YH. -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2003年12月4日 21:36 收件人: YhLu 抄送: ron minnich; Stefan Reinauer; linuxbios(a)clustermatic.org 主题: Re: Tyan S2885 YhLu <YhLu(a)tyan.com> writes: > Eric, > > I found in amdk8_scan_root_bus in northbridge/amd/amdk8/northbridge.c > You put > /* Unmap all of the other pci busses */ > for(reg = 0xe0; reg <= 0xec; reg += 4) { > f1_write_config32(reg, 0); > } > > Why you need to clear that? After you clear that, I can not see the 8151 and > AGP in s2885. Hmm. This looks like a thinko. So right now the code says: unsigned int amdk8_scan_root_bus(device_t root, unsigned int max) { unsigned reg; max = pci_scan_bus(&root->link[0], PCI_DEVFN(0x18, 0), 0xff, max); /* Unmap all of the other pci busses */ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } return max; } And I think what I meant was: unsigned int amdk8_scan_root_bus(device_t root, unsigned int max) { unsigned reg; /* Unmap all of the other pci busses */ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } max = pci_scan_bus(&root->link[0], PCI_DEVFN(0x18, 0), 0xff, max); return max; } I don't have a clue why it works at all with clearing those registers after the pci bus scan. I wonder if that is the reason scan order matters because I don't clear those registers out first and things are dual mapped. Anyway my intention was to be very careful and to clear the HT chain mapping registers before we scanned them so we didn't have any old configurations getting in the way. Eric

1 0

arima hdama success
by Craig C Forney Dec. 5, 2003

Dec. 5, 2003

On Wed, 3 Dec 2003, Ron Minnich wrote > as of this morning, with Yh Lu's changes, arima hdama builds work fine. > >ron I'm not having the same success. I got the latest snapshot this evening, built for the arima hdama, and it fails the same way it has failed (hangs after printing out stuff below) for the last couple of months. Have Yh Lu's changes that fix the arima hdama been committed? If not, could someone point me to the changes that fix whatever this problem is? Thanks, Craig Forney Opus Innovations LLC LinuxBIOS-1.1.5.0Fallback Thu Dec 4 23:13:33 PST 2003 starting... setting up resource map.... AMD8111 southbridge is connected to HT link 00000000 setting up resource map.... done. Enabling routing table for node 00000000 done. Enabling SMP settings setup_remote_node setup_remote_done Renaming current temp node to 00000001 done. Enabling routing table for node 00000001 done. 00000002 nodes initialized. detect_mp_capabilities: 00000002 coherent_ht_finalize done SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram1.01 setting up CPU01 northbridge registers done. Ram2.00 166Mhz Interleaved RAM: 0x00100000 KB Ram2.01 Enabling dual channel memory disabling dimm00 disabling dimm01 disabling dimm00 disabling dimm01 200Mhz disabling dimm00 disabling dimm01 RAM: 0x00100000 KB Ram3 ECC enabled ECC enabled Initializing memory: done Clearing memory: addr 00000000-0000003f ----------------done Initializing memory: done Clearing memory: addr 00000040-0000003f done Ram4 PCI: 00:01.00 00: 22 10 50 74 00 00 30 02 12 00 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f1 01 20 02 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: ff ff 00 00 a0 00 00 00 00 00 00 00 ff 00 00 00 40: 07 00 1f 00 00 00 00 00 02 0c 00 00 00 2c 00 00 50: 00 00 02 00 00 00 04 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 07 b8 03 00 08 00 03 00 0e 00 ff ff 02 00 ff ff b0: 00 00 00 00 00 00 00 00 08 c0 00 80 00 00 00 00 c0: 08 00 41 00 20 00 11 00 20 00 00 00 22 00 35 00 d0: 02 00 35 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 08 0c 00 08 08 0d 00 0f 0f 13 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:01.01 00: 22 10 51 74 00 00 00 02 01 10 00 08 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00 ... PCI info deleted for brevity ... 80: 33 00 00 00 00 00 00 00 35 33 72 13 20 0a 10 00 90: 00 80 0a 08 08 0b 5b 0e 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: a3 88 1e 5a 02 00 00 00 8c 5b b7 d6 72 9f e7 ef c0: 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 04 67 05 44 e4 ae 6b 16 9e 4f 10 40 c5 1b cc 44 e0: d9 c6 0a 24 48 04 5c 10 38 6c 03 48 86 74 2e 26 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:18.03 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 40 00 be fc 07 77 73 80 7b 46 50: 08 a5 f7 0b 88 00 00 00 16 16 16 00 00 04 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 02 00 00 00 70 0f 00 00 00 83 06 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 01 00 00 e0 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 20 10 00 00 1b 01 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.5.0Fallback Thu Dec 4 23:13:33 PST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD 8111 Enumerating: NSC 87360 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [ffff/ffff] enabled PCI: 00:19.1 [ffff/ffff/00ffff] has unknown header type ff, ignoring. PCI: 00:19.1 No device operations

1 0

Tyan S2885
by YhLu Dec. 5, 2003

Dec. 5, 2003

Eric, I found in amdk8_scan_root_bus in northbridge/amd/amdk8/northbridge.c You put /* Unmap all of the other pci busses */ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } Why you need to clear that? After you clear that, I can not see the 8151 and AGP in s2885. PS: I have reversed the scan sequence to make sure HT scan 8111 at first and then 8151. Regards Yinghai Lu

2 1

Level 2 cache activation code?
by Svante Signell Dec. 4, 2003

Dec. 4, 2003

Hello, I have recently upgraded my dual MSI-6120 from 2xCeleron (Mendocino) 300@450MHz with 2xMSI-6905 slot 370 to slot 1 adapters to one Celeron2 1.3GHz (Tualatin) using a Slot-T adapter card. The plan is to equip the mobo with 2xPIII or preferably 2xVIA C3 Nehemiah (when SMP capable). The problem is that the latest MSI BIOS (v2.0) for the mobo does not support Coppermine/Tualatin processors. The single GNU/Linux kernels boot without problems but _extremely_ slowly, at least with a speed reduction by a factor 10. hdparm -tT gives around 20/2 compared with 250/25 with the Mendocino CPU(s). For example uncompressing the kernel takes minute(s) compared to seconds. After some trials and web searching I suspect that the problem is with the level 2 cache not activated by the BIOS. I see the you have code in the linuxbios for activating caches. i) Does this code work for 440BX motherboards? ii) Is it possible to extract this code and try out after the kernel has booted (slowly), to verify my assumption? iii) Is there some other tool available for cache activation? iv) One interesting continuation would be to try to replace the MSI (AMI) BIOS with linuxbios, but as a first step I think this would be a little risky. Any ideas? Thanks, Svante

6 27

Doubt with Diskonchip millennium?
by Devi Priya Dec. 4, 2003

Dec. 4, 2003

Hi, In the application note (AP044) from Msystems diskonchip it is given as: "The DiskOnChip Millennium is mapped into an 8KB memory window in the host platforms memory map. This 8KB window consists of four 2KB windows." Why is this mapping done? Is this done for all the DiskOnChip Millennium? The steps for BIOS is summarised as 1. After DiskOnChip Millennium BUSY# signal is negated, the CPU fetches the Reset Vector from the Boot-Block area, fetches the Boot Code stored there, and starts to execute the code. 2. Boot Code runs the first part of BIOS, initializing the basic hardware functionality. 3. Boot Codes loads the rest of the BIOS from the flash memory to the DRAM, and transfer control (jumps) there. 4. Chip Select of DiskOnChip Millennium is remapped from Reset Vector to BIOS expansion area. 5. CPU executes the rest of the BIOS code, including ROM expansion devices (among them, the DiskOnChip Millennium itself). 6. CPU calls OS bootstrap loader (INT19). 7. OS is loaded, and recognizes the DiskOnChip Millennium as the boot device. 8. OS loads the application code from the DiskOnChip Millennium and executes it. 9. Application software uses DiskOnChip Millennium exactly as if it were using a regular hard disk. In step 4 why is this remapping done _________________________________________________________________ Shop online for kids toys by age group, price range, and toy category at MSN Shopping. No waiting for a clerk to help you! http://shopping.msn.com

1 0

Re: Diskonchip ipl code for sc1200?
by Devi Priya Dec. 3, 2003

Dec. 3, 2003

Hi, Thanks for ur suggestion. Should I write both ipl code for the chipset and the DOCM? Should I also write the SPL code for chipset and DOCM? Can I use the ipl and spl code given with the xpressloader BootLoader Development Kit? >From: ron minnich <rminnich(a)lanl.gov> >To: Devi Priya <ijpriya(a)hotmail.com> >CC: linuxbios(a)clustermatic.org >Subject: Re: Diskonchip ipl code for sc1200? >Date: Wed, 3 Dec 2003 07:34:03 -0700 (MST) > >On Wed, 3 Dec 2003, Devi Priya wrote: > > > I could not find any ipl code for sc1200 (nano mainboard). Which >should I > > mention in the config file for docipl? Please give me suggestion. > >you'll have to write it. > >ron > >_______________________________________________ >Linuxbios mailing list >Linuxbios(a)clustermatic.org >http://www.clustermatic.org/mailman/listinfo/linuxbios _________________________________________________________________ It is Ms World time! Send in your wishes to Ami Vashi. http://server1.msn.co.in/sp03/Missworld2003/ Help her bring home the crown!

2 1

Filesystem for doc?
by Devi Priya Dec. 3, 2003

Dec. 3, 2003

Hi, Which filesystem should I use for diskonchip? Should I use ths True FFS or can I use the NFTL? _________________________________________________________________ Love shopping online? Get this e credit card. http://server1.msn.co.in/features/amex/ Save cost, add value!

1 0

Re: Tyan S2885
by YhLu Dec. 3, 2003

Dec. 3, 2003

Output -----邮件原件----- 发件人: YhLu 发送时间: 2003年12月3日 18:34 收件人: YhLu; ebiederman(a)lnxi.com 抄送: ron minnich; Stefan Reinauer; linuxbios(a)clustermatic.org 主题: Tyan S2885 Eric, I found in amdk8_scan_root_bus in northbridge/amd/amdk8/northbridge.c You put /* Unmap all of the other pci busses */ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } Why you need to clear that? After you clear that, I can not see the 8151 and AGP in s2885. PS: I have reversed the scan sequence to make sure HT scan 8111 at first and then 8151. Regards Yinghai Lu

1 0

irq tables generation
by Stefan Reinauer Dec. 3, 2003

Dec. 3, 2003

Hi, * ron minnich <rminnich(a)lanl.gov> [031202 00:28]: > > {0,0xa0, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0}, > > > pci_assign_irqs(2, 0x5, dualenetbIrq);'' > > in addition i had to play with the irq lists. > > eek. You know that this is exactly the wrong way to do this and why, I > assume. But it works, so keep it for now. But this will never go into the > CVS. Do we agree that interrupts should be _unassigned_ during firmware execution and set by the OS only? Another way of handling this might be to set some default values and allow the OS to reconfigure those. A PIRQ-Table has to contain * one entry for each PCI device that needs an interrupt * one entry for each peer bus to be visible. It seems we know these parameters in-system already and can generate a valid table assuming some fixed parameters (cycling interrupts a la {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}} and a fixed mask of 0xdeb8. > irq_table.c is for linux, it tells linux how the irqs are wired up. In an > ideal world, linuxbios would hand the irq table to linux or plan9 or *bsd > and those OSes would do everything correctly. In our world, each of these > OSes get it wrong often enough that we have to now assign it directly. I > had hoped to avoid IRQ assignment in linuxbios but it seems that we have > no choice -- too many busted hardware/OS bits out there. Not to forget the mptable - that contains additional information on which busses are available - information that Linux obviously don't like to read from there but from the irq table. Stefan -- Stefan Reinauer, SUSE LINUX AG Teamleader Architecture Development

2 2

Re: config -> default
by Greg Watson Dec. 3, 2003

Dec. 3, 2003

Stefan, Which builds are broken? I thought I checked all configurations built after the change (apart from the VIA which Ron was working on.) and modified any that had problems. My hope was that this change would make the use of options more logical and consistent. The intention is that parts set default values for any options that they require or are specific to the part. Then when all the parts are put together in a target configuration file, these default values can be overridden for the specific build. I was also toying with the idea of allowing some options to be read-only, which I think would address your concern. Apologies for breaking things. I try to build all targets after any change like this to make sure things are still working. Greg At 4:16 PM +0100 11/6/03, Stefan Reinauer wrote: >Hi, > >most of the builds are broken again since "config" in the mainboard >config file now has to be renamed to "default". On the one hand I see >the reason for most of these changes, even though I am not sure if >we want to suggest that some stuff can be overridden in the target >config file, like: > >-option CONFIG_IOAPIC=1 >+default CONFIG_IOAPIC=1 > >Can those changing elementary stuff like this that breaks all builds try >to apply some regexps on the Config files so that other builds don't >break? Getting further is somewhat hard currently since the code almost >instantly breaks after the last fixes are checked in.. > >Stefan > >-- > Stefan Reinauer, SUSE LINUX AG >Teamleader Architecture Development >_______________________________________________ >Linuxbios mailing list >Linuxbios(a)clustermatic.org >http://www.clustermatic.org/mailman/listinfo/linuxbios

3 6

arima hdama success
by ron minnich Dec. 3, 2003

Dec. 3, 2003

as of this morning, with Yh Lu's changes, arima hdama builds work fine. ron

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Diskonchip ipl code for sc1200?
by Devi Priya Dec. 3, 2003

Dec. 3, 2003

Hi, I could not find any ipl code for sc1200 (nano mainboard). Which should I mention in the config file for docipl? Please give me suggestion. Thanks in advance. _________________________________________________________________ Contact brides & grooms FREE! Only on www.shaadi.com. http://www.shaadi.com/ptnr.php?ptnr=hmltag Register now!

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Help on epia-m 10000 linuxbios VGA
by Santi Mirenna Dec. 3, 2003

Dec. 3, 2003

Hi to all, today i make EPIA-M 10000 rom image. i compile to have VGA and Filo, after apply patch of Dave Ashley and info from Takeshi about RAM ammount VGA now is found by the system but .... In attach you have the output log .... Can someone tell me where i wrong? Dave Ashley reply: You haven't applied all the patch, specifically the handler for the unsupported bios interrupts. This is the bug where it just gets into an endless loop of bios interrupts, so the program needs to exit the bios somehow. -Dave Hi , can some one tell me where to look .... i made the patch ....where to look Dave to know if the patch is ok ? Thanks. Santi Mirenna

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Re: Help on epia-m 10000 linuxbios VGA
by Santi Mirenna Dec. 3, 2003

Dec. 3, 2003

At 11.59 03/12/2003, you wrote: >Hi Santi, > >At a minimum you need to check that your arch/i386/lib/idt.c file has the >Int 21 and Unsupported Interrupt handler calling code installed: > >@@ -175,9 +175,18 @@ > eax = 64 * 1024; > ret = 0; > break; >+#ifdef CONFIG_INT21HANDLER >+ case 0x15: >+ ret=handleint21( &edi, &esi, &ebp, &esp, >+ &ebx, &edx, &ecx, &eax, &flags); >+ break; >+#endif > default: > printk_info(__FUNCTION__ ": Unsupport int #0x%x\n", > intnumber); >+#ifdef CONFIG_UNSUPPORTINT_RECOVER >+ unsupportint_recover(); >+#endif > break; > > >and that arch/i386/lib/vgabios.c and mainboard/via/epia-m/mainboard.c >respectively have the actual handler routines: > >@@ -145,6 +145,13 @@ > __asm__ (".text\n""real_mode_switch_end:\n"); > extern char real_mode_switch_end[]; > >+#ifdef CONFIG_UNSUPPORTINT_RECOVER >+void unsupportint_recover(void) >+{ >+ __asm__ __volatile__ ( " jmp vgarestart \n" ); >+} >+#endif >+ > >and > >@@ -92,3 +176,33 @@ > final_southbridge_fixup(); > } > >+int handleint21( unsigned long *edi, unsigned long *esi, unsigned long *ebp, >+ unsigned long *esp, unsigned long *ebx, unsigned >long *edx, >+ unsigned long *ecx, unsigned long *eax, unsigned >long *flags) >+{ >+int res=-1; >+ switch(*eax&0xffff) >+ { >+ case 0x5f19: >+ break; >+ case 0x5f18: >+ *eax=0x5f; >+ *ebx=0x15; // MCLK = 133, 32M frame buffer >+ res=0; >+ break; >+ case 0x5f02: >+ *eax=0x5f; >+ *ebx=0 | (3<<8); >+ *ecx=5 | (0<<8) | (0<<16); >+ res=0; >+ break; >+ case 0x5f0f: >+ *eax=0x5f; >+ *ebx=0; >+ *ecx=0; >+ *edx=0; >+ res=0; >+ break; >+ } >+ return res; >+} > > >NOTE: It's possible that you may have patch these in by hand as the >original diffs were from an older version of the codebase and things may >have changed since then. All the patch is ok and I get the CVS of 05 2003-July >A quick check is to make sure there are no *.rej files present which might >indicate a patch operation has failed. all files are patched >The diffs aren't large, so it's probably worthing checking them by hand to >make sure the patches have been properly applied. > >Cheers > >Ian > >At 09:31 03/12/2003, Santi Mirenna wrote: >>Hi to all, today i make EPIA-M 10000 rom image. i compile to have VGA and >>Filo, >>after apply patch of Dave Ashley and info from Takeshi about RAM ammount >>VGA now is found by the system but .... >>In attach you have the output log .... >>Can someone tell me where i wrong? >> >>Dave Ashley reply: >> >>You haven't applied all the patch, specifically the handler >>for the unsupported bios interrupts. >>This is the bug where it just gets into an endless loop >>of bios interrupts, so the program needs to exit the >>bios somehow. -Dave >> >>Hi , can some one tell me where to look .... >>i made the patch ....where to look Dave to know if the patch is ok ? >> >>Thanks. >> >>Santi Mirenna

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Re: Tyan S4880
by YhLu Dec. 2, 2003

Dec. 2, 2003

Eric, The Kernel is used 2.4.22 and I compiled it in ADM64 mode. The LAN device is Broadcom 5704 and driver should be tg3. The SCSI device (LSI SCSI 53c1030 -- onboard and Adaptec 29320 addon card) all can not be initialized in Linux Kernal. Regards YH.

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答复: Tyan S4880
by YhLu Dec. 2, 2003

Dec. 2, 2003

>> 3. southbridge/amd/amd8131/amd8131_bridge.c: update ioapic_anable to enable >> PCI-X MASTER Mode. >Why is this necessary? Previously it has been the policy to not set >the master enables any more than is necessary for proper operation >of the devices. Unless I am mistaken not setting the master enables is >very much in spec for pci devices. Eric, Otherwise I can not use LAN and SCSI devices in PCI-X in Linux. For Broadcom NIC, I can not ifconfig and ping. For SCSI, I just can not get through the SCSI initialize in Linux kernel. YH.

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答复: Tyan S4880
by YhLu Dec. 2, 2003

Dec. 2, 2003

It should work for quertet. I compare the schematic of S4880 and quartet, and the SPD_ROM access part is the same. You need to update raminit.h and amd8111_early_sumbus.c too. YH. -----邮件原件----- 发件人: Stefan Reinauer [mailto:stepan@suse.de] 发送时间: 2003年12月2日 6:16 收件人: YhLu 抄送: ron minnich; ebiederman(a)lnxi.com; linuxbios(a)clustermatic.org 主题: Re: Tyan S4880 * YhLu <YhLu(a)tyan.com> [031202 02:05]: > With update 1 and 2, you can get ride of FAKE_SPD_ROM. > You need to change some lines in auto.c for quartet. > 1. I2C HUB address: 0x30 --> 0x18, > 2. RC0-> (1<<1)<<8, RC1-> (1<<2)<<8, RC2-> (1<<3)<<8, RC3-> (1<<4)<<8. Tried this, doesn't work. I end up with 0KB memory detected on each CPU. Is it only my Quartets that behave like this? Stefan -- Stefan Reinauer, SUSE LINUX AG Teamleader Architecture Development

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LinuxBIOS on laptop - someone can create a custom mainboard!
by Miernik Dec. 2, 2003

Dec. 2, 2003

I think you will be interested in this project: http://www.technoir.nu/libretto/list/2003/msg01557.html Here he writes "Price really depends on what ICs and bios used": http://www.technoir.nu/libretto/list/2003/msg01564.html This would be a really exiting to have a complete custome made mainboard for a Toshiba Libretto laptop with LinuxBIOS. -- Miernik ________________________ jabber:miernik@amessage.info ___________________/__ tel: +48608233394 __/ mailto:miernik@ctnet.pl Sing a declaration against US invasion in Iraq: http://www.moveon.org/declaration/

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LINUXBIOS can boot any variety OS
by mount me Dec. 1, 2003

Dec. 1, 2003

Hi linuxbiosians, Heard and Read that Windows 2000 can be booted using Linuxbios. Keeeeeeen and Interested in entering linuxbios. Could i get the list of OS's booted using LINUXBIOS and a brief explanation document along with it ? or links plz.... I am stilll looking for a motherboard in Chennai,INDIA Has anyone tried linuxbios in CHENNAI,INDIA ? need your support to start linuxbios with. Regards, karthik bala guru ________________________________________________________________________ Yahoo! India Promos: Win TVs, Bikes, DVD players & more! Go to http://in.promos.yahoo.com

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v1: epia-m: irq_tables.c, mainboard.c
by Niki Waibel Dec. 1, 2003

Dec. 1, 2003

i think we need a new thread for the ``intel dual netwokcard problem on epia-m'' topic. facts (correct me if i am wrong!): * intel dual eth nic is not working with linuxbios (2003-10-24). * it can be plugged into the pci slot (00:14.0) of the epia-m. * the dual nic has a pci-to-pci bridge on the card. * that bridge assignes pci bus 2 (0=internal, 1=vga/agp?) * the 2 nics on the card assign: 02:04.0 and 02:05.0 * linuxbios detects the bus/bridge and also sees the 2 nic. !!* linuxbios does not assign irqs to the nics. * default (2003-10-24) linuxbios src/mainboard/via/epia-m/irq_tables.c: === /* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM */ #include <arch/pirq_routing.h> const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32+16*5, /* there can be total 5 devices on the bus */ 0, /* Where the interrupt router lies (bus) */ 0, /* Where the interrupt router lies (dev) */ 0x1c20, /* IRQs devoted exclusively to PCI usage */ 0, /* Vendor */ 0, /* Device */ 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ #if 0 0x58, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this st ructu re (including checksum) */ { {0,0xa0, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0}, {0,0x98, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x2, 0}, {0,0x50, {{0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}}, 0x3, 0}, {0,0x68, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0}, {0,0x8, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0, 0}, {0x50,0, {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, 0, 0} } #else 0xac, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this st ructu re (including checksum) */ { /* ethernet */ {0,0x90, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0}, /* usb */ {0,0x80, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0}, /* pci */ {0,0xa0, {{0x1, 0xdeb8}, {0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}}, 0x3, 0}, /* audio */ {0,0x8d, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x0, 0}, /* 1394 */ {0,0x68, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0} } #endif }; === * if i run util/getpir/getpir (with the dual eth nic board) i get: === /* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM */ #include <arch/pirq_routing.h> const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32+16*5, /* there can be total 5 devices on the bus */ 0, /* Where the interrupt router lies (bus) */ 0, /* Where the interrupt router lies (dev) */ 0x1c00, /* IRQs devoted exclusively to PCI usage */ 0, /* Vendor */ 0, /* Device */ 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x78, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this st ructu re (including checksum) */ { {0,0xa0, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0}, {0,0x98, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x2, 0}, {0,0x50, {{0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}}, 0x3, 0}, {0,0x68, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0}, {0,0x8, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0, 0}, } }; === * it does not help using the new irq_tables.c. * i had to modify src/mainboard/via/epia-m/mainboard.c in addition to get it running. --> basically add: ``pci_assign_irqs(2, 0x4, dualenetaIrq); pci_assign_irqs(2, 0x5, dualenetbIrq);'' in addition i had to play with the irq lists. questions: * what do the strange numbers in my new irq_table.c mean? * if everything is hardcoded in mainboard.c -- what is irq_table.c for? * is it possible that all this is hardcoded in mainboard.c for epia/epia-m only, but not for other boards? other boards use irq_table.c to assign interrupts? * if you plug a card to the pci slot linuxbios seems to detect everything (devices/bridges/devices behind bridges). why cannot we say: ok there is irq 5, 10, 11 and 12. assign that 4 irqs to all devices which were detected in the previous stage. this must be the way the regular bios does it... * when booting the epia-m with the std (award) bios and using the getpir prg -> the resulting irq_table.c does not work either. is it just ignored by the epia-m setup, or what is it actually for? niki

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automatic power on possible?
by thomas＠wehrspann.de Dec. 1, 2003

Dec. 1, 2003

Most modern motherboards supports the timer based automatic power on via BIOS settings. With linuxbios this is not(?) possible. There is a program for linux, called nvram-wakeup, to set the wakeup time in nvram or rtc. But especially for the K7SEM or EPIA boards a reboot is needed after it, so the wakeup settings can take effect. Does anyone know what the BIOS is doing what linuxbios does not? Perhaps it can be done in a program? Thanks Thomas Wehrspann

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Re: Linuxbios with Diskonchip?
by Devi Priya Dec. 1, 2003

Dec. 1, 2003

Hi, I have Diskonchip millennium MD2800 (8 MB capacity) and Microns SDRAM capacity (256 Mbits). Then the flash is to be mapped into the physical address 0xFFFFFFFF-0xFF800000. SDRAM is to mapped into the physical address 0x00000000-0xFE000000. Is this mapping correct? >From: ron minnich <rminnich(a)lanl.gov> >To: Devi Priya <ijpriya(a)hotmail.com> >CC: gizara(a)cox.net, <linuxbios(a)clustermatic.org> >Subject: Re: Linuxbios with Diskonchip? >Date: Sat, 29 Nov 2003 18:35:20 -0700 (MST) > >On Fri, 28 Nov 2003, Devi Priya wrote: > > > Hi, > > > > I am using Diskonchip millennium with boot capability. I just want >to > > know if diskonchip is mapped to the high order physical address (at >reset) > > and is any remapping is done later? > >usually mapped at flash address, right? 0xf0000 and 0xfff00000 > >ron > >_______________________________________________ >Linuxbios mailing list >Linuxbios(a)clustermatic.org >http://www.clustermatic.org/mailman/listinfo/linuxbios _________________________________________________________________ >From the hottest toys to tips on keeping fit this winter, youll find a range of helpful holiday info here. http://special.msn.com/network/happyholidays.armx

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