Danomi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41648 ) Change subject: mb/google/poppy: Create sylas variant ...................................................................... mb/google/poppy: Create sylas variant Create new variant and build for sylas. BUG=b:155315878 TEST=FW_NAME="sylas" emerge-nami coreboot chromeos-bootimage Change-Id: Ifa43b72d4e1f61a50ab624ad8bd2938c3a1ef809 Signed-off-by: Danomi Lin <lin.danomi@inventec.corp-partner.google.com> --- A src/mainboard/google/poppy/variants/sylas/Makefile.inc A src/mainboard/google/poppy/variants/sylas/bard-data.vbt A src/mainboard/google/poppy/variants/sylas/devicetree.cb A src/mainboard/google/poppy/variants/sylas/gpio.c A src/mainboard/google/poppy/variants/sylas/include/variant/acpi/dptf.asl A src/mainboard/google/poppy/variants/sylas/include/variant/ec.h A src/mainboard/google/poppy/variants/sylas/include/variant/gpio.h A src/mainboard/google/poppy/variants/sylas/include/variant/sku.h A src/mainboard/google/poppy/variants/sylas/mainboard.c A src/mainboard/google/poppy/variants/sylas/memory.c A src/mainboard/google/poppy/variants/sylas/nhlt.c A src/mainboard/google/poppy/variants/sylas/smihandler.c 12 files changed, 1,860 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/41648/1 diff --git a/src/mainboard/google/poppy/variants/sylas/Makefile.inc b/src/mainboard/google/poppy/variants/sylas/Makefile.inc new file mode 100644 index 0000000..dc80357 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/Makefile.inc @@ -0,0 +1,45 @@ + +# IMPORTANT!! When a new memory SPD is added here, please ensure that ddp_bitmap +# is correctly updated in memory.c to indicate if memory id is using DDP. +SPD_SOURCES = empty_ddr4 # 0b0000 +SPD_SOURCES += micron_dimm_MT40A256M16GE-083E # 0b0001 +SPD_SOURCES += samsung_dimm_K4A8G165WB-BCRC # 0b0010 +SPD_SOURCES += hynix_dimm_H5AN4G6NBJR-UHC # 0b0011 +SPD_SOURCES += hynix_dimm_H5ANAG6NAMR-UHC # 0b0100 +SPD_SOURCES += hynix_dimm_H5ANAG6NCMR-VKC # 0b0101 +SPD_SOURCES += hynix_dimm_H5AN8G6NAFR-UHC # 0b0110 +SPD_SOURCES += samsung_dimm_K4A4G165WE-BCRC # 0b0111 +SPD_SOURCES += samsung_dimm_K4A8G165WC-BCTD # 0b1000 +SPD_SOURCES += samsung_dimm_K4AAG165WB-MCRC # 0b1001 +SPD_SOURCES += hynix_dimm_H5AN4G6NAFR-UHC # 0b1010 +SPD_SOURCES += micron_dimm_MT40A256M16LY-075F # 0b1011 +SPD_SOURCES += micron_dimm_MT40A512M16TB-062EJ # 0b1100 +SPD_SOURCES += micron_dimm_MT40A1G16KNR-075E # 0b1101 +SPD_SOURCES += micron_dimm_MT40A512M16LY-075E # 0b1110 +SPD_SOURCES += hynix_dimm_H5AN8G6NCJR-VKC # 0b1111 + +# Used when PCH_MEM_CONFIG4 = 1 (LPDDR3) +SEC_SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107 # 0b0000 +SEC_SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b0001 +SEC_SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR-NUD # 0b0010 +SEC_SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD # 0b0011 +SEC_SPD_SOURCES += micron_dimm_MT52L1G32D4PG-107 # 0b0100 +SEC_SPD_SOURCES += hynix_dimm_H9CCNNNCLGALAR-NUD # 0b0101 +SEC_SPD_SOURCES += nayna_dimm_NT6CL256T32CM-H1 # 0b0110 + +bootblock-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c +ramstage-y += nhlt.c +ramstage-y += mainboard.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +# Add OEM ID table +cbfs-files-y += oem.bin +oem.bin-file := $(call strip_quotes,$(CONFIG_OEM_BIN_FILE)) +oem.bin-type := raw + +$(call add_vbt_to_cbfs, vbt-bard.bin, bard-data.vbt) diff --git a/src/mainboard/google/poppy/variants/sylas/bard-data.vbt b/src/mainboard/google/poppy/variants/sylas/bard-data.vbt new file mode 100644 index 0000000..cdaca6a --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/bard-data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/sylas/devicetree.cb b/src/mainboard/google/poppy/variants/sylas/devicetree.cb new file mode 100644 index 0000000..8325261 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/devicetree.cb @@ -0,0 +1,493 @@ +chip soc/intel/skylake + + # Deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "1" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # Enable DPTF + register "dptf_enable" = "1" + + # Enable S0ix + register "s0ix_enable" = "1" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "3" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "SaImguEnable" = "0" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "0" + register "IshEnable" = "0" + register "PttSwitch" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "SaGv" = "3" + register "SerialIrqConfigSirqEnable" = "1" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" + register "VmxEnable" = "1" + + # Intersil VR c-state issue workaround + # send VR mailbox command for IA/GT/SA rails + register "IslVrCmd" = "2" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 2A | 2A | 2A | 2A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 11 | 2.4 | 3.1 | 3.1 | + #| DcLoadline | 10 | 2.46 | 3.1 | 3.1 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(2), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 1100, + .dc_loadline = 1000, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(2), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 240, + .dc_loadline = 246, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(2), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(2), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Root port 4 (x1) + # PcieRpEnable: Enable root port + # PcieRpClkReqSupport: Enable CLKREQ# + # PcieRpClkReqNumber: Uses SRCCLKREQ1# + # PcieRpClkSrcNumber: Uses 1 + # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting + # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism + register "PcieRpEnable[3]" = "1" + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "1" + register "PcieRpClkSrcNumber[3]" = "1" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" + + # Root port 5 (x4) + # PcieRpEnable: Enable root port + # PcieRpClkReqSupport: Enable CLKREQ# + # PcieRpClkReqNumber: Uses SRCCLKREQ3# + # PcieRpClkSrcNumber: Uses 3 + # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting + # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + + # Root port 9 (x2) + # PcieRpEnable: Enable root port + # PcieRpClkReqSupport: Enable CLKREQ# + # PcieRpClkReqNumber: Uses SRCCLKREQ2# + # PcieRpClkSrcNumber: Uses 2 + # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting + # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "2" + register "PcieRpClkSrcNumber[8]" = "2" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_LONG(OC1)" # Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Port + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Card reader + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WiFi + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Rear camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Front camera + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader + + # Touchscreen + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" + + # Trackpad + register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" + + # Pen + register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" + + # Audio + register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Touchscreen | + #| I2C1 | Trackpad | + #| I2C2 | Pen | + #| I2C3 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 90, + .sda_hold = 36, + }, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 90, + .sda_hold = 36, + }, + .early_init = 1, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 100, + .sda_hold = 36, + }, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 195, + .scl_hcnt = 90, + .sda_hold = 36, + }, + }, + }" + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoPci, + [PchSerialIoIndexSpi1] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + register "speed_shift_enable" = "1" + + register "tcc_offset" = "3" # TCC of 97C + register "psys_pmax" = "101" + + # PCH Trip Temperature in degree C + register "pch_trip_temp" = "75" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 on end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "reset_delay_ms" = "20" + register "reset_off_delay_ms" = "2" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" + register "enable_delay_ms" = "5" + register "enable_off_delay_ms" = "100" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C3)" + register "stop_off_delay_ms" = "2" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "reset_delay_ms" = "1" + register "reset_off_delay_ms" = "2" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "100" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C3)" + register "stop_delay_ms" = "20" + register "stop_off_delay_ms" = "2" + device i2c 39 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYTS7817"" + register "generic.desc" = ""Synaptics Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" + register "generic.enable_delay_ms" = "45" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 20 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)" + register "wake" = "GPE0_DW2_16" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)" + register "generic.wake" = "GPE0_DW2_16" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # I2C #1 + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM005C"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D3)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "generic.wake" = "GPE0_DW2_01" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_E8)" + register "key.dev_name" = ""INST"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_insert"" + device generic 0 on end + end + end # I2C #2 + device pci 15.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" + register "sdmode_delay" = "5" + device generic 0 on end + end + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1A on end + end + end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 off end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW2_22" # Wake pin = GPP_E22 + device pci 00.0 on end + end + end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" + device spi 0 on end + end + end # GSPI #0 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B0_IRQ)" + register "wake" = "GPE0_DW0_01" # GPP_B1 + device spi 0 on end + end # FPMCU + end # GSPI #1 + device pci 1e.4 on end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/poppy/variants/sylas/gpio.c b/src/mainboard/google/poppy/variants/sylas/gpio.c new file mode 100644 index 0000000..42f84f5 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/gpio.c @@ -0,0 +1,490 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <variant/sku.h> + +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { + /* A0 : RCIN# ==> NC(TP22) */ + PAD_CFG_NC(GPP_A0), + /* A1 : ESPI_IO0 */ + /* A2 : ESPI_IO1 */ + /* A3 : ESPI_IO2 */ + /* A4 : ESPI_IO3 */ + /* A5 : ESPI_CS# */ + /* A6 : SERIRQ ==> NC(TP24) */ + PAD_CFG_NC(GPP_A6), + /* A7 : PIRQA# ==> NC(TP15) */ + PAD_CFG_NC(GPP_A7), + /* A8 : CLKRUN# ==> NC(TP23) */ + PAD_CFG_NC(GPP_A8), + /* A9 : ESPI_CLK */ + /* A10 : CLKOUT_LPC1 ==> NC */ + PAD_CFG_NC(GPP_A10), + /* A11 : PME# ==> NC(TP46) */ + PAD_CFG_NC(GPP_A11), + /* A12 : BM_BUSY# ==> NC */ + PAD_CFG_NC(GPP_A12), + /* A13 : SUSWARN# ==> SUSWARN#_R */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + /* A14 : ESPI_RESET# */ + /* A15 : SUSACK# ==> SUSACK# */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : SD_1P8_SEL ==> NC */ + PAD_CFG_NC(GPP_A16), + /* A17 : SD_PWR_EN# ==> NC */ + PAD_CFG_NC(GPP_A17), + /* A18 : ISH_GP0 ==> EMMC_RST#L_R_SOC (unstuffed) */ + PAD_CFG_NC(GPP_A18), + /* A19 : ISH_GP1 ==> NC */ + PAD_CFG_NC(GPP_A19), + /* A20 : ISH_GP2 ==> NC */ + PAD_CFG_NC(GPP_A20), + /* A21 : ISH_GP3 ==> NC */ + PAD_CFG_NC(GPP_A21), + /* A22 : ISH_GP4 ==> NC */ + PAD_CFG_NC(GPP_A22), + /* A23 : ISH_GP5 ==> PCH_SPK_EN */ + PAD_CFG_GPO(GPP_A23, 1, DEEP), + + /* B0 : CORE_VID0 ==> NC(T3) */ + PAD_CFG_NC(GPP_B0), + /* B1 : CORE_VID1 ==> NC(T4) */ + PAD_CFG_NC(GPP_B1), + /* B2 : VRALERT# ==> NC */ + PAD_CFG_NC(GPP_B2), + /* B3 : CPU_GP2 ==> TOUCHSCREEN_RST# */ + PAD_CFG_GPO(GPP_B3, 0, DEEP), + /* B4 : CPU_GP3 ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* B5 : SRCCLKREQ0# ==> NC */ + PAD_CFG_NC(GPP_B5), + /* B6 : SRCCLKREQ1# ==> CLKREQ_PCIE#1 */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : SRCCLKREQ2# ==> CLKREQ_PCIE#2 */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : SRCCLKREQ3# ==> CLKREQ_PCIE#3 */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : SRCCLKREQ4# ==> WLAN_PE_RST_AP */ + PAD_CFG_GPO(GPP_B9, 0, RSMRST), + /* B10 : SRCCLKREQ5# ==> NC */ + PAD_CFG_NC(GPP_B10), + /* B11 : EXT_PWR_GATE# ==> NC */ + PAD_CFG_NC(GPP_B11), + /* B12 : SLP_S0# ==> PM_SLP_R_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST#_PCH */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : SPKR ==> EC_GPP_B14 (rsvd for later) */ + PAD_CFG_NC(GPP_B14), + /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS# */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* B19 : GSPI1_CS# ==> NC(TP26) */ + PAD_CFG_NC(GPP_B19), + /* B20 : GSPI1_CLK ==> NC(TP27) */ + PAD_CFG_NC(GPP_B20), + /* B21 : GSPI1_MISO ==> NC(TP28) */ + PAD_CFG_NC(GPP_B21), + /* B22 : GSPI1_MOSI ==> NC(TP30) */ + PAD_CFG_NC(GPP_B22), + /* B23 : SM1ALERT# ==> SOC_SML1ALERT# (unstuffed) */ + PAD_CFG_NC(GPP_B23), + + /* C0 : SMBCLK ==> SOC_SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA ==> SOC_SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C2 : SMBALERT# ==> NC(TP917) */ + PAD_CFG_NC(GPP_C2), + /* C4 : SML0DATA ==> NC */ + PAD_CFG_NC(GPP_C4), + /* C5 : SML0ALERT# ==> SOC_SML0ALERT# (unstuffed) */ + PAD_CFG_NC(GPP_C5), + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + /* C7 : SM1DATA ==> TRACKPAD_DISABLE# */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C8 : UART0_RXD ==> NC(TP31) */ + PAD_CFG_NC(GPP_C8), + /* C9 : UART0_TXD ==> NC(TP32) */ + PAD_CFG_NC(GPP_C9), + /* C10 : UART0_RTS# ==> EN_PP3300_DX_CAM1 */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM2 */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C12 : UART1_RXD ==> PCH_MEM_CONFIG0 */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), + /* C13 : UART1_TXD ==> PCH_MEM_CONFIG1 */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), + /* C14 : UART1_RTS# ==> PCH_MEM_CONFIG2 */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), + /* C15 : UART1_CTS# ==> PCH_MEM_CONFIG3 */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), + /* C16 : I2C0_SDA ==> I2C_0_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> I2C_0_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> I2C_1_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> I2C_1_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : UART2_RTS# ==> NC(TP926) */ + PAD_CFG_NC(GPP_C22), + /* C23 : UART2_CTS# ==> PCH_WP */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + + /* D0 : SPI1_CS# ==> DDR_CHB_EN (for debugging) */ + PAD_CFG_NC(GPP_D0), + /* D1 : SPI1_CLK ==> PEN_IRQ# */ + PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), + /* D2 : SPI1_MISO ==> PEN_PDCT# */ + PAD_CFG_GPI_APIC(GPP_D2, NONE, PLTRST), + /* D3 : SPI1_MOSI ==> PEN_RST# */ + PAD_CFG_GPO(GPP_D3, 0, DEEP), + /* D4 : FASHTRIG ==> NC */ + PAD_CFG_NC(GPP_D4), + /* D5 : ISH_I2C0_SDA ==> NC */ + PAD_CFG_NC(GPP_D5), + /* D6 : ISH_I2C0_SCL ==> NC */ + PAD_CFG_NC(GPP_D6), + /* D7 : ISH_I2C1_SDA ==> NC */ + PAD_CFG_NC(GPP_D7), + /* D8 : ISH_I2C1_SCL ==> NC */ + PAD_CFG_NC(GPP_D8), + /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ + PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), + /* D10 : ISH_SPI_CLK ==> SINGLE_CHANNEL */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), + /* D11 : ISH_SPI_MISO ==> DCI_CLK (debug header) */ + PAD_CFG_NC(GPP_D11), + /* D12 : ISH_SPI_MOSI ==> DCI_DATA (debug header) */ + PAD_CFG_NC(GPP_D12), + /* D13 : ISH_UART0_RXD ==> H1_BOOT_UART_RX (unstuffed) */ + PAD_CFG_NC(GPP_D13), + /* D14 : ISH_UART0_TXD ==> H1_BOOT_UART_TX (unstuffed) */ + PAD_CFG_NC(GPP_D14), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_CFG_NC(GPP_D15), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_CFG_NC(GPP_D16), + /* D18 : DMIC_DATA1 ==> SOC_DMIC_DATA1_R */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* D19 : DMIC_CLK0 ==> SOC_DMIC_CLK0_R */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* D20 : DMIC_DATA0 ==> SOC_DMIC_DATA0_R */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* D21 : SPI1_IO2 ==> DDR_CHA_EN (debugging) */ + PAD_CFG_NC(GPP_D21), + /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */ + PAD_CFG_GPO(GPP_D22, 1, DEEP), + /* D23 : I2S_MCLK ==> I2S_1_MCLK */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + + /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + /* E1 : SATAXPCIE1 ==> EMR_GARAGE_DET# - for wake event */ + PAD_CFG_GPI_ACPI_SCI(GPP_E1, NONE, DEEP, INVERT), + /* E2 : SATAXPCIE2 ==> WLAN_OFF# */ + PAD_CFG_GPO(GPP_E2, 1, DEEP), + /* E3 : CPU_GP0 ==> TRACKPAD_INT# */ + PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST), + /* E4 : SATA_DEVSLP0 ==> BT_OFF# */ + PAD_CFG_GPO(GPP_E4, 1, DEEP), + /* E5 : SATA_DEVSLP1 ==> NC(TP928) */ + PAD_CFG_NC(GPP_E5), + /* E6 : SATA_DEVSLP2 ==> NC(TP915) */ + PAD_CFG_NC(GPP_E6), + /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT# */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + /* E8 : SATALED# ==> EMR_GARAGE_DET# - for notification */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E8, NONE, DEEP), + /* E9 : USB2_OCO# ==> USB_C0_OC# */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : USB2_OC1# ==> USB_C1_OC# */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + /* E11 : USB2_OC2# ==> USB_A0_OC# */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + /* E12 : USB2_OC3# ==> NC */ + PAD_CFG_NC(GPP_E12), + /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + /* E15 : DDPD_HPD2 ==> DDR_SEL */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E16 : DDPE_HPD3 ==> TRACKPAD_INT# */ + PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, INVERT), + /* E17 : EDP_HPD ==> EDP_HPD */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + /* E18 : DDPB_CTRLCLK ==> SOC_DP1_CTRL_CLK */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + /* E19 : DDPB_CTRLDATA ==> SOC_DP1_CTRL_DATA */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + /* E20 : DDPC_CTRLCLK ==> SOC_DP2_CTRL_CLK */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* E21 : DDPC_CTRLDATA ==> SOC_DP2_CTRL_DATA */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* E22 : DDPD_CTRLCLK ==> WLAN_PCIE_WAKE# */ + PAD_CFG_GPI_ACPI_SCI(GPP_E22, NONE, DEEP, INVERT), + /* E23 : DDPD_CTRLDATA ==> NC(TP17)*/ + PAD_CFG_NC(GPP_E23), + + /* The next 4 pads are for bit banging the amplifiers, default to I2S */ + /* F0 : I2S2_SCLK ==> I2S2_2_BCLK_R */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), + /* F1 : I2S2_SFRM ==> I2S2_2_FS_LRC */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), + /* F2 : I2S2_TXD ==> I2S2_2_TX_DAC */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), + /* F3 : I2S2_RXD ==> NC */ + PAD_CFG_NC(GPP_F3), + /* F4 : I2C2_SDA ==> I2C_2_SDA */ + PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), + /* F5 : I2C2_SCL ==> I2C_2_SCL */ + PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), + /* F6 : I2C3_SDA ==> I2C_3_SDA */ + PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), + /* F7 : I2C3_SCL ==> I2C_3_SCL */ + PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), + /* F8 : I2C4_SDA ==> I2C_4_SDA (unstuffed) */ + PAD_CFG_NC(GPP_F8), + /* F9 : I2C4_SCL ==> I2C_4_SCL (unstuffed) */ + PAD_CFG_NC(GPP_F9), + /* F10 : I2C5_SDA ==> NC */ + PAD_CFG_NC(GPP_F10), + /* F11 : I2C5_SCL ==> NC */ + PAD_CFG_NC(GPP_F11), + /* F12 : EMMC_CMD ==> EMMC_1_CMD */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA0 ==> EMMC_1_D0 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA1 ==> EMMC_1_D1 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA2 ==> EMMC_1_D2 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA3 ==> EMMC_1_D3 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA4 ==> EMMC_1_D4 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA5 ==> EMMC_1_D5 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA6 ==> EMMC_1_D6 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_DATA7 ==> EMMC_1_D7 */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_RCLK ==> EMMC_1_RCLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_CLK ==> EMMC_1_CLK */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : RSVD ==> NC */ + PAD_CFG_NC(GPP_F23), + + /* G0 : SD_CMD ==> NC */ + PAD_CFG_NC(GPP_G0), + /* G1 : SD_DATA0 ==> NC */ + PAD_CFG_NC(GPP_G1), + /* G2 : SD_DATA1 ==> NC */ + PAD_CFG_NC(GPP_G2), + /* G3 : SD_DATA2 ==> NC */ + PAD_CFG_NC(GPP_G3), + /* G4 : SD_DATA3 ==> NC */ + PAD_CFG_NC(GPP_G4), + /* G5 : SD_CD# ==> NC */ + PAD_CFG_NC(GPP_G5), + /* G6 : SD_CLK ==> NC */ + PAD_CFG_NC(GPP_G6), + /* G7 : SD_WP ==> SD_WP (not needed) */ + PAD_CFG_NC(GPP_G7), + + /* GPD0: BATLOW# ==> PCH_BATLOW# */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R# */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_R_BTN# */ + PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + /* GPD4: SLP_S3# ==> SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: SLP_S4# ==> SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: SLP_A# ==> NC(TP44) */ + PAD_CFG_NC(GPD6), + /* GPD7: RSVD ==> NC */ + PAD_CFG_NC(GPD7), + /* GPD8: SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: SLP_WLAN# ==> NC(TP41) */ + PAD_CFG_NC(GPD9), + /* GPD10: SLP_S5# ==> NC(TP38) */ + PAD_CFG_NC(GPD10), + /* GPD11: LANPHYC ==> NC */ + PAD_CFG_NC(GPD11), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS# */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* Ensure UART pins are in native mode for H1. */ + /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + + /* C23 : UART2_CTS# ==> PCH_WP */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + + /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + + /* D10 : ISH_SPI_CLK ==> SINGLE_CHANNEL */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, 20K_PD, DEEP), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct pad_config nami_default_sku_gpio_table[] = { + /* D17 : DMIC_CLK1 ==> SOC_DMIC_CLK1 */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ + PAD_CFG_GPO(GPP_C3, 0, DEEP), +}; + +static const struct pad_config no_dmic1_sku_gpio_table[] = { + /* D17 : DMIC_CLK1 ==> NC */ + PAD_CFG_NC(GPP_D17), + /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ + PAD_CFG_GPO(GPP_C3, 0, DEEP), +}; + +static const struct pad_config pantheon_gpio_table[] = { + /* D17 : DMIC_CLK1 ==> NC */ + PAD_CFG_NC(GPP_D17), + /* C3 : SML0CLK ==> NC */ + PAD_CFG_NC(GPP_C3), +}; + +static const struct pad_config fpmcu_gpio_table[] = { + /* B0 : CORE_VID0 ==> FPMCU_INT_L */ + PAD_CFG_GPI_APIC(GPP_B0, NONE, DEEP), + /* B1 : CORE_VID1 ==> FPMCU_INT_L */ + PAD_CFG_GPI_ACPI_SCI(GPP_B1, 20K_PU, DEEP, INVERT), + /* B11 : EXT_PWR_GATE# ==> PCH_FP_PWR_EN */ + PAD_CFG_GPO(GPP_B11, 1, DEEP), + /* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS# */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_SPI_FP_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_SPI_FP_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI ==> PCH_SPI_FP_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ + PAD_CFG_GPO(GPP_C3, 0, DEEP), + /* C9 : UART0_TXD ==> FP_RST_ODL */ + PAD_CFG_GPO(GPP_C9, 1, DEEP), + /* D5 : ISH_I2C0_SDA ==> FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_D5, 0, DEEP), + /* D17 : DMIC_CLK1 ==> NC */ + PAD_CFG_NC(GPP_D17), +}; + +const struct pad_config *variant_sku_gpio_table(size_t *num) +{ + uint32_t sku_id = variant_board_sku(); + const struct pad_config *board_gpio_tables; + switch (sku_id) { + case SKU_0_VAYNE: + case SKU_1_VAYNE: + case SKU_2_VAYNE: + case SKU_0_SONA: + case SKU_1_SONA: + case SKU_0_SYNDRA: + case SKU_1_SYNDRA: + case SKU_2_SYNDRA: + case SKU_3_SYNDRA: + case SKU_4_SYNDRA: + case SKU_5_SYNDRA: + case SKU_6_SYNDRA: + case SKU_7_SYNDRA: + case SKU_3_PANTHEON: + case SKU_4_PANTHEON: + *num = ARRAY_SIZE(no_dmic1_sku_gpio_table); + board_gpio_tables = no_dmic1_sku_gpio_table; + break; + case SKU_0_PANTHEON: + case SKU_1_PANTHEON: + case SKU_2_PANTHEON: + *num = ARRAY_SIZE(pantheon_gpio_table); + board_gpio_tables = pantheon_gpio_table; + break; + case SKU_0_EKKO: + case SKU_1_EKKO: + case SKU_2_EKKO: + case SKU_3_EKKO: + case SKU_4_EKKO: + case SKU_5_EKKO: + case SKU_6_EKKO: + case SKU_7_EKKO: + case SKU_0_BARD: + case SKU_1_BARD: + case SKU_2_BARD: + case SKU_3_BARD: + case SKU_4_BARD: + case SKU_5_BARD: + case SKU_6_BARD: + case SKU_7_BARD: + *num = ARRAY_SIZE(fpmcu_gpio_table); + board_gpio_tables = fpmcu_gpio_table; + break; + default: + *num = ARRAY_SIZE(nami_default_sku_gpio_table); + board_gpio_tables = nami_default_sku_gpio_table; + break; + } + return board_gpio_tables; +} diff --git a/src/mainboard/google/poppy/variants/sylas/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/sylas/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..2b3bd25 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/include/variant/acpi/dptf.asl @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 125 +#define DPTF_CPU_ACTIVE_AC0 87 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal_Sensor_Remote_CPU" +#define DPTF_TSR0_PASSIVE 75 +#define DPTF_TSR0_CRITICAL 125 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 39 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal_Sensor_Remote_PMIC" +#define DPTF_TSR1_PASSIVE 75 +#define DPTF_TSR1_CRITICAL 125 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Thermal_Sensor_Remote_CPU" +#define DPTF_TSR2_PASSIVE 75 +#define DPTF_TSR2_CRITICAL 125 +#define DPTF_TSR2_ACTIVE_AC0 50 +#define DPTF_TSR2_ACTIVE_AC1 47 +#define DPTF_TSR2_ACTIVE_AC2 45 +#define DPTF_TSR2_ACTIVE_AC3 42 +#define DPTF_TSR2_ACTIVE_AC4 39 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +#ifdef DPTF_ENABLE_FAN_CONTROL +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + } +}) +#endif + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 1, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR0 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 1, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR1 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 1, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR2 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 1, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 44000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/poppy/variants/sylas/include/variant/ec.h b/src/mainboard/google/poppy/variants/sylas/include/variant/ec.h new file mode 100644 index 0000000..a5a0196 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/include/variant/ec.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +#include <variant/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +/* Enable Tablet switch */ +#define EC_ENABLE_TABLET_EVENT +#define EC_ENABLE_TBMC_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/google/poppy/variants/sylas/include/variant/gpio.h b/src/mainboard/google/poppy/variants/sylas/include/variant/gpio.h new file mode 100644 index 0000000..98450f6 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/include/variant/gpio.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C13 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_C15 +#define GPIO_MEM_CONFIG_4 GPP_E15 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/poppy/variants/sylas/include/variant/sku.h b/src/mainboard/google/poppy/variants/sylas/include/variant/sku.h new file mode 100644 index 0000000..d6786dc --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/include/variant/sku.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_SKU_H__ +#define __MAINBOARD_SKU_H__ + +#define SKU_UNKNOWN 0xFFFFFFFF +#define SKU_0_NAMI 0x3A7B +#define SKU_0_VAYNE 0x3A67 +#define SKU_1_VAYNE 0x3A63 +#define SKU_2_VAYNE 0x3A7F +#define SKU_0_PANTHEON 0x3F63 +#define SKU_1_PANTHEON 0x3F67 +#define SKU_2_PANTHEON 0x3F62 +#define SKU_3_PANTHEON 0xBF63 +#define SKU_4_PANTHEON 0xBF62 +#define SKU_0_SONA 0x3AE2 +#define SKU_1_SONA 0x3AE3 +#define SKU_0_SYLAS 0x39E2 +#define SKU_1_SYLAS 0x39E3 +#define SKU_0_AKALI 0x29E1 +#define SKU_1_AKALI 0x2861 +#define SKU_0_AKALI360 0x2BE7 +#define SKU_1_AKALI360 0x2A67 +#define SKU_0_SYNDRA 0x2BC63 +#define SKU_1_SYNDRA 0x2BC62 +#define SKU_2_SYNDRA 0x2BC61 +#define SKU_3_SYNDRA 0X2BC60 +#define SKU_4_SYNDRA 0X6BC63 +#define SKU_5_SYNDRA 0X6BC62 +#define SKU_6_SYNDRA 0X6BC61 +#define SKU_7_SYNDRA 0X6BC60 +#define SKU_0_EKKO 0x10118E3 +#define SKU_1_EKKO 0x10018E3 +#define SKU_2_EKKO 0x10118E1 +#define SKU_3_EKKO 0X10018E1 +#define SKU_4_EKKO 0x10118E2 +#define SKU_5_EKKO 0x10018E2 +#define SKU_6_EKKO 0x10118E0 +#define SKU_7_EKKO 0x10018E0 +#define SKU_0_BARD 0x1019CE3 +#define SKU_1_BARD 0x1009CE3 +#define SKU_2_BARD 0x1019CE1 +#define SKU_3_BARD 0X1009CE1 +#define SKU_4_BARD 0X1009CE0 +#define SKU_5_BARD 0X1009CE2 +#define SKU_6_BARD 0x1019CE0 +#define SKU_7_BARD 0x1019CE2 + +#endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/poppy/variants/sylas/mainboard.c b/src/mainboard/google/poppy/variants/sylas/mainboard.c new file mode 100644 index 0000000..dde74c7 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/mainboard.c @@ -0,0 +1,310 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <assert.h> +#include <baseboard/variants.h> +#include <cbfs.h> +#include <chip.h> +#include <commonlib/cbfs_serialized.h> +#include <compiler.h> +#include <device/device.h> +#include <drivers/intel/gma/opregion.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/mp_init.h> +#include <smbios.h> +#include <soc/ramstage.h> +#include <string.h> +#include <variant/sku.h> + +#define PL2_I7_SKU 44 +#define PL2_DEFAULT 29 +#define PL2_KBL_U 25 + +/* PL2 ID define*/ +#define PL2_ID_DEFAULT 0 +#define PL2_ID_SONA_SYNDRA 1 +#define PL2_ID_BARD_EKKO 2 + +static const struct pl2_config { + uint32_t cpuid_y0_pl2; + uint32_t cpuid_non_y0_pl2; +} pl2_config_table[] = { + [PL2_ID_DEFAULT] = { PL2_I7_SKU, PL2_DEFAULT }, + [PL2_ID_SONA_SYNDRA] = { PL2_DEFAULT, PL2_KBL_U }, + [PL2_ID_BARD_EKKO] = { PL2_DEFAULT, PL2_KBL_U }, +}; + +/* Variant for AKALI */ +#define AKALI_SA_AC_LOADLINE 1100 +#define AKALI_SA_DC_LOADLINE 1028 +#define AKALI_IA_AC_LOADLINE 272 +#define AKALI_IA_DC_LOADLINE 247 +#define AKALI_GT_AC_LOADLINE 314 +#define AKALI_GT_DC_LOADLINE 321 + +/* We only have Akali and Nami default settings so far */ +enum project_sku { + PRJ_AKALI = 1, +}; + +static const struct { + enum project_sku sku; + int ac_loadline[NUM_VR_DOMAINS]; + int dc_loadline[NUM_VR_DOMAINS]; +} sku_overwrite_mapping[] = { + { + .sku = PRJ_AKALI, + .ac_loadline = { + AKALI_SA_AC_LOADLINE, + AKALI_IA_AC_LOADLINE, + AKALI_GT_AC_LOADLINE, + AKALI_GT_AC_LOADLINE + }, + .dc_loadline = { + AKALI_SA_DC_LOADLINE, + AKALI_IA_DC_LOADLINE, + AKALI_GT_DC_LOADLINE, + AKALI_GT_DC_LOADLINE + } + }, +}; + +static uint32_t get_pl2(int pl2_id) +{ + assert(pl2_id < ARRAY_SIZE(pl2_config_table)); + if (cpuid_eax(1) == CPUID_KABYLAKE_Y0) + return pl2_config_table[pl2_id].cpuid_y0_pl2; + + return pl2_config_table[pl2_id].cpuid_non_y0_pl2; +} + +uint32_t variant_board_sku(void) +{ + static uint32_t sku_id = SKU_UNKNOWN; + uint32_t id; + + if (sku_id != SKU_UNKNOWN) + return sku_id; + if (google_chromeec_cbi_get_sku_id(&id)) + return SKU_UNKNOWN; + sku_id = id; + + return sku_id; +} + +const char *smbios_mainboard_sku(void) +{ + static char sku_str[14]; /* sku{0..4294967295} */ + + snprintf(sku_str, sizeof(sku_str), "sku%u", variant_board_sku()); + + return sku_str; +} + +#define OEM_UNKNOWN 0xff + +/* + * Read OEM ID from EC using cbi commands. + * Return value: + * Success = OEM ID read from EC + * Failure = OEM_UNKNOWN (0xff) + */ +static uint8_t read_oem_id(void) +{ + static uint8_t oem_id = OEM_UNKNOWN; + uint32_t id; + + if (oem_id != OEM_UNKNOWN) + return oem_id; + + if (google_chromeec_cbi_get_oem_id(&id)) + return OEM_UNKNOWN; + + if (id > OEM_UNKNOWN) { + printk(BIOS_ERR, "%s: OEM ID too big %u!\n", __func__, id); + return OEM_UNKNOWN; + } + + oem_id = id; + printk(BIOS_DEBUG, "%s: OEM ID=%d\n", __func__, oem_id); + + return oem_id; +} + +/* "oem.bin" in cbfs contains array of records using the following structure. */ +struct oem_mapping { + uint8_t oem_id; + char oem_name[10]; +} __packed; + +/* Local buffer to read "oem.bin" */ +static char oem_bin_data[200]; + +const char *smbios_mainboard_manufacturer(void) +{ + uint8_t oem_id = read_oem_id(); + const struct oem_mapping *oem_entry = (void *)&oem_bin_data; + size_t oem_data_size; + size_t curr = 0; + static const char *manuf; + + if (manuf) + return manuf; + + /* If OEM ID cannot be determined, return default manuf string. */ + if (oem_id == OEM_UNKNOWN) + return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; + + oem_data_size = cbfs_boot_load_file("oem.bin", oem_bin_data, + sizeof(oem_bin_data), + CBFS_TYPE_RAW); + + while ((curr < oem_data_size) && + ((oem_data_size - curr) >= sizeof(*oem_entry))) { + if (oem_id == oem_entry->oem_id) { + manuf = oem_entry->oem_name; + break; + } + curr += sizeof(*oem_entry); + oem_entry++; + } + + if (manuf == NULL) + manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; + + return manuf; +} + +const char *mainboard_vbt_filename(void) +{ + uint32_t sku_id = variant_board_sku(); + + switch (sku_id) { + case SKU_0_PANTHEON: + case SKU_1_PANTHEON: + case SKU_2_PANTHEON: + return "vbt-pantheon.bin"; + case SKU_0_VAYNE: + case SKU_1_VAYNE: + case SKU_2_VAYNE: + return "vbt-vayne.bin"; + case SKU_0_AKALI: + case SKU_1_AKALI: + case SKU_0_AKALI360: + case SKU_1_AKALI360: + return "vbt-akali.bin"; + case SKU_0_BARD: + case SKU_1_BARD: + case SKU_2_BARD: + case SKU_3_BARD: + case SKU_4_BARD: + case SKU_5_BARD: + case SKU_6_BARD: + case SKU_7_BARD: + return "vbt-bard.bin"; + default: + return "vbt.bin"; + break; + } +} + +static int find_sku_mapping(const uint8_t oem_id) +{ + /* Check if this OEM ID has a mapping table entry. */ + for (int i = 0; i < ARRAY_SIZE(sku_overwrite_mapping); i++) + if (oem_id == sku_overwrite_mapping[i].sku) + return i; + + return -1; +} + +/* Override dev tree settings per board */ +void variant_devtree_update(void) +{ + uint32_t sku_id = variant_board_sku(); + uint32_t i; + int oem_index; + struct device *root = SA_DEV_ROOT; + config_t *cfg = root->chip_info; + uint8_t pl2_id = PL2_ID_DEFAULT; + struct device *spi_fpmcu = PCH_DEV_GSPI1; + + switch (sku_id) { + case SKU_0_SONA: + case SKU_1_SONA: + case SKU_0_SYNDRA: + case SKU_1_SYNDRA: + case SKU_2_SYNDRA: + case SKU_3_SYNDRA: + case SKU_4_SYNDRA: + case SKU_5_SYNDRA: + case SKU_6_SYNDRA: + case SKU_7_SYNDRA: + pl2_id = PL2_ID_SONA_SYNDRA; + case SKU_0_VAYNE: + case SKU_1_VAYNE: + case SKU_2_VAYNE: + case SKU_0_PANTHEON: + case SKU_1_PANTHEON: + case SKU_2_PANTHEON: + case SKU_3_PANTHEON: + case SKU_4_PANTHEON: + cfg->usb2_ports[5].enable = 0; + spi_fpmcu->enabled = 0; + break; + case SKU_0_BARD: + case SKU_1_BARD: + case SKU_2_BARD: + case SKU_3_BARD: + case SKU_4_BARD: + case SKU_5_BARD: + case SKU_6_BARD: + case SKU_7_BARD: + case SKU_0_EKKO: + case SKU_1_EKKO: + case SKU_2_EKKO: + case SKU_3_EKKO: + case SKU_4_EKKO: + case SKU_5_EKKO: + case SKU_6_EKKO: + case SKU_7_EKKO: + pl2_id = PL2_ID_BARD_EKKO; + cfg->usb2_ports[5].enable = 0; + cfg->usb2_ports[7].enable = 0; + cfg->usb2_ports[8].enable = 0; + cfg->usb2_ports[9].enable = 0; + break; + default: + break; + } + + /* Update PL2 based on SKU. */ + cfg->tdp_pl2_override = get_pl2(pl2_id); + + /* Overwrite settings for different projects based on OEM ID*/ + oem_index = find_sku_mapping(read_oem_id()); + + /* Return if the OEM ID is not supported or no changes are required */ + if (oem_index < 0) + return; + + for (i = 0; i < ARRAY_SIZE(cfg->domain_vr_config); i++) { + cfg->domain_vr_config[i].ac_loadline = + sku_overwrite_mapping[oem_index].ac_loadline[i]; + cfg->domain_vr_config[i].dc_loadline = + sku_overwrite_mapping[oem_index].dc_loadline[i]; + } +} diff --git a/src/mainboard/google/poppy/variants/sylas/memory.c b/src/mainboard/google/poppy/variants/sylas/memory.c new file mode 100644 index 0000000..b7f5185 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/memory.c @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <variant/gpio.h> +#include <string.h> + +/* Rcomp resistor */ +static const u16 rcomp_resistor_ddp[] = { 121, 81, 100 }; +static const u16 rcomp_resistor_sdp[] = { 200, 81, 100 }; +static const u16 rcomp_resistor_lpddr3[] = { 200, 81, 162 }; + +/* Rcomp target */ +static const u16 rcomp_target[] = { 100, 40, 20, 20, 26 }; +static const u16 rcomp_target_lpddr3[] = { 100, 40, 40, 23, 40 }; + +/* DQ byte map */ +static const u8 dq_map_lpddr3[][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } +}; + +/* DQS CPU<>DRAM map */ +static const u8 dqs_map_lpddr3[][8] = { + { 1, 0, 3, 2, 6, 5, 4, 7 }, + { 0, 3, 2, 1, 6, 4, 7, 5 }, +}; + +/* Memory ids are 1-indexed, so subtract 1 to use 0-indexed values in bitmap. */ +#define MEM_ID(x) (1 << ((x) - 1)) + +/* Bitmap to indicate which memory ids are using DDP. */ +static const uint16_t ddp_bitmap = MEM_ID(4); + +static void fill_lpddr3_memory_params(struct memory_params *p) +{ + p->type = MEMORY_LPDDR3; + p->use_sec_spd = 1; + p->dq_map = dq_map_lpddr3; + p->dq_map_size = sizeof(dq_map_lpddr3); + p->dqs_map = dqs_map_lpddr3; + p->dqs_map_size = sizeof(dqs_map_lpddr3); + p->rcomp_resistor = rcomp_resistor_lpddr3; + p->rcomp_resistor_size = sizeof(rcomp_resistor_lpddr3); + p->rcomp_target = rcomp_target_lpddr3; + p->rcomp_target_size = sizeof(rcomp_target_lpddr3); +} + +static void fill_ddr4_memory_params(struct memory_params *p) +{ + p->type = MEMORY_DDR4; + p->use_sec_spd = 0; + + /* Rcomp resistor values are different for SDP and DDP. */ + if (ddp_bitmap & MEM_ID(variant_memory_sku())) { + p->rcomp_resistor = rcomp_resistor_ddp; + p->rcomp_resistor_size = sizeof(rcomp_resistor_ddp); + } else { + p->rcomp_resistor = rcomp_resistor_sdp; + p->rcomp_resistor_size = sizeof(rcomp_resistor_sdp); + } + + p->rcomp_target = rcomp_target; + p->rcomp_target_size = sizeof(rcomp_target); +} + +void variant_memory_params(struct memory_params *p) +{ + memset(p, 0, sizeof(*p)); + gpio_input_pulldown(GPIO_MEM_CONFIG_4); + if (gpio_get(GPIO_MEM_CONFIG_4)) + /* set to LPDDR3 */ + fill_lpddr3_memory_params(p); + else + /* default to DDR4 */ + fill_ddr4_memory_params(p); + + /* GPP_D10 set to 0 for dual channel and 1 for single channel */ + if (gpio_get(GPP_D10)) + p->single_channel = 1; +} diff --git a/src/mainboard/google/poppy/variants/sylas/nhlt.c b/src/mainboard/google/poppy/variants/sylas/nhlt.c new file mode 100644 index 0000000..c3096d4 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/nhlt.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +void variant_nhlt_init(struct nhlt *nhlt) +{ + /* 4 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 4)) + printk(BIOS_ERR, "Couldn't add 4CH DMIC array.\n"); + + /* Dialog DA7219 Headset codec. */ + if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add Dialog DA7219.\n"); + + /* MAXIM Smart Amps for left and right speakers. */ + if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0)) + printk(BIOS_ERR, "Couldn't add Maxim_98357 codec.\n"); + +} + +void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id, + uint32_t *oem_revision) +{ + *oem_id = "GOOGLE"; + *oem_table_id = "NAMIMAX"; + *oem_revision = 0; +} diff --git a/src/mainboard/google/poppy/variants/sylas/smihandler.c b/src/mainboard/google/poppy/variants/sylas/smihandler.c new file mode 100644 index 0000000..6816508 --- /dev/null +++ b/src/mainboard/google/poppy/variants/sylas/smihandler.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <delay.h> +#include "gpio.h" + +#define TOUCH_DISABLE GPP_C3 +#define TOUCH_RESET GPP_B3 +#define TOUCH_ENABLE GPP_B4 +#define FP_PWR_ENABLE GPP_B11 + +/* + * Elan touchscreen has higher delay requirements than the other + * devices, so using that. + */ +#define ELAN_STOP_OFF_DELAY 2 +#define ELAN_RESET_OFF_DELAY 2 +#define ELAN_ENABLE_OFF_DELAY 100 + +void variant_smi_sleep(u8 slp_typ) +{ + if (slp_typ == ACPI_S5) { + /* TOUCHSCREEN_DIS# */ + gpio_set(TOUCH_DISABLE, 0); + mdelay(ELAN_STOP_OFF_DELAY); + /* TOUCHSCREEN_RST# */ + gpio_set(TOUCH_RESET, 0); + mdelay(ELAN_RESET_OFF_DELAY); + /* EN_PP3300_DX_TOUCHSCREEN */ + gpio_set(TOUCH_ENABLE, 0); + mdelay(ELAN_ENABLE_OFF_DELAY); + /* PCH_FP_PWR_EN */ + gpio_set(FP_PWR_ENABLE, 0); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa43b72d4e1f61a50ab624ad8bd2938c3a1ef809 Gerrit-Change-Number: 41648 Gerrit-PatchSet: 1 Gerrit-Owner: Danomi Lin <lin.danomi@inventec.corp-partner.google.com> Gerrit-MessageType: newchange