Change in coreboot[master]: soc/intel/braswell: Increase dcache size
Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45827 ) Change subject: soc/intel/braswell: Increase dcache size ...................................................................... soc/intel/braswell: Increase dcache size Need to increase the DRAM cache size for braswell as the was getting the compilation error "Cache as RAM area is too full" when moving the mrc_cache writeback to romstage. We need to increase this first before landing the CL moving mrc_cache writeback to romstage. BUG=b:150502246 BRANCH=None TEST=Able to successfully compile braswell boards Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Signed-off-by: Shelley Chen <shchen@google.com> --- M src/soc/intel/braswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/45827/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5c9988c..077b5a1 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -96,7 +96,7 @@ config DCACHE_RAM_SIZE hex - default 0x4000 + default 0x5000 help The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE -- To view, visit https://review.coreboot.org/c/coreboot/+/45827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Gerrit-Change-Number: 45827 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen@google.com> Gerrit-MessageType: newchange
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45827 ) Change subject: soc/intel/braswell: Increase dcache size ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG@9 PS1, Line 9: the it? https://review.coreboot.org/c/coreboot/+/45827/1/src/soc/intel/braswell/Kcon... File src/soc/intel/braswell/Kconfig: https://review.coreboot.org/c/coreboot/+/45827/1/src/soc/intel/braswell/Kcon... PS1, Line 103: must add up to a power of 2 Given this comment, I believe you will have to bump it up to 0x8000. -- To view, visit https://review.coreboot.org/c/coreboot/+/45827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Gerrit-Change-Number: 45827 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen@google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Wed, 30 Sep 2020 06:39:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45827 ) Change subject: soc/intel/braswell: Increase dcache size ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG@9 PS1, Line 9: Need to increase the DRAM cache size for braswell as the was getting : the compilation error "Cache as RAM area is too full" when moving the : mrc_cache writeback to romstage.
Increase the DRAM cache size for Braswell to address the compilation error
Cache as RAM area too full
when moving the mrc_cache writeback to romstage.
-- To view, visit https://review.coreboot.org/c/coreboot/+/45827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Gerrit-Change-Number: 45827 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen@google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Wed, 30 Sep 2020 16:34:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment
Hello build bot (Jenkins), Furquan Shaikh, Duncan Laurie, Julius Werner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45827 to look at the new patch set (#2). Change subject: soc/intel/braswell: Increase dcache size ...................................................................... soc/intel/braswell: Increase dcache size Increase the DRAM cache size for Braswell to address the compilation error Cache as RAM area too full when moving the mrc_cache writeback to romstage. We need to increase this first before landing the CL moving mrc_cache writeback to romstage. BUG=b:150502246 BRANCH=None TEST=Able to successfully compile braswell boards Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Signed-off-by: Shelley Chen <shchen@google.com> --- M src/soc/intel/braswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/45827/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Gerrit-Change-Number: 45827 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen@google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-MessageType: newpatchset
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45827 ) Change subject: soc/intel/braswell: Increase dcache size ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/45827/1/src/soc/intel/braswell/Kcon... File src/soc/intel/braswell/Kconfig: https://review.coreboot.org/c/coreboot/+/45827/1/src/soc/intel/braswell/Kcon... PS1, Line 103: must add up to a power of 2
Given this comment, I believe you will have to bump it up to 0x8000. Done
-- To view, visit https://review.coreboot.org/c/coreboot/+/45827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Gerrit-Change-Number: 45827 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen@google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Thu, 01 Oct 2020 20:40:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan@google.com> Gerrit-MessageType: comment
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45827 ) Change subject: soc/intel/braswell: Increase dcache size ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Gerrit-Change-Number: 45827 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen@google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Thu, 01 Oct 2020 21:07:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45827 ) Change subject: soc/intel/braswell: Increase dcache size ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG@9 PS1, Line 9: the
it? Done
https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG@9 PS1, Line 9: Need to increase the DRAM cache size for braswell as the was getting : the compilation error "Cache as RAM area is too full" when moving the : mrc_cache writeback to romstage.
Increase the DRAM cache size for Braswell to address the […] Done
-- To view, visit https://review.coreboot.org/c/coreboot/+/45827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Gerrit-Change-Number: 45827 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen@google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Fri, 02 Oct 2020 18:16:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan@google.com> Comment-In-Reply-To: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-MessageType: comment
Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45827 ) Change subject: soc/intel/braswell: Increase dcache size ...................................................................... soc/intel/braswell: Increase dcache size Increase the DRAM cache size for Braswell to address the compilation error Cache as RAM area too full when moving the mrc_cache writeback to romstage. We need to increase this first before landing the CL moving mrc_cache writeback to romstage. BUG=b:150502246 BRANCH=None TEST=Able to successfully compile braswell boards Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45827 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> --- M src/soc/intel/braswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ae4fc21..4eb810e 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -93,7 +93,7 @@ config DCACHE_RAM_SIZE hex - default 0x4000 + default 0x8000 help The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE -- To view, visit https://review.coreboot.org/c/coreboot/+/45827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Gerrit-Change-Number: 45827 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen@google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen@google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-MessageType: merged
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45827 ) Change subject: soc/intel/braswell: Increase dcache size ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 5/1/6 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/21963 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/21962 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : FAIL : https://lava.9esec.io/r/21961 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/21960 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/21958 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/21957 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/45827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Gerrit-Change-Number: 45827 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen@google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen@google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Sat, 03 Oct 2020 01:04:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45827?usp=email ) Change subject: soc/intel/braswell: Increase dcache size ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: For the record, this seems to have caused a regression: CB:82256 -- To view, visit https://review.coreboot.org/c/coreboot/+/45827?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Gerrit-Change-Number: 45827 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen@google.com> Gerrit-Reviewer: Duncan L Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh@gmail.com> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05@gmail.com> Gerrit-Reviewer: Shelley Chen <shchen@google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot@gmail.com> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@mailbox.org> Gerrit-Comment-Date: Wed, 08 May 2024 15:17:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment
participants (5)
-
9elements QA (Code Review) -
Angel Pons (Code Review)
-
Furquan Shaikh (Code Review)
-
Paul Menzel (Code Review)
-
Shelley Chen (Code Review)