Jianeng Ceng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87899?usp=email ) Change subject: mb/google/nissa/var/pujjoniru: Config AUX gpio to correct TCSS port ...................................................................... mb/google/nissa/var/pujjoniru: Config AUX gpio to correct TCSS port In TWL, Type-C0 corresponds to TCSS port1, and Type-C1 corresponds to TCSS port0. In order for the DP functions of the two Type-C ports to operate normally, the corresponding relationship needs to be configured correctly. BUG=b:418106736 TEST=DP function of Type-C0/C1 workable Change-Id: I4aa406e72d1e5f0434866b105f20df6362f3d304 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/pujjoniru/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/87899/1 diff --git a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb index 60d3117..cc3d1dc 100644 --- a/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjoniru/overridetree.cb @@ -27,12 +27,12 @@ # motherboard to USBC connector register "tcss_aux_ori" = "5" - register "typec_aux_bias_pads[0]" = "{ + register "typec_aux_bias_pads[1]" = "{ .pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23 }" - register "typec_aux_bias_pads[1]" = "{ + register "typec_aux_bias_pads[0]" = "{ .pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22 }" -- To view, visit https://review.coreboot.org/c/coreboot/+/87899?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4aa406e72d1e5f0434866b105f20df6362f3d304 Gerrit-Change-Number: 87899 Gerrit-PatchSet: 1 Gerrit-Owner: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>