Change in coreboot[master]: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming
Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44060 ) Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming SA SMRAMC register PCI offset 0x88 is depcrecated ICL. JSL and TGL. Removing the resgiter programming for these platforms. The write to this register does not take effect and remains configured to 0, even when programmed. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 --- M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/include/soc/systemagent.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/include/soc/systemagent.h M src/soc/intel/jasperlake/smmrelocate.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/smmrelocate.c 9 files changed, 0 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/44060/1 diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 45c81ca..2823fd7 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -221,9 +221,6 @@ * start flowing. */ global_smi_enable(); - - /* Lock down the SMRAM space. */ - smm_lock(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/icelake/include/soc/systemagent.h b/src/soc/intel/icelake/include/soc/systemagent.h index 90465a24..ef648a6 100644 --- a/src/soc/intel/icelake/include/soc/systemagent.h +++ b/src/soc/intel/icelake/include/soc/systemagent.h @@ -9,12 +9,6 @@ #define EPBAR 0x40 #define DMIBAR 0x68 -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #define CAPID0_A 0xe4 #define BIOS_RESET_CPL 0x5da8 diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index f1a7033..a847db9 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -17,7 +17,6 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> -#include <soc/systemagent.h> static void update_save_state(int cpu, uintptr_t curr_smbase, @@ -234,15 +233,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 99cbef2..3a50929 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -185,9 +185,6 @@ * start flowing. */ global_smi_enable(); - - /* Lock down the SMRAM space. */ - smm_lock(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/jasperlake/include/soc/systemagent.h b/src/soc/intel/jasperlake/include/soc/systemagent.h index 2ad98f7..e21c9af 100644 --- a/src/soc/intel/jasperlake/include/soc/systemagent.h +++ b/src/soc/intel/jasperlake/include/soc/systemagent.h @@ -9,12 +9,6 @@ #define EPBAR 0x40 #define DMIBAR 0x68 -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #define CAPID0_A 0xe4 #define VTD_DISABLE (1 << 23) diff --git a/src/soc/intel/jasperlake/smmrelocate.c b/src/soc/intel/jasperlake/smmrelocate.c index 664ea6c..bbdcb68 100644 --- a/src/soc/intel/jasperlake/smmrelocate.c +++ b/src/soc/intel/jasperlake/smmrelocate.c @@ -17,7 +17,6 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> -#include <soc/systemagent.h> static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, @@ -233,15 +232,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 9a96f8f..be056fb 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -191,9 +191,6 @@ * start flowing. */ global_smi_enable(); - - /* Lock down the SMRAM space. */ - smm_lock(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h index 3e43843..fca9b2b 100644 --- a/src/soc/intel/tigerlake/include/soc/systemagent.h +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -15,12 +15,6 @@ #define EPBAR 0x40 #define DMIBAR 0x68 -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #define CAPID0_A 0xe4 #define VTD_DISABLE (1 << 23) diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index 664ea6c..bbdcb68 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -17,7 +17,6 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> -#include <soc/systemagent.h> static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, @@ -233,15 +232,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-MessageType: newchange
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44060 ) Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... Patch Set 1: So if I understand correctly, right now SMRAM on these platforms remains unlocked after coreboot loads the payload? -- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak@chromium.org> Gerrit-Comment-Date: Thu, 30 Jul 2020 16:37:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44060 ) Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/c/coreboot/+/44060/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44060/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming So, if this register is deprecated, how is SMRAM locked? Via IMRs? https://review.coreboot.org/c/coreboot/+/44060/1//COMMIT_MSG@9 PS1, Line 9: depcrecated deprecated https://review.coreboot.org/c/coreboot/+/44060/1//COMMIT_MSG@10 PS1, Line 10: resgiter register -- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak@chromium.org> Gerrit-Comment-Date: Thu, 30 Jul 2020 16:54:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44060 ) Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... Patch Set 1:
Patch Set 1:
So if I understand correctly, right now SMRAM on these platforms remains unlocked after coreboot loads the payload?
This are compatible SMRAM region locking not the actual DRAM based SMRAM locking stuff. This register controls below 1 MB VGA region (0xA_0000 till 0xB_FFFF) Here is the register range that this register protects: C_BASE_SEG: This field indicates the location of SMM space. Only SMM space between A_0000h and B_FFFFh is supported, so this field is hardwired to 010b -- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak@chromium.org> Gerrit-Comment-Date: Fri, 31 Jul 2020 03:26:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44060 ) Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... Patch Set 1:
Patch Set 1:
Patch Set 1:
So if I understand correctly, right now SMRAM on these platforms remains unlocked after coreboot loads the payload?
This are compatible SMRAM region locking not the actual DRAM based SMRAM locking stuff. This register controls below 1 MB VGA region (0xA_0000 till 0xB_FFFF)
Here is the register range that this register protects:
C_BASE_SEG: This field indicates the location of SMM space. Only SMM space between A_0000h and B_FFFFh is supported, so this field is hardwired to 010b
Ah right, this only locks the CSEG, which we don't typically use here in coreboot, preferring TSEG instead. To "lock" access to TSEG, we program the SMRR registers to prevent access to SMRAM (TSEG region) from any other SAI than SMM_SAI. Is my understanding correct? -- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak@chromium.org> Gerrit-Comment-Date: Fri, 31 Jul 2020 21:06:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44060 ) Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1:
So if I understand correctly, right now SMRAM on these platforms remains unlocked after coreboot loads the payload?
This are compatible SMRAM region locking not the actual DRAM based SMRAM locking stuff. This register controls below 1 MB VGA region (0xA_0000 till 0xB_FFFF)
Here is the register range that this register protects:
C_BASE_SEG: This field indicates the location of SMM space. Only SMM space between A_0000h and B_FFFFh is supported, so this field is hardwired to 010b
Ah right, this only locks the CSEG, which we don't typically use here in coreboot, preferring TSEG instead. To "lock" access to TSEG, we program the SMRR registers to prevent access to SMRAM (TSEG region) from any other SAI than SMM_SAI. Is my understanding correct?
Yes Tim -- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak@chromium.org> Gerrit-Comment-Date: Sat, 01 Aug 2020 03:22:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44060 ) Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak@chromium.org> Gerrit-Comment-Date: Sat, 01 Aug 2020 03:22:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44060 ) Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1:
So if I understand correctly, right now SMRAM on these platforms remains unlocked after coreboot loads the payload?
This are compatible SMRAM region locking not the actual DRAM based SMRAM locking stuff. This register controls below 1 MB VGA region (0xA_0000 till 0xB_FFFF)
Here is the register range that this register protects:
C_BASE_SEG: This field indicates the location of SMM space. Only SMM space between A_0000h and B_FFFFh is supported, so this field is hardwired to 010b
Ah right, this only locks the CSEG, which we don't typically use here in coreboot, preferring TSEG instead. To "lock" access to TSEG, we program the SMRR registers to prevent access to SMRAM (TSEG region) from any other SAI than SMM_SAI. Is my understanding correct?
Yes Tim
Thanks Subrata! -- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak@chromium.org> Gerrit-Comment-Date: Tue, 04 Aug 2020 00:12:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44060 ) Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Aug 2020 17:15:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44060 ) Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/44060/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44060/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming
So, if this register is deprecated, how is SMRAM locked? Via IMRs? This register was not used to lock the SMRAM RAM rather only controlled the access to range specified in C_BASE_SEG.
-- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Aug 2020 17:23:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus@gmail.com> Gerrit-MessageType: comment
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44060 to look at the new patch set (#2). Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming SA SMRAMC register PCI offset 0x88 is deprecated ICL. JSL and TGL. Removing the register programming for these platforms. The write to this register does not take effect and remains configured to 0, even when programmed. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 --- M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/include/soc/systemagent.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/include/soc/systemagent.h M src/soc/intel/jasperlake/smmrelocate.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/smmrelocate.c 9 files changed, 0 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/44060/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-MessageType: newpatchset
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44060 ) Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/44060/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44060/1//COMMIT_MSG@9 PS1, Line 9: depcrecated
deprecated Done
https://review.coreboot.org/c/coreboot/+/44060/1//COMMIT_MSG@10 PS1, Line 10: resgiter
register Done
-- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Aug 2020 17:25:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus@gmail.com> Gerrit-MessageType: comment
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44060 to look at the new patch set (#3). Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming SA SMRAMC register PCI offset 0x88 is deprecated for ICL, JSL and TGL. Removing the register programming for these platforms. The write to this register does not take effect and remains configured to 0, even when programmed. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 --- M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/include/soc/systemagent.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/include/soc/systemagent.h M src/soc/intel/jasperlake/smmrelocate.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/smmrelocate.c 9 files changed, 0 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/44060/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-MessageType: newpatchset
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44060 ) Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/44060/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44060/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming
This register was not used to lock the SMRAM RAM rather only controlled the access to range specifie […] Angel, can this be marked resolved? any opens?
-- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Angel Pons <th3fanbus@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Wed, 05 Aug 2020 06:56:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus@gmail.com> Comment-In-Reply-To: Aamir Bohra <aamir.bohra@intel.com> Gerrit-MessageType: comment
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44060 ) Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... Patch Set 3: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/44060/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44060/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming
Angel, can this be marked resolved? any opens? Yes, sorry for the late reply.
-- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Wed, 05 Aug 2020 07:44:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus@gmail.com> Comment-In-Reply-To: Aamir Bohra <aamir.bohra@intel.com> Gerrit-MessageType: comment
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44060 ) Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Thu, 06 Aug 2020 02:34:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44060 ) Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming SA SMRAMC register PCI offset 0x88 is deprecated for ICL, JSL and TGL. Removing the register programming for these platforms. The write to this register does not take effect and remains configured to 0, even when programmed. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> --- M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/include/soc/systemagent.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/include/soc/systemagent.h M src/soc/intel/jasperlake/smmrelocate.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/smmrelocate.c 9 files changed, 0 insertions(+), 66 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Subrata Banik: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 45c81ca..2823fd7 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -221,9 +221,6 @@ * start flowing. */ global_smi_enable(); - - /* Lock down the SMRAM space. */ - smm_lock(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/icelake/include/soc/systemagent.h b/src/soc/intel/icelake/include/soc/systemagent.h index 90465a24..ef648a6 100644 --- a/src/soc/intel/icelake/include/soc/systemagent.h +++ b/src/soc/intel/icelake/include/soc/systemagent.h @@ -9,12 +9,6 @@ #define EPBAR 0x40 #define DMIBAR 0x68 -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #define CAPID0_A 0xe4 #define BIOS_RESET_CPL 0x5da8 diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index f1a7033..a847db9 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -17,7 +17,6 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> -#include <soc/systemagent.h> static void update_save_state(int cpu, uintptr_t curr_smbase, @@ -234,15 +233,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 99cbef2..3a50929 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -185,9 +185,6 @@ * start flowing. */ global_smi_enable(); - - /* Lock down the SMRAM space. */ - smm_lock(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/jasperlake/include/soc/systemagent.h b/src/soc/intel/jasperlake/include/soc/systemagent.h index 2ad98f7..e21c9af 100644 --- a/src/soc/intel/jasperlake/include/soc/systemagent.h +++ b/src/soc/intel/jasperlake/include/soc/systemagent.h @@ -9,12 +9,6 @@ #define EPBAR 0x40 #define DMIBAR 0x68 -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #define CAPID0_A 0xe4 #define VTD_DISABLE (1 << 23) diff --git a/src/soc/intel/jasperlake/smmrelocate.c b/src/soc/intel/jasperlake/smmrelocate.c index 664ea6c..bbdcb68 100644 --- a/src/soc/intel/jasperlake/smmrelocate.c +++ b/src/soc/intel/jasperlake/smmrelocate.c @@ -17,7 +17,6 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> -#include <soc/systemagent.h> static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, @@ -233,15 +232,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 9a96f8f..be056fb 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -191,9 +191,6 @@ * start flowing. */ global_smi_enable(); - - /* Lock down the SMRAM space. */ - smm_lock(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h index 3e43843..fca9b2b 100644 --- a/src/soc/intel/tigerlake/include/soc/systemagent.h +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -15,12 +15,6 @@ #define EPBAR 0x40 #define DMIBAR 0x68 -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #define CAPID0_A 0xe4 #define VTD_DISABLE (1 << 23) diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index 664ea6c..bbdcb68 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -17,7 +17,6 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> -#include <soc/systemagent.h> static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, @@ -233,15 +232,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-MessageType: merged
participants (5)
-
Aamir Bohra (Code Review) -
Angel Pons (Code Review)
-
Furquan Shaikh (Code Review)
-
Subrata Banik (Code Review)
-
Tim Wawrzynczak (Code Review)