Patch merged into coreboot/master: soc/intel/skylake: Remove pad configuration size hardcoding
Nov. 30, 2016
7:54 a.m.
the following patch was just integrated into master: commit 0068dfdcc8c2a80508cdd44909d9a2561a30a0e5 Author: Subrata Banik <subrata.banik@intel.com> Date: Wed Nov 23 00:54:47 2016 +0530 soc/intel/skylake: Remove pad configuration size hardcoding Existing GPIO driver inside coreboot use some hardcoded magic number to calculate gpio pad offset. Avoid this kind of hardcoding. Change-Id: I6110435574b141c57f366ccb1fbe9bf49d4dd70a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17571 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> See https://review.coreboot.org/17571 for details. -gerrit
3338
Age (days ago)
3338
Last active (days ago)
0 comments
1 participants
participants (1)
-
gerrit@coreboot.org