Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support
Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44578 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support ...................................................................... mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support Add initial support for another CFL variant. Quite hacky right now - but seems to boot Linux with Tianocore. Right now I need to enable, but hidden, the two additional NICs. Not sure where this comes from - maybe GPIOs. Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Signed-off-by: Christian Walter <christian.walter@9elements.com> --- M src/mainboard/supermicro/x11-lga1151v2-series/Kconfig M src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/Makefile.inc A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/variants.h A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb 8 files changed, 460 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/44578/1 diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig index ed29b16..4029fce 100644 --- a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig @@ -25,6 +25,7 @@ config MAINBOARD_PART_NUMBER string default "X11SCH-F" if BOARD_SUPERMICRO_X11SCH_F + default "X11SCH-L4NF" if BOARD_SUPERMICRO_X11SCH_L4NF config MAINBOARD_DIR string @@ -33,10 +34,12 @@ config VARIANT_DIR string default "x11sch-f" if BOARD_SUPERMICRO_X11SCH_F + default "x11sch-l4nf" if BOARD_SUPERMICRO_X11SCH_L4NF config MAINBOARD_PART_NUMBER string default "X11SCH-F" if BOARD_SUPERMICRO_X11SCH_F + default "X11SCH-L4NF" if BOARD_SUPERMICRO_X11SCH_L4NF config MAX_CPUS int diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name index 8ab4f1e..d25b19f 100644 --- a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name +++ b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name @@ -1,3 +1,8 @@ config BOARD_SUPERMICRO_X11SCH_F bool "X11SCH-F" select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151V2_SERIES + +config BOARD_SUPERMICRO_X11SCH_L4NF + bool "X11SCH-L4NF" + select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151V2_SERIES + diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/Makefile.inc b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/Makefile.inc new file mode 100644 index 0000000..8914639 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt new file mode 100644 index 0000000..a66959a --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Vendor name: Supermicro +Board name: X11SCH-L4NF +Board URL: https://www.supermicro.com/en/products/motherboard/X11SCH-F +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c new file mode 100644 index 0000000..b2a72f5 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c @@ -0,0 +1,296 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "include/variant/gpio.h" +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_ALERT1# */ + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO0 */ + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_IO1 */ + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO2 */ + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO3 */ + _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_CS0# */ + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_ALERT0# */ + _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_CLK */ + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* CLKOUT_LPC1 */ + _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SUSWARN#/SUSPWRDNACK */ + _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_RESET# */ + _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSACK# */ + PAD_CFG_GPO(GPP_A16, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_A17, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, DEEP, OFF, ACPI), /* GPIO */ + /* GPP_A19 - RESERVED */ + _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A21, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, DEEP, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPO(GPP_B0, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_B3, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B5, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_B7, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B8, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B9, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B10, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B11, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S0# */ + _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* PLTRST# */ + _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SPKR */ + PAD_CFG_GPO(GPP_B15, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B16, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B17, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_B20, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B21, 1, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, DEEP, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* PCHHOT# */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ + _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPIO */ + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C12, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C13, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_C15, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C0_SDA */ + _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C0_SCL */ + _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C1_SDA */ + _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C1_SCL */ + /* GPP_C20 - RESERVED */ + PAD_CFG_GPO(GPP_C21, 1, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + + /* ------- GPIO Group GPP_D ------- */ + _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_D1, 1, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, DEEP, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_D5, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D6, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D7, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D8, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D9, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D10, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D11, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D12, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D13, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D14, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D16, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D17, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D18, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D19, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D21, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D22, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D23, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPO(GPP_G0, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G1, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G2, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G3, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G4, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G5, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G6, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G7, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group AZA ------- */ + + /* ------- GPIO Group VGPIO_0 ------- */ + + /* ------- GPIO Group VGPIO_1 ------- */ + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + PAD_CFG_GPO(GPD0, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ACPRESENT */ + _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* LAN_WAKE# */ + _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PRWBTN# */ + _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S3# */ + _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S4# */ + _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_A# */ + _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSCLK */ + PAD_CFG_GPO(GPD9, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S5# */ + PAD_CFG_GPO(GPD11, 0, DEEP), /* GPIO */ + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_K ------- */ + _PAD_CFG_STRUCT(GPP_K0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_K4, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K5, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K6, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K7, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K8, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_K9, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K10, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K11, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K13, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K14, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_K15, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K16, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_K18, 1, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SMI# */ + PAD_CFG_GPO(GPP_K20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K21, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H1, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H4, 0, DEEP), /* GPIO */ + /* GPP_H5 - RESERVED */ + PAD_CFG_GPO(GPP_H6, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H7, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H8, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H9, 0, DEEP), /* GPIO */ + /* GPP_H10 - RESERVED */ + /* GPP_H11 - RESERVED */ + PAD_CFG_GPO(GPP_H12, 1, PLTRST), /* GPIO */ + /* GPP_H13 - RESERVED */ + /* GPP_H14 - RESERVED */ + _PAD_CFG_STRUCT(GPP_H15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + /* GPP_H16 - RESERVED */ + /* GPP_H17 - RESERVED */ + _PAD_CFG_STRUCT(GPP_H18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_H19, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H20, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H21, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H22, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H23, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAXPCIE1 */ + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_E4, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_E7, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATALED# */ + _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC0# */ + _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC1# */ + _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC2# */ + _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC3# */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, DEEP, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, DEEP, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SCLOCK */ + _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SLOAD */ + _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SDATAOUT1 */ + _PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SDATAOUT0 */ + PAD_CFG_GPO(GPP_F14, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC4# */ + _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC5# */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F18, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F19, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F22, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F23, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group SPI ------- */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD0 */ + _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD1 */ + _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD2 */ + _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_HPD3 */ + _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* EDP_HPD */ + _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* DDPB_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPC_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPC_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), /* DDPD_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), /* DDPD_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG0 */ + _PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG1 */ + _PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG2 */ + _PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* M2_SKT2_CFG3 */ + + /* ------- GPIO Group GPP_J ------- */ + _PAD_CFG_STRUCT(GPP_J0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* CNV_PA_BLANKING */ + _PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* n/a */ + _PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ + _PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ + PAD_CFG_GPI_TRIG_OWN(GPP_J4, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J5, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_J7, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_J8, 1, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_J9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_J10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_J11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ +}; + +/* Early pad configuration in romstage. */ +const struct pad_config early_gpio_table[] = { + /* GPP_B0 - Toggle SMBus mux to read DIMM SPDs */ + PAD_CFG_GPO(GPP_B0, 1, DEEP), +}; + +const struct pad_config *get_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *get_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/gpio.h new file mode 100644 index 0000000..018a08f --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef X11SCH_F_GPIO_H +#define X11SCH_F_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> +#include <intelblocks/gpio_defs.h> + +const struct pad_config *get_gpio_table(size_t *num); +const struct pad_config *get_early_gpio_table(size_t *num); + +#endif /* X11SCH_F__GPIO_H */ diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/variants.h b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/variants.h new file mode 100644 index 0000000..b7ade58 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/variants.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/cnl_memcfg_init.h> + +/* Return memory configuration structure */ +const struct cnl_mb_cfg *variant_memcfg_config(void); diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb new file mode 100644 index 0000000..9f936f5 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb @@ -0,0 +1,128 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[21]" = "1" + register "PcieRpEnable[22]" = "1" + register "PcieRpEnable[23]" = "1" + + register "PcieClkSrcUsage[0]" = "0x80" + register "PcieClkSrcUsage[1]" = "0x80" + register "PcieClkSrcUsage[2]" = "0x80" + register "PcieClkSrcUsage[3]" = "0x80" + register "PcieClkSrcUsage[4]" = "0x80" + register "PcieClkSrcUsage[5]" = "0x80" + register "PcieClkSrcUsage[6]" = "0x80" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieClkSrcUsage[8]" = "0x80" + register "PcieClkSrcUsage[9]" = "0x80" + register "PcieClkSrcUsage[10]" = "0x80" + register "PcieClkSrcUsage[11]" = "0x80" + register "PcieClkSrcUsage[12]" = "0x80" + register "PcieClkSrcUsage[13]" = "0x80" + register "PcieClkSrcUsage[14]" = "0x80" + register "PcieClkSrcUsage[15]" = "0x80" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[6]" = "6" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[9]" = "9" + register "PcieClkSrcClkReq[10]" = "10" + register "PcieClkSrcClkReq[11]" = "11" + register "PcieClkSrcClkReq[12]" = "12" + register "PcieClkSrcClkReq[13]" = "13" + register "PcieClkSrcClkReq[14]" = "14" + register "PcieClkSrcClkReq[15]" = "15" + + register "gen1_dec" = "0x000c0ca1" # IPMI KCS + + # USB Config 2.0/3.0 + + # USB OC0 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" + + # USB OC1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" + + # USB OC2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" + + # USB OC3 + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" + + # USB OC4 + register "usb2_ports[7]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC4)" + + # USB OC5 + register "usb2_ports[8]" = "USB2_PORT_MID(OC5)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC5)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC5)" + + # USB KCS + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + # USB OC6/7 - not connected + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # HECI + register "HeciEnabled" = "1" + # SPS doesn't support all command issued by FSP... + register "DisableHeciRetry" = "1" + + # Internal GFX + register "InternalGfx" = "1" + + # Disable S0ix + register "s0ix_enable" = "0" + + device domain 0 on + device pci 1b.0 hidden end # PCIe Bridge + device pci 1b.4 on end # onboard Ethernet + device pci 1b.5 on end # onboard Ethernet + device pci 1b.6 hidden end # onboard Ethernet + device pci 1b.7 hidden end # onboard Ethernet + device pci 1c.0 on end # PCIe Bridge + device pci 1c.1 on end # Aspeed Graphics + device pci 1c.4 on end # NVMe PCIE x4 + device pci 1d.0 on end # PCIE x4 + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/44578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Gerrit-Change-Number: 44578 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter@9elements.com> Gerrit-MessageType: newchange
Christian Walter has removed Martin Roth from this change. ( https://review.coreboot.org/c/coreboot/+/44578 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support ...................................................................... Removed reviewer Martin Roth. -- To view, visit https://review.coreboot.org/c/coreboot/+/44578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Gerrit-Change-Number: 44578 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter@9elements.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-MessageType: deleteReviewer
Christian Walter has removed Patrick Georgi from this change. ( https://review.coreboot.org/c/coreboot/+/44578 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support ...................................................................... Removed reviewer Patrick Georgi. -- To view, visit https://review.coreboot.org/c/coreboot/+/44578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Gerrit-Change-Number: 44578 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter@9elements.com> Gerrit-MessageType: deleteReviewer
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44578 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb: https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 117: device domain 0 on Please add missing root port numbers. -- To view, visit https://review.coreboot.org/c/coreboot/+/44578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Gerrit-Change-Number: 44578 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter@9elements.com> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-CC: Felix Singer <felixsinger@posteo.net> Gerrit-Comment-Date: Wed, 19 Aug 2020 12:45:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44578 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support ...................................................................... Patch Set 1: (99 comments) https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c: https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 12: _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_ALERT1# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 13: _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO0 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 14: _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_IO1 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 15: _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO2 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 16: _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO3 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 17: _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_CS0# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 18: _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 19: _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_ALERT0# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 20: _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* CLKRUN# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 21: _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_CLK */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 22: _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* CLKOUT_LPC1 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 23: _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 24: _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 25: _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SUSWARN#/SUSPWRDNACK */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 26: _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_RESET# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 27: _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSACK# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 32: _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 39: _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 40: _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 44: _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 50: _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S0# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 51: _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* PLTRST# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 52: _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SPKR */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 56: _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 61: _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* PCHHOT# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 68: _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 74: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 80: _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 82: _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C0_SDA */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 83: _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C0_SCL */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 84: _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C1_SDA */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 85: _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C1_SCL */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 88: _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 89: _PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 92: _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 95: _PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 96: _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 137: _PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ACPRESENT */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 138: _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* LAN_WAKE# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 139: _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PRWBTN# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 140: _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S3# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 141: _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S4# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 142: _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_A# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 143: _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 144: _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSCLK */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 146: _PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S5# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 152: _PAD_CFG_STRUCT(GPP_K0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 153: _PAD_CFG_STRUCT(GPP_K1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 154: _PAD_CFG_STRUCT(GPP_K2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 155: _PAD_CFG_STRUCT(GPP_K3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 164: _PAD_CFG_STRUCT(GPP_K12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 169: _PAD_CFG_STRUCT(GPP_K17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 171: _PAD_CFG_STRUCT(GPP_K19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SMI# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 174: _PAD_CFG_STRUCT(GPP_K22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 175: _PAD_CFG_STRUCT(GPP_K23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 180: _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 193: _PAD_CFG_STRUCT(GPP_H15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 196: _PAD_CFG_STRUCT(GPP_H18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 205: _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAXPCIE1 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 207: _PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 209: _PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 210: _PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 212: _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATALED# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 213: _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC0# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 214: _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC1# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 215: _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC2# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 216: _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC3# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 224: _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 226: _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 227: _PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 228: _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 229: _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SCLOCK */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 230: _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SLOAD */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 231: _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SDATAOUT1 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 232: _PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SDATAOUT0 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 234: _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC4# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 235: _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC5# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 249: _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD0 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 250: _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD1 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 251: _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD2 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 252: _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_HPD3 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 253: _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* EDP_HPD */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 254: _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_CTRLCLK */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 255: _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* DDPB_CTRLDATA */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 256: _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPC_CTRLCLK */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 257: _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPC_CTRLDATA */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 258: _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), /* DDPD_CTRLCLK */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 259: _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), /* DDPD_CTRLDATA */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 260: _PAD_CFG_STRUCT(GPP_I11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG0 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 261: _PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG1 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 262: _PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG2 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 263: _PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* M2_SKT2_CFG3 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 266: _PAD_CFG_STRUCT(GPP_J0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* CNV_PA_BLANKING */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 267: _PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* n/a */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 268: _PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 269: _PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 275: _PAD_CFG_STRUCT(GPP_J9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 276: _PAD_CFG_STRUCT(GPP_J10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/1/src/mainboard/supermicro/x1... PS1, Line 277: _PAD_CFG_STRUCT(GPP_J11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/44578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Gerrit-Change-Number: 44578 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter@9elements.com> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-CC: Felix Singer <felixsinger@posteo.net> Gerrit-CC: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Wed, 19 Aug 2020 13:22:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment
Angel Pons has uploaded a new patch set (#2) to the change originally created by Christian Walter. ( https://review.coreboot.org/c/coreboot/+/44578 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support ...................................................................... mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support Add initial support for another CFL variant. Quite hacky right now - but seems to boot Linux with Tianocore. Right now I need to enable, but hidden, the two additional NICs. Not sure where this comes from - maybe GPIOs. Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Signed-off-by: Christian Walter <christian.walter@9elements.com> --- M src/mainboard/supermicro/x11-lga1151v2-series/Kconfig M src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb 5 files changed, 421 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/44578/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Gerrit-Change-Number: 44578 Gerrit-PatchSet: 2 Gerrit-Owner: Christian Walter <christian.walter@9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Felix Singer <felixsinger@posteo.net> Gerrit-MessageType: newpatchset
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44578 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support ...................................................................... Patch Set 2: (99 comments) https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c: https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 19: _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_ALERT1# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 20: _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO0 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 21: _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_IO1 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 22: _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO2 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 23: _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO3 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 24: _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_CS0# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 25: _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 26: _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_ALERT0# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 27: _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* CLKRUN# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 28: _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_CLK */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 29: _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* CLKOUT_LPC1 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 30: _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 31: _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 32: _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SUSWARN#/SUSPWRDNACK */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 33: _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_RESET# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 34: _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSACK# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 39: _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 46: _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 47: _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 51: _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 57: _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S0# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 58: _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* PLTRST# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 59: _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SPKR */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 63: _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 68: _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* PCHHOT# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 75: _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 81: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 87: _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 89: _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C0_SDA */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 90: _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C0_SCL */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 91: _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C1_SDA */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 92: _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C1_SCL */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 95: _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 96: _PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 99: _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 102: _PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 103: _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 144: _PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ACPRESENT */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 145: _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* LAN_WAKE# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 146: _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PRWBTN# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 147: _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S3# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 148: _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S4# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 149: _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_A# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 150: _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 151: _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSCLK */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 153: _PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S5# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 159: _PAD_CFG_STRUCT(GPP_K0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 160: _PAD_CFG_STRUCT(GPP_K1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 161: _PAD_CFG_STRUCT(GPP_K2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 162: _PAD_CFG_STRUCT(GPP_K3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 171: _PAD_CFG_STRUCT(GPP_K12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 176: _PAD_CFG_STRUCT(GPP_K17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 178: _PAD_CFG_STRUCT(GPP_K19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SMI# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 181: _PAD_CFG_STRUCT(GPP_K22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 182: _PAD_CFG_STRUCT(GPP_K23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 187: _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 200: _PAD_CFG_STRUCT(GPP_H15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 203: _PAD_CFG_STRUCT(GPP_H18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 212: _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAXPCIE1 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 214: _PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 216: _PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 217: _PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 219: _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATALED# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 220: _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC0# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 221: _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC1# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 222: _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC2# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 223: _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC3# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 231: _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 233: _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 234: _PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 235: _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 236: _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SCLOCK */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 237: _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SLOAD */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 238: _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SDATAOUT1 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 239: _PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SDATAOUT0 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 241: _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC4# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 242: _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC5# */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 256: _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD0 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 257: _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD1 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 258: _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD2 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 259: _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_HPD3 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 260: _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* EDP_HPD */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 261: _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_CTRLCLK */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 262: _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* DDPB_CTRLDATA */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 263: _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPC_CTRLCLK */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 264: _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPC_CTRLDATA */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 265: _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), /* DDPD_CTRLCLK */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 266: _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), /* DDPD_CTRLDATA */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 267: _PAD_CFG_STRUCT(GPP_I11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG0 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 268: _PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG1 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 269: _PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG2 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 270: _PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* M2_SKT2_CFG3 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 273: _PAD_CFG_STRUCT(GPP_J0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* CNV_PA_BLANKING */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 274: _PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* n/a */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 275: _PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 276: _PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 282: _PAD_CFG_STRUCT(GPP_J9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 283: _PAD_CFG_STRUCT(GPP_J10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters https://review.coreboot.org/c/coreboot/+/44578/2/src/mainboard/supermicro/x1... PS2, Line 284: _PAD_CFG_STRUCT(GPP_J11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/44578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Gerrit-Change-Number: 44578 Gerrit-PatchSet: 2 Gerrit-Owner: Christian Walter <christian.walter@9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Felix Singer <felixsinger@posteo.net> Gerrit-Comment-Date: Mon, 28 Sep 2020 21:33:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44578 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support ...................................................................... Patch Set 3: (99 comments) File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/5b6dd8a2_12272867 PS3, Line 19: _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_ALERT1# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/822a372a_3deda580 PS3, Line 20: _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO0 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/6278cc87_2e4ac49d PS3, Line 21: _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_IO1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/43f059e0_6f16a754 PS3, Line 22: _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO2 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/0178e2a1_8aa99213 PS3, Line 23: _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO3 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/c06a59bc_0788de6b PS3, Line 24: _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_CS0# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/fba75718_ea42035e PS3, Line 25: _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/6aa02301_f1346e35 PS3, Line 26: _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_ALERT0# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/d34c63e0_dd15a890 PS3, Line 27: _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* CLKRUN# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/8160f130_26d65c84 PS3, Line 28: _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_CLK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/58a634c5_1f9f56a8 PS3, Line 29: _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* CLKOUT_LPC1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/65e231ad_ce2aa38a PS3, Line 30: _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/21b2c70f_19078c10 PS3, Line 31: _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/2b1e3ecb_00d01849 PS3, Line 32: _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SUSWARN#/SUSPWRDNACK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/a061d111_4d9cb15d PS3, Line 33: _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_RESET# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/71092aa7_0a8c22f0 PS3, Line 34: _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSACK# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/cde3f196_3f51eecc PS3, Line 39: _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/95b13c20_c597443b PS3, Line 46: _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/3f66d436_09490d77 PS3, Line 47: _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/213ca756_65ec2a29 PS3, Line 51: _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/a229145c_f192b69d PS3, Line 57: _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S0# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/b1b96089_d714be53 PS3, Line 58: _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* PLTRST# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/29e84109_78cf97ff PS3, Line 59: _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SPKR */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/f888ca24_c3fef436 PS3, Line 63: _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/f33f0f77_3cfacae6 PS3, Line 68: _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* PCHHOT# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/dd5b2d9e_25c4b17a PS3, Line 75: _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/c421dee7_6d2b1d64 PS3, Line 81: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/3e207aab_2b4fe6ea PS3, Line 87: _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/8fa58a60_a97533e3 PS3, Line 89: _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C0_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/f176a75e_ed860446 PS3, Line 90: _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C0_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/efe92312_7ade5280 PS3, Line 91: _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C1_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/2e02f600_b4699523 PS3, Line 92: _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C1_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/908c38f3_495ad1b3 PS3, Line 95: _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/0e469b58_ab7da7ff PS3, Line 96: _PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/f97574da_60fa85a9 PS3, Line 99: _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/7779f4a3_e5bc832f PS3, Line 102: _PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/d230a530_47b1ef45 PS3, Line 103: _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/9dacb388_ef1c35bb PS3, Line 144: _PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ACPRESENT */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/fcca1531_562db94b PS3, Line 145: _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* LAN_WAKE# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/d8354bf0_1cdbc0d9 PS3, Line 146: _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PRWBTN# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/863e6a18_17f64cb3 PS3, Line 147: _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S3# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/4609670c_fa333ece PS3, Line 148: _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S4# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/353a8f12_974a0cad PS3, Line 149: _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_A# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/fbc11566_e8be78d3 PS3, Line 150: _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/9fd62505_f3a71d2f PS3, Line 151: _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSCLK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/72b9acd9_f911f027 PS3, Line 153: _PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S5# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/13130ce5_ab3f0d0a PS3, Line 159: _PAD_CFG_STRUCT(GPP_K0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/f00dbd54_a237af64 PS3, Line 160: _PAD_CFG_STRUCT(GPP_K1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/19e9fc2c_a1791e43 PS3, Line 161: _PAD_CFG_STRUCT(GPP_K2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/892b01a9_04172b32 PS3, Line 162: _PAD_CFG_STRUCT(GPP_K3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/c64cb092_32f1e475 PS3, Line 171: _PAD_CFG_STRUCT(GPP_K12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/869800ab_03431b98 PS3, Line 176: _PAD_CFG_STRUCT(GPP_K17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/a162584b_59aa0268 PS3, Line 178: _PAD_CFG_STRUCT(GPP_K19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SMI# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/fae72c34_6d12ca0b PS3, Line 181: _PAD_CFG_STRUCT(GPP_K22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/b0c9312a_a65ae583 PS3, Line 182: _PAD_CFG_STRUCT(GPP_K23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/0576e0b5_14bbebba PS3, Line 187: _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/6b8280c4_a7456da9 PS3, Line 200: _PAD_CFG_STRUCT(GPP_H15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/82962c0d_ecccba94 PS3, Line 203: _PAD_CFG_STRUCT(GPP_H18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/a9f699e4_053c67bf PS3, Line 212: _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAXPCIE1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/fc3e65a6_a4d6258c PS3, Line 214: _PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/50e223c5_c0df8dfc PS3, Line 216: _PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/78a7ad0b_c959c9dd PS3, Line 217: _PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/3dc839d8_027dec86 PS3, Line 219: _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATALED# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/17cd5434_ec61b6e9 PS3, Line 220: _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC0# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/faa060cb_997f6bec PS3, Line 221: _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC1# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/302ed667_86c51d32 PS3, Line 222: _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC2# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/a828e165_87409769 PS3, Line 223: _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC3# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/4a241ac1_b343df2b PS3, Line 231: _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/b5e3cf02_3eec2df5 PS3, Line 233: _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/a02ac951_b5d8c867 PS3, Line 234: _PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/3681bca5_a9b2fb5f PS3, Line 235: _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/a327b633_6e45eb97 PS3, Line 236: _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SCLOCK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/50d4f04a_9a2bf2bc PS3, Line 237: _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SLOAD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/f17b0d73_1a46dd00 PS3, Line 238: _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SDATAOUT1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/7eb4a9d4_c5b5d5cb PS3, Line 239: _PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SDATAOUT0 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/d8addc15_22c9f1aa PS3, Line 241: _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC4# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/32137e37_985e1c80 PS3, Line 242: _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC5# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/bc7359b4_9eece079 PS3, Line 256: _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD0 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/6f8513d0_40093e75 PS3, Line 257: _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/f1ae760a_72aa6ab3 PS3, Line 258: _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD2 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/4a1e6297_6080ed90 PS3, Line 259: _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_HPD3 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/c7157cab_20e9e953 PS3, Line 260: _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* EDP_HPD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/e892e15c_1d2e5c4b PS3, Line 261: _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_CTRLCLK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/d6fd9fb1_fe75e6fc PS3, Line 262: _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* DDPB_CTRLDATA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/96d86a52_53f780b5 PS3, Line 263: _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPC_CTRLCLK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/a96b6507_53707989 PS3, Line 264: _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPC_CTRLDATA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/37bd1738_eefffacd PS3, Line 265: _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), /* DDPD_CTRLCLK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/608b1bfa_5bccc230 PS3, Line 266: _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), /* DDPD_CTRLDATA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/da8eecc8_52255f1d PS3, Line 267: _PAD_CFG_STRUCT(GPP_I11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG0 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/4cfe77b5_7ccccb05 PS3, Line 268: _PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/d74be10f_11830aa3 PS3, Line 269: _PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG2 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/c2074e08_6b45a46c PS3, Line 270: _PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* M2_SKT2_CFG3 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/566bd326_fad25acf PS3, Line 273: _PAD_CFG_STRUCT(GPP_J0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* CNV_PA_BLANKING */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/d3f36b7c_b87c04b8 PS3, Line 274: _PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* n/a */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/e7798e66_cb76dbf1 PS3, Line 275: _PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/ce5ee102_a8ebd296 PS3, Line 276: _PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/302a153f_483e2852 PS3, Line 282: _PAD_CFG_STRUCT(GPP_J9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/27d041e6_e145b3ba PS3, Line 283: _PAD_CFG_STRUCT(GPP_J10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120956): https://review.coreboot.org/c/coreboot/+/44578/comment/91b3ecc5_ec2f99e2 PS3, Line 284: _PAD_CFG_STRUCT(GPP_J11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/44578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Gerrit-Change-Number: 44578 Gerrit-PatchSet: 3 Gerrit-Owner: Christian Walter <christian.walter@9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Mon, 07 Jun 2021 16:31:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment
Attention is currently required from: Christian Walter, Angel Pons. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44578 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support ...................................................................... Patch Set 4: (99 comments) File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/0cb705c3_98f0c985 PS4, Line 19: _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_ALERT1# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/efc9e0fe_2d1fe5a6 PS4, Line 20: _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO0 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/ab15a44f_6fa1b50c PS4, Line 21: _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_IO1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/d271fd9a_50f17e52 PS4, Line 22: _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO2 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/44e7bc4a_8f3c40d9 PS4, Line 23: _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO3 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/2c60016d_86f958df PS4, Line 24: _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_CS0# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/6e7305ff_67d020a5 PS4, Line 25: _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/2cc4b599_ec7cae19 PS4, Line 26: _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_ALERT0# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/c567070b_14c195b9 PS4, Line 27: _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* CLKRUN# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/58c5dafa_b88bb754 PS4, Line 28: _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_CLK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/32c58461_92bf963a PS4, Line 29: _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* CLKOUT_LPC1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/d627794b_fe366035 PS4, Line 30: _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/1fa10bdd_d4bdf305 PS4, Line 31: _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/b55ed2da_5b1c2713 PS4, Line 32: _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SUSWARN#/SUSPWRDNACK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/0508c347_d63ddb5b PS4, Line 33: _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_RESET# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/4a7b8bdc_de794025 PS4, Line 34: _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSACK# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/dd5e4080_17302de6 PS4, Line 39: _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/e580b00e_3206dbac PS4, Line 46: _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/2be67652_89125e8d PS4, Line 47: _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/9af43a9e_ae244cc0 PS4, Line 51: _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/c14f07b5_d8638a1c PS4, Line 57: _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S0# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/1b9c2b0c_0ea45a74 PS4, Line 58: _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* PLTRST# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/dc76a7f0_934ff267 PS4, Line 59: _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SPKR */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/34d609e7_082332fe PS4, Line 63: _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/4ac7dfc0_8dba7297 PS4, Line 68: _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* PCHHOT# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/44ce542f_79102fa7 PS4, Line 75: _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/ba098995_3c02a90b PS4, Line 81: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/f078d48d_8241af4a PS4, Line 87: _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/61e44ce8_d078388a PS4, Line 89: _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C0_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/f4064860_a2127c3f PS4, Line 90: _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C0_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/69f3457b_1fd0418a PS4, Line 91: _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C1_SDA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/29f53f0e_294afd1d PS4, Line 92: _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C1_SCL */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/4303f266_29259d5a PS4, Line 95: _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/5aa6cb31_9b166708 PS4, Line 96: _PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/6cd54a20_96421b45 PS4, Line 99: _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/cc3532f5_e9e50f7b PS4, Line 102: _PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/de595c2e_371f8965 PS4, Line 103: _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/f694c611_78ffca9a PS4, Line 144: _PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ACPRESENT */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/c2752437_f819c48d PS4, Line 145: _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* LAN_WAKE# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/d96ee1a8_b0f72f7f PS4, Line 146: _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PRWBTN# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/a4ec9fd8_594eb035 PS4, Line 147: _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S3# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/b38e0a50_e054f5b6 PS4, Line 148: _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S4# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/a821a734_beaf64d6 PS4, Line 149: _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_A# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/6787f9bf_911b5453 PS4, Line 150: _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/828acd19_69b4eb53 PS4, Line 151: _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSCLK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/7310847d_b119b7ba PS4, Line 153: _PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S5# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/efb50c5f_fbc149eb PS4, Line 159: _PAD_CFG_STRUCT(GPP_K0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/52469679_f1972cde PS4, Line 160: _PAD_CFG_STRUCT(GPP_K1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/abe5e634_6af68126 PS4, Line 161: _PAD_CFG_STRUCT(GPP_K2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/6e83a34b_021165a6 PS4, Line 162: _PAD_CFG_STRUCT(GPP_K3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/a96ab8e7_3721dd7d PS4, Line 171: _PAD_CFG_STRUCT(GPP_K12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/b4687dbe_5ed64eeb PS4, Line 176: _PAD_CFG_STRUCT(GPP_K17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/b0c13609_ba62e4e8 PS4, Line 178: _PAD_CFG_STRUCT(GPP_K19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SMI# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/4ffcfd91_6e3939a1 PS4, Line 181: _PAD_CFG_STRUCT(GPP_K22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/0cfca00c_f4ab1636 PS4, Line 182: _PAD_CFG_STRUCT(GPP_K23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/6733ab01_27927e0f PS4, Line 187: _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/e2240a56_86516fce PS4, Line 200: _PAD_CFG_STRUCT(GPP_H15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/1a361506_015b65c7 PS4, Line 203: _PAD_CFG_STRUCT(GPP_H18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/4b57ba45_320816c6 PS4, Line 212: _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAXPCIE1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/f70d4aa9_f29bfcfe PS4, Line 214: _PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/3da2f085_61b62687 PS4, Line 216: _PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/d748ac39_6965e56a PS4, Line 217: _PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/52cb220a_eb4262d0 PS4, Line 219: _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATALED# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/f59df78e_18d2abf0 PS4, Line 220: _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC0# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/d8b36923_ca961c6c PS4, Line 221: _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC1# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/2bf57719_2c1828c3 PS4, Line 222: _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC2# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/2c70f643_56ffaf6c PS4, Line 223: _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC3# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/e82b2eb1_ec1279a0 PS4, Line 231: _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/a0d00072_68ce6ddf PS4, Line 233: _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/2fc9ef69_93d28dbc PS4, Line 234: _PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/51bf61dc_7a619d5f PS4, Line 235: _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/f638cba9_c19425a8 PS4, Line 236: _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SCLOCK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/9344de3c_dfcde42b PS4, Line 237: _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SLOAD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/5f33de8a_df83074e PS4, Line 238: _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SDATAOUT1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/99600ea4_a2361fb0 PS4, Line 239: _PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SDATAOUT0 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/bc9e0c56_f8e3c5bc PS4, Line 241: _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC4# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/37247e32_001f71bd PS4, Line 242: _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC5# */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/9f142e6e_3066b2e0 PS4, Line 256: _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD0 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/fa55a02d_ab3c212c PS4, Line 257: _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/459bbf9f_1157c291 PS4, Line 258: _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD2 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/2a607c0a_8c40e88d PS4, Line 259: _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_HPD3 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/0e29bb60_33e37e3f PS4, Line 260: _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* EDP_HPD */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/1dfc9194_45c5ee7a PS4, Line 261: _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_CTRLCLK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/c12fabd9_b5529a6e PS4, Line 262: _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* DDPB_CTRLDATA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/578a249b_49e20679 PS4, Line 263: _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPC_CTRLCLK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/1be897fa_cdf19fab PS4, Line 264: _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPC_CTRLDATA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/28edfe39_02db8554 PS4, Line 265: _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), /* DDPD_CTRLCLK */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/9cdc8ba8_62898213 PS4, Line 266: _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), /* DDPD_CTRLDATA */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/f8b9e1ab_a4e0dd26 PS4, Line 267: _PAD_CFG_STRUCT(GPP_I11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG0 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/46d4e36f_5471a128 PS4, Line 268: _PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/32b14b3a_94bfda58 PS4, Line 269: _PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG2 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/98b2fd59_79fc7c61 PS4, Line 270: _PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* M2_SKT2_CFG3 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/1eca545b_b2595463 PS4, Line 273: _PAD_CFG_STRUCT(GPP_J0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* CNV_PA_BLANKING */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/7b299a77_3ebf1b1c PS4, Line 274: _PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* n/a */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/cba013cc_6281a248 PS4, Line 275: _PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/e31e6f33_901e3987 PS4, Line 276: _PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/c3b9275f_3b91a213 PS4, Line 282: _PAD_CFG_STRUCT(GPP_J9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/840f785a_5f05218b PS4, Line 283: _PAD_CFG_STRUCT(GPP_J10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-122590): https://review.coreboot.org/c/coreboot/+/44578/comment/d5d79c95_70057f53 PS4, Line 284: _PAD_CFG_STRUCT(GPP_J11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/44578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Gerrit-Change-Number: 44578 Gerrit-PatchSet: 4 Gerrit-Owner: Christian Walter <christian.walter@9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Attention: Christian Walter <christian.walter@9elements.com> Gerrit-Attention: Angel Pons <th3fanbus@gmail.com> Gerrit-Comment-Date: Wed, 23 Jun 2021 14:44:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44578?usp=email ) Change subject: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support ...................................................................... Abandoned This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author. -- To view, visit https://review.coreboot.org/c/coreboot/+/44578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Gerrit-Change-Number: 44578 Gerrit-PatchSet: 4 Gerrit-Owner: Christian Walter <christian.walter@9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-MessageType: abandon
Felix Singer has restored this change. ( https://review.coreboot.org/c/coreboot/+/44578?usp=email ) Change subject: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/44578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: restore Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Gerrit-Change-Number: 44578 Gerrit-PatchSet: 4 Gerrit-Owner: Christian Walter <christian.walter@9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44578?usp=email ) Change subject: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/44578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Gerrit-Change-Number: 44578 Gerrit-PatchSet: 4 Gerrit-Owner: Christian Walter <christian.walter@9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
participants (5)
-
Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
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Christian Walter (Code Review)
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Felix Singer (Code Review)
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Martin L Roth (Code Review)