kayalvizhi dhandapani (kayalvizhid@ami.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7026 -gerrit commit 9e0615ec127214cbaf85bda1091f6f5220e52d3e Author: Kayalvizhi Dhandapani <kayalvizhid@ami.com> Date: Tue Oct 7 14:34:01 2014 -0400 intel/fsp_baytrail: Fix SMM/SMI When enabled SMM, the boot stopped while patching up global NVS in DSDT. Both CPUs are assigned the same SMBASE address. Updated cpu_smm_do_relocation() function so that each cpu get different SMBASE address Change-Id: I77cd27d3a4f207411a689b5be572b4406a03f16b Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com> --- src/mainboard/intel/bayleybay_fsp/devicetree.cb | 2 +- src/soc/intel/fsp_baytrail/Kconfig | 6 +++++- src/soc/intel/fsp_baytrail/cpu.c | 10 ++++++++-- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb index befd3dc..356c8df 100644 --- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb +++ b/src/mainboard/intel/bayleybay_fsp/devicetree.cb @@ -27,7 +27,7 @@ chip soc/intel/fsp_baytrail register "SataMode" = "SATA_MODE_AHCI" register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" - register "MrcInitTsegSize" = "TSEG_SIZE_DEFAULT" + register "MrcInitTsegSize" = "TSEG_SIZE_8_MB" register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT" register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index cb4757b..7fc72ac 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -31,12 +31,16 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select DYNAMIC_CBMEM + select HAVE_SMI_HANDLER select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES select PARALLEL_MP - select REG_SCRIPT + select REG_SCRIPT + select SMM_MODULES + select SMM_TSEG + select BAYTRAIL_SMM select SMP select SPI_FLASH select SSE2 diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index f260880..6f1e9c4 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -148,14 +148,20 @@ static void adjust_apic_id_map(struct smm_loader_params *smm_params) runtime->apic_id_to_cpu[i] = mp_get_apic_id(i); } -static void asmlinkage -cpu_smm_do_relocation(void *arg, int cpu, const struct smm_runtime *runtime) +static void asmlinkage cpu_smm_do_relocation(void *arg) { #ifndef CONFIG_MAX_CPUS #error CONFIG_MAX_CPUS must be set. #endif msr_t smrr; em64t100_smm_state_save_area_t *smm_state; + const struct smm_module_params *p; + const struct smm_runtime *runtime; + int cpu; + + p = arg; + runtime = p->runtime; + cpu = p->cpu; if (cpu >= CONFIG_MAX_CPUS) { printk(BIOS_CRIT,