Change in coreboot[4.11_branch]: soc/intel/fsp_broadwell_de: examine ACM status at romstage entry
Hello Philipp Deppenwiese, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42713 to review the following change. Change subject: soc/intel/fsp_broadwell_de: examine ACM status at romstage entry ...................................................................... soc/intel/fsp_broadwell_de: examine ACM status at romstage entry When INTEL_TXT is set, at romstage entry check if startup ACM worked correctly by probing TXT_ERROR register. Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I6f423df8b05dc44220a9bad3674f687bac94e335 --- M src/soc/intel/fsp_broadwell_de/romstage/romstage.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/42713/1 diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 8438b10..9699927 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -38,6 +38,9 @@ #include <soc/ubox.h> #include <build.h> +#include <security/intel/txt/txt.h> +#include <security/intel/txt/txt_register.h> + static void init_rtc(void) { u16 gen_pmcon3 = pci_read_config16(PCI_DEV(0, LPC_DEV, LPC_FUNC), GEN_PMCON_3); @@ -156,6 +159,12 @@ early_iio_hide(); timestamp_add_now(TS_BEFORE_INITRAM); post_code(0x48); + + if (CONFIG(INTEL_TXT)) { + printk(BIOS_DEBUG, "Check TXT_ERROR register\n"); + intel_txt_log_acm_error(read32((void *)TXT_ERROR)); + } + /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB -- To view, visit https://review.coreboot.org/c/coreboot/+/42713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I6f423df8b05dc44220a9bad3674f687bac94e335 Gerrit-Change-Number: 42713 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang@fb.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Gerrit-MessageType: newchange
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42713 ) Change subject: soc/intel/fsp_broadwell_de: examine ACM status at romstage entry ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/42713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I6f423df8b05dc44220a9bad3674f687bac94e335 Gerrit-Change-Number: 42713 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Zhang <jonzhang@fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Tue, 21 Jul 2020 10:23:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42713 ) Change subject: soc/intel/fsp_broadwell_de: examine ACM status at romstage entry ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I6f423df8b05dc44220a9bad3674f687bac94e335 Gerrit-Change-Number: 42713 Gerrit-PatchSet: 5 Gerrit-Owner: Jonathan Zhang <jonzhang@fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Sat, 08 Aug 2020 20:27:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Philipp Deppenwiese has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42713 ) Change subject: soc/intel/fsp_broadwell_de: examine ACM status at romstage entry ...................................................................... soc/intel/fsp_broadwell_de: examine ACM status at romstage entry When INTEL_TXT is set, at romstage entry check if startup ACM worked correctly by probing TXT_ERROR register. Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I6f423df8b05dc44220a9bad3674f687bac94e335 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42713 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> --- M src/soc/intel/fsp_broadwell_de/romstage/romstage.c 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 8438b10..9699927 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -38,6 +38,9 @@ #include <soc/ubox.h> #include <build.h> +#include <security/intel/txt/txt.h> +#include <security/intel/txt/txt_register.h> + static void init_rtc(void) { u16 gen_pmcon3 = pci_read_config16(PCI_DEV(0, LPC_DEV, LPC_FUNC), GEN_PMCON_3); @@ -156,6 +159,12 @@ early_iio_hide(); timestamp_add_now(TS_BEFORE_INITRAM); post_code(0x48); + + if (CONFIG(INTEL_TXT)) { + printk(BIOS_DEBUG, "Check TXT_ERROR register\n"); + intel_txt_log_acm_error(read32((void *)TXT_ERROR)); + } + /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB -- To view, visit https://review.coreboot.org/c/coreboot/+/42713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I6f423df8b05dc44220a9bad3674f687bac94e335 Gerrit-Change-Number: 42713 Gerrit-PatchSet: 6 Gerrit-Owner: Jonathan Zhang <jonzhang@fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-MessageType: merged
participants (3)
-
Angel Pons (Code Review) -
Jonathan Zhang (Code Review) -
Philipp Deppenwiese (Code Review)