Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36357 ) Change subject: soc/intel/icelake: set LT_LOCK_MEMORY at end of POST ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/36357/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/36357/2//COMMIT_MSG@7 PS2, Line 7: icelake Nico Huber:

Patch Set 2: -Code-Review

Thinking about this, MP init works different with FSP2.1, so it should be tested, IMHO. Might even be a no-op.

-- To view, visit https://review.coreboot.org/c/coreboot/+/36357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib728e61bc874acf505348e72c00a99e0a6efd2cb Gerrit-Change-Number: 36357 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h@gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Sat, 02 Nov 2019 13:14:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment