Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49180 ) Change subject: [UNTESTED] sb/intel/bd82x6x: Correct conditional IOBP update ...................................................................... [UNTESTED] sb/intel/bd82x6x: Correct conditional IOBP update This one IOBP register only needs to be updated if its bit 20 is zero. Change-Id: I7c9e268f9fdf0ae57c6f453f8bce160b177889a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/49180/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index e86297b..251ff86 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -181,8 +181,8 @@ pch_iobp_update(0xea0000a9, ~(0x3ff << 3), 0x29f << 3); pch_iobp_update(SATA_IOBP_SP1G3IR, ~(0xff << 16 | 0x3f << 8), 0x88 << 16 | 3 << 8); - /* TODO: Needs special handling */ - pch_iobp_update(0xea007f05, 0, 0x00010642); + if ((pch_iobp_read(0xea007f05) & 1 << 20) == 0) + pch_iobp_update(0xea007f05, ~(7 << 8), 6 << 8); pch_iobp_update(0xea0040b7, ~0xffff, 0xc91c); pch_iobp_update(0xea0040b8, ~0xffff, 0xc91c); -- To view, visit https://review.coreboot.org/c/coreboot/+/49180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c9e268f9fdf0ae57c6f453f8bce160b177889a4 Gerrit-Change-Number: 49180 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-MessageType: newchange