Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38989 ) Change subject: [TEST] Add support for link time optimization ...................................................................... Patch Set 6: I worked around that error with the hack below. ``` $ git diff diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 1615e75c9a..d818205ab7 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -78,11 +78,7 @@ $(1)-S-ccopts += -I. $$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs) @printf " LINK $$(subst $$(obj)/,,$$(@))\n" $$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) -Wl,--whole-archive,--start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) -Wl,--no-whole-archive $$(COMPILER_RT_$(1)) -Wl,--end-group -T $(call src-to-obj,$(1),$(dir)/memlayout.ld) -Wl,--oformat=$(2) - -LANG=C LC_ALL= $$(OBJCOPY_$(1)) --only-section .illegal_globals $$(@) $$(objcbfs)/$(1)_null.offenders >/dev/null 2>&1 - if [ -z "$$$$($$(NM_$(1)) $$(objcbfs)/$(1)_null.offenders 2>&1 | grep 'no symbols')" ];then \ - echo "Forbidden global variables in $(1):"; \ - $$(NM_$(1)) $$(objcbfs)/$(1)_null.offenders; false; \ - fi + -LANG=C LC_ALL= $$(OBJCOPY_$(1)) --only-section $$(@) $$(objcbfs)/$(1)_null.offenders >/dev/null 2>&1 endef ############################################################################### diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 92b26a0877..05e317dd29 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -83,10 +83,6 @@ */ . = 0xffffff00; -.illegal_globals . : { - *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) - *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) -} _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); #if CONFIG(PAGING_IN_CACHE_AS_RAM) ``` romstage is 9.3 % smaller, and ramstage around 11 %. ``` $ build/cbfstool build/coreboot.rom print FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 170260 none fallback/ramstage 0x29a00 stage 105668 none […] ``` No LTO: ``` fallback/romstage 0x80 stage 185012 none fallback/ramstage 0x2d3c0 stage 119027 none ``` With that, I reach the payload phase, but the drive connected to the SATA port is not detected by the payload (GRUB, SeaBIOS) and GNU/Linux (5.7-rc1 and 5.5) – also not with warm reboot. I cannot spot a difference in the coreboot log [1]. Booting from USB works. [1]: https://paste.flashrom.org/view.php?id=3306 -- To view, visit https://review.coreboot.org/c/coreboot/+/38989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48c31ea8b1b57276125cffdac44c7c16642547ac Gerrit-Change-Number: 38989 Gerrit-PatchSet: 6 Gerrit-Owner: Jacob Garber <jgarber1@ualberta.ca> Gerrit-Reviewer: Jacob Garber <jgarber1@ualberta.ca> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski@3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Reviewer: ron minnich <rminnich@gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas@noos.fr> Gerrit-Comment-Date: Sun, 26 Apr 2020 11:12:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment