Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44239 ) Change subject: cpu/intel/model_6xx: Update ucode before enabling cache ...................................................................... cpu/intel/model_6xx: Update ucode before enabling cache Other similar CPUs update the microcode first, so do the same here. Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d Signed-off-by: Angel Pons <th3fanbus@gmail.com> --- M src/cpu/intel/model_6xx/model_6xx_init.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44239/1 diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index a6944d3..f394b5f 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -9,14 +9,14 @@ static void model_6xx_init(struct device *dev) { + /* Update the microcode */ + intel_update_microcode_from_cbfs(); + /* Turn on caching if we haven't already */ x86_enable_cache(); x86_setup_mtrrs(); x86_mtrr_check(); - /* Update the microcode */ - intel_update_microcode_from_cbfs(); - /* Enable the local CPU APICs */ setup_lapic(); }; -- To view, visit https://review.coreboot.org/c/coreboot/+/44239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d Gerrit-Change-Number: 44239 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-MessageType: newchange