Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 ) Change subject: src/mainboard/asus: Add H110M-E/M.2 mainboard support ...................................................................... Patch Set 18: (16 comments) Chapter bazillionth: The devicetree :) Adding Maxim Polyakov as reviewer, as he ported asrock/h110m and probably knows Skylake stuff better than I do https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb: https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 78: # VR Settings Configuration for 5 Domains All the VR (Voltage Regulator) settings, if taken from asrock/h110m, should work. https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 145: register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V I think you don't need this https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 190: register "SerialIoDevMode" = "{ \ I don't think these should be enabled either https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 212: 6 In your case, this is root port 8 https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 213: register "PcieRpEnable[5]" = "1" : # Enable CLKREQ# : register "PcieRpClkReqSupport[5]" = "1" : # Use SRCCLKREQ1# : register "PcieRpClkReqNumber[5]" = "1" : # Enable Advanced Error Reporting : register "PcieRpAdvancedErrorReporting[5]" = "1" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[5]" = "1" : # Use CLK SRC 1 : register "PcieRpClkSrcNumber[5]" = "1" s/[5]/[7] (replace '[5]' with '[7]' on this section) https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 225: # Enable Root port 5 (x1) for PCIE slot. This one is correct https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 240: 7 In your case, this is root port 9 https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 241: register "PcieRpEnable[6]" = "1" : # Enable CLKREQ# : register "PcieRpClkReqSupport[6]" = "1" : # Use SRCCLKREQ3# : register "PcieRpClkReqNumber[6]" = "3" : # Enable Advanced Error Reporting : register "PcieRpAdvancedErrorReporting[6]" = "1" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[6]" = "1" : # Use CLK SRC 3 : register "PcieRpClkSrcNumber[6]" = "3" : # Use Hot Plug subsystem : register "PcieRpHotPlug[6]" = "1" s/[6]/[8] (replace '[6]' with '[8]' on this section) https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 278: device pci 14.2 on # Thermal Subsystem : subsystemid 0x1849 0xa131 : end Disable this device: device pci 14.2 off end # Thermal Subsystem https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 285: device pci 16.0 on # Management Engine Interface 1 : subsystemid 0x1849 0xa131 : end Looks disabled on your board, but it might just be hidden https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 302: 1c.4 on 1c.4 off https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 303: 1c.5 on 1c.5 off https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 304: 1c.6 on 1c.6 off https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 305: 1c.7 off 1c.7 on https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 306: 1d.0 off 1d.0 on https://review.coreboot.org/c/coreboot/+/34603/18/src/mainboard/asus/h110m-e... PS18, Line 319: c The values you should write here are the ones superiotool says. Make sure the LDNs (device pnp 2e.X) are correct. If in doubt, send a log of 'superiotool -d' -- To view, visit https://review.coreboot.org/c/coreboot/+/34603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Gerrit-Change-Number: 34603 Gerrit-PatchSet: 18 Gerrit-Owner: Pavel Sayekat Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot@felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Maxim Polyakov <m.poliakov@yahoo.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak@gmail.com> Gerrit-Reviewer: Nico Huber <nico.h@gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Pavel Sayekat Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Sat, 03 Aug 2019 10:34:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment