HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40802 ) Change subject: nb/intel/i945/memmap: Convert to 96 characters line length ...................................................................... nb/intel/i945/memmap: Convert to 96 characters line length Change-Id: I2ef938573e75022dcb31c935dde7d3055e7a53f0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> --- M src/northbridge/intel/i945/memmap.c 1 file changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/40802/1 diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index ee9f100..0183ea2 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -65,11 +65,10 @@ return (void *) top_of_ram; } -/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ +/* Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) { - static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, - 48, 64 }; + static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64 }; if (gms >= ARRAY_SIZE(ggc2uma)) die("Bad Graphics Mode Select (GMS) setting.\n"); @@ -91,9 +90,7 @@ * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); - } -- To view, visit https://review.coreboot.org/c/coreboot/+/40802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ef938573e75022dcb31c935dde7d3055e7a53f0 Gerrit-Change-Number: 40802 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas@noos.fr> Gerrit-MessageType: newchange