September 2026 - coreboot-gerrit

[XS] Change in coreboot[main]: ec/google/chromeec: Give BAT1 a unique _UID
by Caveh Jalali (Code Review) Sept. 30, 2026

Sept. 30, 2026

Attention is currently required from: Boris Mittelberg, Matt DeVillier, Subrata Banik. Caveh Jalali has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/95894?usp=email ) Change subject: ec/google/chromeec: Give BAT1 a unique _UID ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/95894?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04797951d615a587a96a2373f7b5a4a6ae9d8365 Gerrit-Change-Number: 95894 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Sep 2026 23:53:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: ec/google/chromeec: Make battery full workaround compile-time only
by Caveh Jalali (Code Review) Sept. 30, 2026

Sept. 30, 2026

Attention is currently required from: Boris Mittelberg, Matt DeVillier, Subrata Banik. Caveh Jalali has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/95895?usp=email ) Change subject: ec/google/chromeec: Make battery full workaround compile-time only ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/95895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If73d445f6f1bf25401af2ab590f1b0e378a00eed Gerrit-Change-Number: 95895 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Sep 2026 23:52:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: ec/google/chromeec: Factor AMD DPTC update into a helper method
by Caveh Jalali (Code Review) Sept. 30, 2026

Sept. 30, 2026

Attention is currently required from: Boris Mittelberg, Matt DeVillier, Subrata Banik. Caveh Jalali has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/95889?usp=email ) Change subject: ec/google/chromeec: Factor AMD DPTC update into a helper method ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/95889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6992ca304864dbecae9e0ec57425ff81297fe376 Gerrit-Change-Number: 95889 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Sep 2026 23:51:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: ec/google/chromeec: Use relative references to EC0 objects
by Caveh Jalali (Code Review) Sept. 30, 2026

Sept. 30, 2026

Attention is currently required from: Boris Mittelberg, Matt DeVillier. Caveh Jalali has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/95888?usp=email ) Change subject: ec/google/chromeec: Use relative references to EC0 objects ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/95888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73ba4492c04c5f041fbbda9b9a375e447bd8bc46 Gerrit-Change-Number: 95888 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Sep 2026 23:50:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: ec/google/chromeec: Drop unused COM1 device from superio.asl
by Caveh Jalali (Code Review) Sept. 30, 2026

Sept. 30, 2026

Attention is currently required from: Boris Mittelberg, Matt DeVillier. Caveh Jalali has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/95887?usp=email ) Change subject: ec/google/chromeec: Drop unused COM1 device from superio.asl ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/95887?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7cf4bb8be108dca9c29ec3e5a913f992c317ac1 Gerrit-Change-Number: 95887 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Sep 2026 23:50:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: ec/google/chromeec: Consolidate CREC preprocessor conditions
by Matt DeVillier (Code Review) Sept. 30, 2026

Sept. 30, 2026

Attention is currently required from: Boris Mittelberg, Caveh Jalali. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/95900?usp=email ) Change subject: ec/google/chromeec: Consolidate CREC preprocessor conditions ...................................................................... ec/google/chromeec: Consolidate CREC preprocessor conditions The CREC device used nested #ifdef blocks and defined the mainboard EC_SYNC_IRQ_WAKE_CAPABLE macro inline to select the interrupt share type. Evaluate each condition once at the top of the file into CREC_HAS_* flags, leaving the mainboard macros untouched, so the guards within the device are simple checks. TEST=Build dsdt.aml for all 339 boards in the mainboard directories using the ChromeEC ASL, both with and without CONFIG_CHROMEOS; all are byte-identical. Change-Id: Ifee260b713c2cb06ac224560899ccb2209d72596 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/google/chromeec/acpi/cros_ec.asl 1 file changed, 25 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/95900/1 diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index cb1e514..6c2d9bd 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -1,7 +1,26 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#if CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE) -#define LPC_GMR_SIZE 0x10000 +#define CREC_HAS_GMR CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE) +#define LPC_GMR_SIZE 0x10000 + +#if defined(EC_ENABLE_SYNC_IRQ) || defined(EC_ENABLE_SYNC_IRQ_GPIO) || CREC_HAS_GMR +#define CREC_HAS_CRS 1 +#else +#define CREC_HAS_CRS 0 +#endif + +/* With a GPIO sync interrupt, the interrupt itself is the wake source instead of _PRW. */ +#if defined(EC_ENABLE_WAKE_PIN) && !defined(EC_ENABLE_SYNC_IRQ_GPIO) +#define CREC_HAS_PRW 1 +#else +#define CREC_HAS_PRW 0 +#endif + +#if defined(EC_SYNC_IRQ_WAKE_CAPABLE) || \ + (defined(EC_ENABLE_SYNC_IRQ_GPIO) && defined(EC_ENABLE_WAKE_PIN)) +#define EC_SYNC_SHARE_TYPE ExclusiveAndWake +#else +#define EC_SYNC_SHARE_TYPE Exclusive #endif Device (CREC) @@ -9,22 +28,11 @@ Name (_HID, CONFIG_EC_GOOGLE_CHROMEEC_ACPI_HID) Name (_UID, 1) Name (_DDN, "EC Command Device") -#ifdef EC_ENABLE_WAKE_PIN -#ifndef EC_ENABLE_SYNC_IRQ_GPIO +#if CREC_HAS_PRW Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 }) -#else -#define EC_SYNC_IRQ_WAKE_CAPABLE -#endif #endif -#ifdef EC_SYNC_IRQ_WAKE_CAPABLE - #define EC_SYNC_SHARE_TYPE ExclusiveAndWake -#else - #define EC_SYNC_SHARE_TYPE Exclusive -#endif - -#if defined(EC_ENABLE_SYNC_IRQ) || defined(EC_ENABLE_SYNC_IRQ_GPIO) || \ -CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE) +#if CREC_HAS_CRS Method (_CRS, 0x0, NotSerialized) { Name (RBUF, ResourceTemplate() @@ -41,12 +49,12 @@ } #endif -#if CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE) +#if CREC_HAS_GMR Memory32Fixed (ReadWrite, 0, 0, MADR) #endif }) -#if CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE) +#if CREC_HAS_GMR CreateDWordField (RBUF, MADR._BAS, BAS0) CreateDWordField (RBUF, MADR._LEN, LEN0) BAS0 = \_SB.PCI0.LPCB.GLGM() -- To view, visit https://review.coreboot.org/c/coreboot/+/95900?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifee260b713c2cb06ac224560899ccb2209d72596 Gerrit-Change-Number: 95900 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org>

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[M] Change in coreboot[main]: ec/google/chromeec: Use a template for the battery devices
by Matt DeVillier (Code Review) Sept. 30, 2026

Sept. 30, 2026

Attention is currently required from: Boris Mittelberg, Caveh Jalali. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/95899?usp=email ) Change subject: ec/google/chromeec: Use a template for the battery devices ...................................................................... ec/google/chromeec: Use a template for the battery devices BAT0 and BAT1 were identical apart from the device name, _UID and EC battery index. Move the device definition into battery_device.asl and include it once per battery with those values defined as macros. TEST=build 31 boards using the ChromeEC ASL, including poppy which has the second battery; dsdt.aml is byte-identical. Change-Id: I19edb9a5f1b13f2546f6eda2e91a03a5e47dc251 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/google/chromeec/acpi/battery.asl A src/ec/google/chromeec/acpi/battery_device.asl 2 files changed, 95 insertions(+), 146 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/95899/1 diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index 5b39f62..95abd67 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -348,152 +348,14 @@ Return (Arg1) } -Device (BAT0) -{ - Name (_HID, EISAID ("PNP0C0A")) - Name (_UID, 1) - Name (_PCL, Package () { \_SB }) - - Name (PBIF, Package () { - 0x00000001, // 0x00: Power Unit: mAh - 0xFFFFFFFF, // 0x01: Design Capacity - 0xFFFFFFFF, // 0x02: Last Full Charge Capacity - 0x00000001, // 0x03: Battery Technology: Rechargeable - 0xFFFFFFFF, // 0x04: Design Voltage - 0x00000003, // 0x05: Design Capacity of Warning - 0xFFFFFFFF, // 0x06: Design Capacity of Low - 0x00000001, // 0x07: Capacity Granularity 1 - 0x00000001, // 0x08: Capacity Granularity 2 - "", // 0x09: Model Number - "", // 0x0a: Serial Number - "LION", // 0x0b: Battery Type - "" // 0x0c: OEM Information - }) - - Name (PBIX, Package () { - 0x00000000, // 0x00: Revision - 0x00000001, // 0x01: Power Unit: mAh - 0xFFFFFFFF, // 0x02: Design Capacity - 0xFFFFFFFF, // 0x03: Last Full Charge Capacity - 0x00000001, // 0x04: Battery Technology: Rechargeable - 0xFFFFFFFF, // 0x05: Design Voltage - 0x00000003, // 0x06: Design Capacity of Warning - 0xFFFFFFFF, // 0x07: Design Capacity of Low - 0x00000000, // 0x08: Cycle Count - 0x00018000, // 0x09: Measurement Accuracy (98.3%?) - 0x000001F4, // 0x0a: Max Sampling Time (500ms) - 0x0000000a, // 0x0b: Min Sampling Time (10ms) - 0xFFFFFFFF, // 0x0c: Max Averaging Interval - 0xFFFFFFFF, // 0x0d: Min Averaging Interval - 0x00000001, // 0x0e: Capacity Granularity 1 - 0x00000001, // 0x0f: Capacity Granularity 2 - "", // 0x10 Model Number - "", // 0x11: Serial Number - "LION", // 0x12: Battery Type - "" // 0x13: OEM Information - }) - - Name (PBST, Package () { - 0x00000000, // 0x00: Battery State - 0xFFFFFFFF, // 0x01: Battery Present Rate - 0xFFFFFFFF, // 0x02: Battery Remaining Capacity - 0xFFFFFFFF, // 0x03: Battery Present Voltage - }) - Name (BSTP, 0) - - Method (_STA, 0, Serialized) - { - Return (BSTA (0)) - } - - Method (_BIF, 0, Serialized) - { - Return (BBIF (0, PBIF, PBIX)) - } - - Method (_BIX, 0, Serialized) - { - Return (BBIX (0, PBIX)) - } - - Method (_BST, 0, Serialized) - { - Return (BBST (0, PBST, RefOf (BSTP))) - } -} +#define BATTERY_NAME BAT0 +#define BATTERY_INDEX 0 +#define BATTERY_UID 1 +#include "battery_device.asl" #ifdef EC_ENABLE_SECOND_BATTERY_DEVICE -Device (BAT1) -{ - Name (_HID, EISAID ("PNP0C0A")) - Name (_UID, 2) - Name (_PCL, Package () { \_SB }) - - Name (PBIF, Package () { - 0x00000001, // 0x00: Power Unit: mAh - 0xFFFFFFFF, // 0x01: Design Capacity - 0xFFFFFFFF, // 0x02: Last Full Charge Capacity - 0x00000001, // 0x03: Battery Technology: Rechargeable - 0xFFFFFFFF, // 0x04: Design Voltage - 0x00000003, // 0x05: Design Capacity of Warning - 0xFFFFFFFF, // 0x06: Design Capacity of Low - 0x00000001, // 0x07: Capacity Granularity 1 - 0x00000001, // 0x08: Capacity Granularity 2 - "", // 0x09: Model Number - "", // 0x0a: Serial Number - "LION", // 0x0b: Battery Type - "" // 0x0c: OEM Information - }) - - Name (PBIX, Package () { - 0x00000000, // 0x00: Revision - 0x00000001, // 0x01: Power Unit: mAh - 0xFFFFFFFF, // 0x02: Design Capacity - 0xFFFFFFFF, // 0x03: Last Full Charge Capacity - 0x00000001, // 0x04: Battery Technology: Rechargeable - 0xFFFFFFFF, // 0x05: Design Voltage - 0x00000003, // 0x06: Design Capacity of Warning - 0xFFFFFFFF, // 0x07: Design Capacity of Low - 0x00000000, // 0x08: Cycle Count - 0x00018000, // 0x09: Measurement Accuracy (98.3%?) - 0x000001F4, // 0x0a: Max Sampling Time (500ms) - 0x0000000a, // 0x0b: Min Sampling Time (10ms) - 0xFFFFFFFF, // 0x0c: Max Averaging Interval - 0xFFFFFFFF, // 0x0d: Min Averaging Interval - 0x00000001, // 0x0e: Capacity Granularity 1 - 0x00000001, // 0x0f: Capacity Granularity 2 - "", // 0x10 Model Number - "", // 0x11: Serial Number - "LION", // 0x12: Battery Type - "" // 0x13: OEM Information - }) - - Name (PBST, Package () { - 0x00000000, // 0x00: Battery State - 0xFFFFFFFF, // 0x01: Battery Present Rate - 0xFFFFFFFF, // 0x02: Battery Remaining Capacity - 0xFFFFFFFF, // 0x03: Battery Present Voltage - }) - Name (BSTP, 0) - - Method (_STA, 0, Serialized) - { - Return (BSTA (1)) - } - - Method (_BIF, 0, Serialized) - { - Return (BBIF (1, PBIF, PBIX)) - } - - Method (_BIX, 0, Serialized) - { - Return (BBIX (1, PBIX)) - } - - Method (_BST, 0, Serialized) - { - Return (BBST (1, PBST, RefOf (BSTP))) - } -} +#define BATTERY_NAME BAT1 +#define BATTERY_INDEX 1 +#define BATTERY_UID 2 +#include "battery_device.asl" #endif diff --git a/src/ec/google/chromeec/acpi/battery_device.asl b/src/ec/google/chromeec/acpi/battery_device.asl new file mode 100644 index 0000000..4618ac9 --- /dev/null +++ b/src/ec/google/chromeec/acpi/battery_device.asl @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Battery device template, included from battery.asl once per battery. + * The includer must define: + * BATTERY_NAME = ACPI device name + * BATTERY_INDEX = EC battery index + * BATTERY_UID = ACPI _UID + */ + +Device (BATTERY_NAME) +{ + Name (_HID, EISAID ("PNP0C0A")) + Name (_UID, BATTERY_UID) + Name (_PCL, Package () { \_SB }) + + Name (PBIF, Package () { + 0x00000001, // 0x00: Power Unit: mAh + 0xFFFFFFFF, // 0x01: Design Capacity + 0xFFFFFFFF, // 0x02: Last Full Charge Capacity + 0x00000001, // 0x03: Battery Technology: Rechargeable + 0xFFFFFFFF, // 0x04: Design Voltage + 0x00000003, // 0x05: Design Capacity of Warning + 0xFFFFFFFF, // 0x06: Design Capacity of Low + 0x00000001, // 0x07: Capacity Granularity 1 + 0x00000001, // 0x08: Capacity Granularity 2 + "", // 0x09: Model Number + "", // 0x0a: Serial Number + "LION", // 0x0b: Battery Type + "" // 0x0c: OEM Information + }) + + Name (PBIX, Package () { + 0x00000000, // 0x00: Revision + 0x00000001, // 0x01: Power Unit: mAh + 0xFFFFFFFF, // 0x02: Design Capacity + 0xFFFFFFFF, // 0x03: Last Full Charge Capacity + 0x00000001, // 0x04: Battery Technology: Rechargeable + 0xFFFFFFFF, // 0x05: Design Voltage + 0x00000003, // 0x06: Design Capacity of Warning + 0xFFFFFFFF, // 0x07: Design Capacity of Low + 0x00000000, // 0x08: Cycle Count + 0x00018000, // 0x09: Measurement Accuracy (98.3%?) + 0x000001F4, // 0x0a: Max Sampling Time (500ms) + 0x0000000a, // 0x0b: Min Sampling Time (10ms) + 0xFFFFFFFF, // 0x0c: Max Averaging Interval + 0xFFFFFFFF, // 0x0d: Min Averaging Interval + 0x00000001, // 0x0e: Capacity Granularity 1 + 0x00000001, // 0x0f: Capacity Granularity 2 + "", // 0x10 Model Number + "", // 0x11: Serial Number + "LION", // 0x12: Battery Type + "" // 0x13: OEM Information + }) + + Name (PBST, Package () { + 0x00000000, // 0x00: Battery State + 0xFFFFFFFF, // 0x01: Battery Present Rate + 0xFFFFFFFF, // 0x02: Battery Remaining Capacity + 0xFFFFFFFF, // 0x03: Battery Present Voltage + }) + Name (BSTP, 0) + + Method (_STA, 0, Serialized) + { + Return (BSTA (BATTERY_INDEX)) + } + + Method (_BIF, 0, Serialized) + { + Return (BBIF (BATTERY_INDEX, PBIF, PBIX)) + } + + Method (_BIX, 0, Serialized) + { + Return (BBIX (BATTERY_INDEX, PBIX)) + } + + Method (_BST, 0, Serialized) + { + Return (BBST (BATTERY_INDEX, PBST, RefOf (BSTP))) + } +} + +#undef BATTERY_NAME +#undef BATTERY_INDEX +#undef BATTERY_UID -- To view, visit https://review.coreboot.org/c/coreboot/+/95899?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19edb9a5f1b13f2546f6eda2e91a03a5e47dc251 Gerrit-Change-Number: 95899 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org>

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[M] Change in coreboot[main]: ec/google/chromeec: Derive _BIF data from _BIX
by Matt DeVillier (Code Review) Sept. 30, 2026

Sept. 30, 2026

Attention is currently required from: Boris Mittelberg, Caveh Jalali. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/95898?usp=email ) Change subject: ec/google/chromeec: Derive _BIF data from _BIX ...................................................................... ec/google/chromeec: Derive _BIF data from _BIX BBIF and BBIX read the same fields from the EC and differ only in where they place them in the returned package, with _BIX also reporting the cycle count. Implement BBIF by calling BBIX and copying the relevant elements, so the EC access logic exists only once. TEST=build 31 boards using the ChromeEC ASL. With acpiexec and EC fields seeded with non-zero capacity, voltage and battery strings, _BIF and _BIX on yaviks and poppy return identical packages before and after this change. Change-Id: I353aab123b27af61e7264a174be821f5030daa7d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/google/chromeec/acpi/battery.asl 1 file changed, 22 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/95898/1 diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index aef8d8f..5b39f62 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -193,46 +193,6 @@ Return (Local0) } -// _BIF implementation. -// Arg0 = battery index -// Arg1 = PBIF -Method (BBIF, 2, Serialized) -{ - If (Acquire (^BATM, 1000)) { - Return (Arg1) - } - - If (BTSW (Arg0)) { - Release (^BATM) - Return (Arg1) - } - // Last Full Charge Capacity - Arg1[2] = BTDF - - // Design Voltage - Arg1[4] = BTDV - - // Design Capacity - Local0 = BTDA - Arg1[1] = Local0 - - // Design Capacity of Warning - Local2 = Local0 * DWRN / 100 - Arg1[5] = Local2 - - // Design Capacity of Low - Local2 = Local0 * DLOW / 100 - Arg1[6] = Local2 - - // Get battery info from mainboard - Arg1[9] = BRSX (1) - Arg1[10] = BRSX (2) - Arg1[12] = BRSX (3) - - Release (^BATM) - Return (Arg1) -} - // _BIX implementation. // Arg0 = battery index // Arg1 = PBIX @@ -276,6 +236,26 @@ Return (Arg1) } +// _BIF implementation, derived from the _BIX data. +// Arg0 = battery index +// Arg1 = PBIF +// Arg2 = PBIX +Method (BBIF, 3, Serialized) +{ + Local0 = BBIX (Arg0, Arg2) + + Arg1[1] = DeRefOf (Local0[2]) // Design Capacity + Arg1[2] = DeRefOf (Local0[3]) // Last Full Charge Capacity + Arg1[4] = DeRefOf (Local0[5]) // Design Voltage + Arg1[5] = DeRefOf (Local0[6]) // Design Capacity of Warning + Arg1[6] = DeRefOf (Local0[7]) // Design Capacity of Low + Arg1[9] = DeRefOf (Local0[16]) // Model Number + Arg1[10] = DeRefOf (Local0[17]) // Serial Number + Arg1[12] = DeRefOf (Local0[19]) // OEM Information + + Return (Arg1) +} + // _BST implementation. // Arg0 = battery index // Arg1 = PBST @@ -428,7 +408,7 @@ Method (_BIF, 0, Serialized) { - Return (BBIF (0, PBIF)) + Return (BBIF (0, PBIF, PBIX)) } Method (_BIX, 0, Serialized) @@ -503,7 +483,7 @@ Method (_BIF, 0, Serialized) { - Return (BBIF (1, PBIF)) + Return (BBIF (1, PBIF, PBIX)) } Method (_BIX, 0, Serialized) -- To view, visit https://review.coreboot.org/c/coreboot/+/95898?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I353aab123b27af61e7264a174be821f5030daa7d Gerrit-Change-Number: 95898 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org>

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[XS] Change in coreboot[main]: ec/google/chromeec: Fix stale comment on TCHG external
by Matt DeVillier (Code Review) Sept. 30, 2026

Sept. 30, 2026

Attention is currently required from: Boris Mittelberg, Caveh Jalali. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/95897?usp=email ) Change subject: ec/google/chromeec: Fix stale comment on TCHG external ...................................................................... ec/google/chromeec: Fix stale comment on TCHG external The comment dates from when this spot declared the mainboard throttle handler (\_TZ.THRT). It now precedes the DPTF charger participant external, so update it accordingly. TEST=build 31 boards using the ChromeEC ASL; dsdt.aml is byte-identical. Change-Id: Ibd268c4308a0a29e9ae1039937322a31b1cd73f9 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/95897/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 2cbee21..9bd0e85 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -17,7 +17,7 @@ #define ACPI_NOTIFY_CROS_EC_S0IX_ENTER 0x01 #define ACPI_NOTIFY_CROS_EC_S0IX_EXIT 0x02 -// Mainboard specific throttle handler +// DPTF charger participant device #ifdef DPTF_ENABLE_CHARGER External (\_SB.DPTF.TCHG, DeviceObj) #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/95897?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd268c4308a0a29e9ae1039937322a31b1cd73f9 Gerrit-Change-Number: 95897 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org>

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[XS] Change in coreboot[main]: ec/google/chromeec: Use logical operators in BSTA
by Matt DeVillier (Code Review) Sept. 30, 2026

Sept. 30, 2026

Attention is currently required from: Boris Mittelberg, Caveh Jalali. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/95896?usp=email ) Change subject: ec/google/chromeec: Use logical operators in BSTA ...................................................................... ec/google/chromeec: Use logical operators in BSTA BSTA combined the result of BTSW and the BTEX flag using bitwise NOT and AND. This only works because BTSW returns 0 or 1 and BTEX is a single bit. Use logical operators to express the intent directly. TEST=build 31 boards using the ChromeEC ASL; the only DSDT change is the BSTA condition (mini PCs, where BSTA returns 0, are unchanged). Change-Id: I82074624289d299c5fd18d0892c9b6b1549bb950 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/google/chromeec/acpi/battery.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/95896/1 diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index 9c675c9..aef8d8f 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -47,7 +47,7 @@ Return (0) } - If (~BTSW (Arg0) & BTEX) { + If (!BTSW (Arg0) && BTEX) { Local0 = 0x1F } Else { Local0 = 0x0F -- To view, visit https://review.coreboot.org/c/coreboot/+/95896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I82074624289d299c5fd18d0892c9b6b1549bb950 Gerrit-Change-Number: 95896 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org>

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