June 2026 - coreboot-gerrit - mail.coreboot.org

Change in ...coreboot[master]: mb/apple: Add MacBook Pro 10,1 (A1398) support
by Evgeny Zinoviev (Code Review) July 17, 2026

July 17, 2026

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32673 Change subject: mb/apple: Add MacBook Pro 10,1 (A1398) support ...................................................................... mb/apple: Add MacBook Pro 10,1 (A1398) support MacBook Pro Retina 15 (Mid 2012) with Ivy Bridge CPU. This is WIP. Not for merging. Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M 3rdparty/vboot A src/mainboard/apple/macbookpro10_1/Kconfig A src/mainboard/apple/macbookpro10_1/Kconfig.name A src/mainboard/apple/macbookpro10_1/Makefile.inc A src/mainboard/apple/macbookpro10_1/acpi/ec.asl A src/mainboard/apple/macbookpro10_1/acpi/platform.asl A src/mainboard/apple/macbookpro10_1/acpi/superio.asl A src/mainboard/apple/macbookpro10_1/acpi_tables.c A src/mainboard/apple/macbookpro10_1/board_info.txt A src/mainboard/apple/macbookpro10_1/devicetree.cb A src/mainboard/apple/macbookpro10_1/dsdt.asl A src/mainboard/apple/macbookpro10_1/gma-mainboard.ads A src/mainboard/apple/macbookpro10_1/gpio.c A src/mainboard/apple/macbookpro10_1/hda_verb.c A src/mainboard/apple/macbookpro10_1/mainboard.c A src/mainboard/apple/macbookpro10_1/romstage.c 16 files changed, 758 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32673/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index e7edff6..304aa42 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit e7edff6653e16ed915c3ad12234d133d1ef4dcc9 +Subproject commit 304aa429c1a04cda3ab2ce37b9e31af84405bfca diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig b/src/mainboard/apple/macbookpro10_1/Kconfig new file mode 100644 index 0000000..603f3ee --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig @@ -0,0 +1,46 @@ +if BOARD_APPLE_MACBOOKPRO10_1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_EDP + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default apple/macbookpro10_1 + +config MAINBOARD_PART_NUMBER + string + default "MacBookPro10,1" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config DRAM_RESET_GATE_GPIO + int + default 28 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig.name b/src/mainboard/apple/macbookpro10_1/Kconfig.name new file mode 100644 index 0000000..c257f7a --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACBOOKPRO10_1 + bool "MacBookPro10,1" diff --git a/src/mainboard/apple/macbookpro10_1/Makefile.inc b/src/mainboard/apple/macbookpro10_1/Makefile.inc new file mode 100644 index 0000000..fd60338 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Makefile.inc @@ -0,0 +1,7 @@ +romstage-y += gpio.c + +cbfs-files-y += spd.bin +spd.bin-file := spd.bin +spd.bin-type := spd + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/apple/macbookpro10_1/acpi/ec.asl b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl new file mode 100644 index 0000000..f70cb3d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/platform.asl b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl new file mode 100644 index 0000000..a17c6ea --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/superio.asl b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl diff --git a/src/mainboard/apple/macbookpro10_1/acpi_tables.c b/src/mainboard/apple/macbookpro10_1/acpi_tables.c new file mode 100644 index 0000000..c48f0bd --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi_tables.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookpro10_1/board_info.txt b/src/mainboard/apple/macbookpro10_1/board_info.txt new file mode 100644 index 0000000..81a5134 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +ROM package: SOIC-8 +ROM socketed: n +Release year: 2012 diff --git a/src/mainboard/apple/macbookpro10_1/devicetree.cb b/src/mainboard/apple/macbookpro10_1/devicetree.cb new file mode 100644 index 0000000..f9e7eb4 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/devicetree.cb @@ -0,0 +1,124 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + #register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0xffffffff" + register "gpu_dp_b_hotplug" = "7" + register "gpu_dp_c_hotplug" = "7" + register "gpu_dp_d_hotplug" = "7" + register "gpu_panel_port_select" = "3" + register "gpu_panel_power_backlight_off_delay" = "8191" + register "gpu_panel_power_backlight_on_delay" = "8191" + register "gpu_panel_power_cycle_delay" = "255" + register "gpu_panel_power_down_delay" = "8191" + register "gpu_panel_power_up_delay" = "8191" + register "gpu_pch_backlight" = "0xffffffff" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x08040201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x8086 0x7270 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x7270 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x8086 0x7270 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x8086 0x7270 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x7270 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x8086 0x7270 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x8086 0x7270 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x8086 0x7270 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x7270 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x7270 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x106b 0x00f7 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x106b 0x00f7 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x106b 0x00f7 + end + device pci 01.2 on + subsystemid 0x106b 0x00f7 + end + device pci 01.1 on + subsystemid 0x106b 0x00f7 + end + end +end diff --git a/src/mainboard/apple/macbookpro10_1/dsdt.asl b/src/mainboard/apple/macbookpro10_1/dsdt.asl new file mode 100644 index 0000000..455ac17 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads new file mode 100644 index 0000000..d4a5d7d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/apple/macbookpro10_1/gpio.c b/src/mainboard/apple/macbookpro10_1/gpio.c new file mode 100644 index 0000000..a445687 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gpio.c @@ -0,0 +1,243 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio11 = GPIO_RESET_RSMRST, + .gpio15 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macbookpro10_1/hda_verb.c b/src/mainboard/apple/macbookpro10_1/hda_verb.c new file mode 100644 index 0000000..b8e4855 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/hda_verb.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b2800, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x106b2800), + + /* NID 0x09. */ + AZALIA_PIN_CFG(0x0, 0x09, 0x002b4020), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x90100112), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x90100110), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x400000f0), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x90a60100), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x004be030), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macbookpro10_1/mainboard.c b/src/mainboard/apple/macbookpro10_1/mainboard.c new file mode 100644 index 0000000..3910541 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/mainboard.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> + +static void mainboard_init(struct device *dev) +{ + +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/apple/macbookpro10_1/romstage.c b/src/mainboard/apple/macbookpro10_1/romstage.c new file mode 100644 index 0000000..c35604b --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/romstage.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <cbfs.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCH_LPC_DEV, 0x82, 0x3f0f); + pci_write_config32(PCH_LPC_DEV, 0x84, 0x000c0681); + pci_write_config32(PCH_LPC_DEV, 0x88, 0x000c1641); + pci_write_config32(PCH_LPC_DEV, 0x8c, 0x001c0301); + pci_write_config32(PCH_LPC_DEV, 0x90, 0x00fc0701); + pci_write_config16(PCH_LPC_DEV, 0x80, 0x0070); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +// FIXME +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + void *spd_file; + size_t spd_file_len = 0; + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (spd_file && spd_file_len >= 128) { + memcpy(&spd[0], spd_file, 128); + memcpy(&spd[2], spd_file, 128); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df Gerrit-Change-Number: 32673 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

11 76

[S] Change in coreboot[main]: soc/amd/strix_halo: adjust data_fabric.h
by David Milosevic (Code Review) July 1, 2026

July 1, 2026

David Milosevic has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/93824?usp=email ) Change subject: soc/amd/strix_halo: adjust data_fabric.h ...................................................................... soc/amd/strix_halo: adjust data_fabric.h This patch verifies and updates registers and constants in data_fabric.h. The source for this information is AMD's internal Strix Halo PPR. Change-Id: I5a9494d90234ca420da9760879b5fd11373c2da5 Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- M src/soc/amd/strix_halo/include/soc/data_fabric.h 1 file changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/93824/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/93824?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a9494d90234ca420da9760879b5fd11373c2da5 Gerrit-Change-Number: 93824 Gerrit-PatchSet: 2 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com>

1 0

[S] Change in coreboot[main]: soc/amd/strix_halo: adjust data_fabric.h
by David Milosevic (Code Review) July 1, 2026

July 1, 2026

David Milosevic has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/93824?usp=email ) Change subject: soc/amd/strix_halo: adjust data_fabric.h ...................................................................... soc/amd/strix_halo: adjust data_fabric.h This patch verifies and updates registers and constants in data_fabric.h. The source for this information is AMD's internal Strix Halo PPR. Change-Id: I5a9494d90234ca420da9760879b5fd11373c2da5 Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- M src/soc/amd/strix_halo/include/soc/data_fabric.h 1 file changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/93824/1 diff --git a/src/soc/amd/strix_halo/include/soc/data_fabric.h b/src/soc/amd/strix_halo/include/soc/data_fabric.h index f2125e4..1435281 100644 --- a/src/soc/amd/strix_halo/include/soc/data_fabric.h +++ b/src/soc/amd/strix_halo/include/soc/data_fabric.h @@ -1,14 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Strix Halo */ - #ifndef AMD_STRIX_HALO_DATA_FABRIC_H #define AMD_STRIX_HALO_DATA_FABRIC_H #include <amdblocks/data_fabric_defs.h> #include <types.h> -#define IOMS0_FABRIC_ID 0x14 +#define IOMS0_FABRIC_ID 0x21 #define DF_PCI_CFG_BASE0 DF_REG_ID(0, 0xc80) #define DF_PCI_CFG_LIMIT0 DF_REG_ID(0, 0xc84) @@ -19,6 +17,7 @@ #define DF_PCI_CFG_BASE(reg) (DF_PCI_CFG_BASE0 + DF_PCI_CFG_REG_OFFSET(reg)) #define DF_PCI_CFG_LIMIT(reg) (DF_PCI_CFG_LIMIT0 + DF_PCI_CFG_REG_OFFSET(reg)) +// DF::CfgBaseAddress union df_pci_cfg_base { struct { uint32_t re : 1; /* [ 0.. 0] */ @@ -31,6 +30,7 @@ uint32_t raw; }; +// DF::CfgLimitAddress union df_pci_cfg_limit { struct { uint32_t dst_fabric_id : 6; /* [ 0.. 5] */ @@ -50,6 +50,7 @@ #define DF_IO_BASE(reg) (DF_IO_BASE0 + DF_IO_REG_OFFSET(reg)) #define DF_IO_LIMIT(reg) (DF_IO_LIMIT0 + DF_IO_REG_OFFSET(reg)) +// DF::X86IOBaseAddress union df_io_base { struct { uint32_t re : 1; /* [ 0.. 0] */ @@ -63,6 +64,7 @@ uint32_t raw; }; +// DF::X86IOLimitAddress union df_io_limit { struct { uint32_t dst_fabric_id : 6; /* [ 0.. 5] */ @@ -77,12 +79,13 @@ #define DF_MMIO_BASE0 DF_REG_ID(0, 0xD80) #define DF_MMIO_LIMIT0 DF_REG_ID(0, 0xD84) -#define DF_MMIO_SHIFT 16 +#define DF_MMIO_SHIFT 16 #define DF_MMIO_CTRL0 DF_REG_ID(0, 0xD88) #define DF_MMIO_REG_SET_SIZE 4 #define DF_MMIO_REG_SET_COUNT 8 +// DF::MmioAddressControl union df_mmio_control { struct { uint32_t re : 1; /* [ 0.. 0] */ @@ -100,6 +103,7 @@ #define DF_FICAD_LO DF_REG_ID(4, 0xB8) #define DF_FICAD_HI DF_REG_ID(4, 0xBC) +// DF::FabricIndirectConfigAccessAddress union df_ficaa { struct { uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ -- To view, visit https://review.coreboot.org/c/coreboot/+/93824?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a9494d90234ca420da9760879b5fd11373c2da5 Gerrit-Change-Number: 93824 Gerrit-PatchSet: 1 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com>

1 0

[XS] Change in coreboot[main]: lib/fmap: Validate area offset/size in fmap_locate_area()
by Matt DeVillier (Code Review) July 1, 2026

July 1, 2026

Attention is currently required from: Julius Werner, Martin L Roth. Matt DeVillier has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/93818?usp=email ) Change subject: lib/fmap: Validate area offset/size in fmap_locate_area() ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/93818?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1673fc6f2f597b7022a9f8b0b23329a3ed5514f1 Gerrit-Change-Number: 93818 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 30 Jun 2026 22:38:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: lib/fmap: Validate area offset/size in fmap_locate_area()
by Martin L Roth (Code Review) July 1, 2026

July 1, 2026

Attention is currently required from: Julius Werner, Matt DeVillier. Martin L Roth has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/93818?usp=email ) Change subject: lib/fmap: Validate area offset/size in fmap_locate_area() ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/93818/comment/e6913d24_4c6c1472?us… : PS1, Line 10: tainted > According to the definitions I'm familiar with, it is always tainted: […] Changing to "unverified" -- To view, visit https://review.coreboot.org/c/coreboot/+/93818?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1673fc6f2f597b7022a9f8b0b23329a3ed5514f1 Gerrit-Change-Number: 93818 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 30 Jun 2026 22:37:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

[XS] Change in coreboot[main]: lib/fmap: Validate area offset/size in fmap_locate_area()
by Martin L Roth (Code Review) July 1, 2026

July 1, 2026

Attention is currently required from: Julius Werner, Matt DeVillier. Hello Julius Werner, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/93818?usp=email to look at the new patch set (#2). Change subject: lib/fmap: Validate area offset/size in fmap_locate_area() ...................................................................... lib/fmap: Validate area offset/size in fmap_locate_area() fmap_locate_area() builds the returned region with region_create(), passing in the offset and size taken straight from the unverified FMAP stored on flash. region_create() only sanity-checks those values with assert(), which does nothing more than logs an error if CONFIG_FATAL_ASSERTS is disabled, the default for release firmware. The overflowing region is returned and fmap_locate_area() reports success, handing the caller a region whose offset + size wraps around. That malformed region can later drive out-of-bounds reads or mmaps. To address this, we use region_create_untrusted() instead. It performs the same overflow check with runtime logic that is always compiled in, which leaves the output region untouched on bad input, and returns an error. We then propagate that error to the caller so a bad FMAP entry is rejected rather than silently accepted. Change-Id: I1673fc6f2f597b7022a9f8b0b23329a3ed5514f1 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M src/lib/fmap.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/93818/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/93818?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1673fc6f2f597b7022a9f8b0b23329a3ed5514f1 Gerrit-Change-Number: 93818 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org>

1 0

[XS] Change in coreboot[main]: lib/fmap: Validate area offset/size in fmap_locate_area()
by Martin L Roth (Code Review) July 1, 2026

July 1, 2026

Attention is currently required from: Julius Werner, Matt DeVillier. Martin L Roth has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/93818?usp=email ) Change subject: lib/fmap: Validate area offset/size in fmap_locate_area() ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/93818/comment/572857cc_3a2a6a3a?us… : PS1, Line 10: tainted > feel like this implies that the values are always tainted. […] According to the definitions I'm familiar with, it is always tainted: ``` What is Tainted Data? Any unchecked and un-sanitized input into a device is considered tainted. ``` https://www.grammatech.com/learn/dont-trust-any-input-prevent-vulnerabiliti… -- To view, visit https://review.coreboot.org/c/coreboot/+/93818?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1673fc6f2f597b7022a9f8b0b23329a3ed5514f1 Gerrit-Change-Number: 93818 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 30 Jun 2026 22:34:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

[M] Change in coreboot[main]: device/azalia_device: Use weak functions to get azalia codecs
by Matt DeVillier (Code Review) June 30, 2026

June 30, 2026

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/89421?usp=email ) Change subject: device/azalia_device: Use weak functions to get azalia codecs ...................................................................... device/azalia_device: Use weak functions to get azalia codecs The reworked verb table was designed to use a terminator (empty structure) to mark the end of the codec table. However, this was found to be slightly error-prone as there are no checks from the compiler on whether the terminator is actually present. Therefore, we chose to use a weak function which returns the codec table and its length. This has the following benefits: 1. Less error-prone as the function requires you to return something. 2. Many boards enable HDA support (indirectly through the SoC configuration) but do not provide any verbs. This can cause linkage errors when compiling with Address Sanitizer enabled. Using weak functions fixes one aspect of this (pc_beep_verbs still remains), as unlike 'extern' the definition is provided. 3. No code is needed on the mainboard side if there are no codecs present, as the weak function's default behavior is to return 0 (i.e. no codecs present). This change introduces the following 2 weak functions: - azalia_get_mainboard_codecs() - azalia_get_platform_codecs() The former is used for the regular mainboard codecs, the latter is used for platform specific codecs (e.g. display audio codecs found in Intel iGPUs). Most mainboards provide these platform codecs as well, causing a lot of duplicated code. We hope to move those into platform specific code in the future and this change should lay the groundwork for that. To keep this change as small as possible, the azalia_get_mainboard_codecs() is placed inside the AZALIA_ARRAY_SIZES macro which will ensure that it is implicitly added to all the mainboard code that uses the new verb table format. The function can be properly placed into the mainboard code in a following change and also be verified with a timeless build. Leaving the terminator in the codec table should also be of no practical concern as azalia_program_verb_table() would do nothing as the verb table is NULL (though realistically it would not even get to this point, as I doubt there is a codec that uses the vendor ID: 0x00000000). This can also be removed in a following change with a simple find(1) and sed(1) command. TEST= Both verbs from azalia_get_mainboard_codecs() and azalia_get_platform_codecs() are loaded on HP ProBook 450 G3. Change-Id: I3accc8dbd7bf211f502c365b8c55219fbf42e0b3 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89421 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/azalia_device.c M src/include/device/azalia_device.h 2 files changed, 41 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index d130c5b..d2ca1d3 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -260,11 +260,37 @@ azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size); } #else -static struct azalia_codec *find_codec(struct azalia_codec *codecs, u32 vid, u8 addr) +__weak size_t azalia_get_mainboard_codecs(struct azalia_codec **codecs) { - for (struct azalia_codec *codec = codecs; codec->vendor_id; codec++) { - if (codec->vendor_id == vid && codec->address == addr) - return codec; + return 0; +} + +__weak size_t azalia_get_platform_codecs(struct azalia_codec **codecs) +{ + return 0; +} + +static struct azalia_codec *find_codec(u32 vid, u8 addr) +{ + /* + * The mainboard codecs should come first, as earlier entries in the + * array have "higher priority". This allows the mainboard to override + * any platform defined codecs. + */ + static size_t (*const codec_tables[])(struct azalia_codec **) = { + azalia_get_mainboard_codecs, + azalia_get_platform_codecs, + }; + + for (size_t i = 0; i < ARRAY_SIZE(codec_tables); i++) { + struct azalia_codec *codec; + size_t count = codec_tables[i](&codec); + + for (size_t k = 0; k < count; k++) { + if (codec->vendor_id == vid && codec->address == addr) + return codec; + codec++; + } } return NULL; } @@ -289,7 +315,7 @@ printk(BIOS_DEBUG, "azalia_audio: done\n"); } -void azalia_custom_codecs_init(u8 *base, struct azalia_codec *codecs, u16 codec_mask) +void azalia_codecs_init(u8 *base, u16 codec_mask) { for (u8 i = 0; i < AZALIA_MAX_CODECS; i++) { if (!(codec_mask & BIT(i))) @@ -299,7 +325,7 @@ continue; u32 vid = read32(base + HDA_IR_REG); - struct azalia_codec *codec = find_codec(codecs, vid, i); + struct azalia_codec *codec = find_codec(vid, i); if (codec == NULL) { printk(BIOS_WARNING, "azalia_audio: cannot find verbs for codec with vendor ID: 0x%08x (address %u)\n", @@ -312,11 +338,6 @@ azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size); } - -void azalia_codecs_init(u8 *base, u16 codec_mask) -{ - azalia_custom_codecs_init(base, mainboard_azalia_codecs, codec_mask); -} #endif void azalia_audio_init(struct device *dev) diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 66126d2..8f64740 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -41,8 +41,9 @@ #if CONFIG(AZALIA_USE_LEGACY_VERB_TABLE) void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes); #else +size_t azalia_get_mainboard_codecs(struct azalia_codec **codecs); +size_t azalia_get_platform_codecs(struct azalia_codec **codecs); void azalia_codec_init(u8 *base, struct azalia_codec *codec); -void azalia_custom_codecs_init(u8 *base, struct azalia_codec *codecs, u16 codec_mask); #endif void azalia_codecs_init(u8 *base, u16 codec_mask); void azalia_audio_init(struct device *dev); @@ -54,8 +55,6 @@ #if CONFIG(AZALIA_USE_LEGACY_VERB_TABLE) extern const u32 cim_verb_data[]; extern const u32 cim_verb_data_size; -#else -extern struct azalia_codec mainboard_azalia_codecs[]; #endif extern const u32 pc_beep_verbs[]; extern const u32 pc_beep_verbs_size; @@ -189,8 +188,13 @@ ARRAY_SIZE(pc_beep_verbs); \ const u32 cim_verb_data_size = sizeof(cim_verb_data) #else -#define AZALIA_ARRAY_SIZES const u32 pc_beep_verbs_size = \ - ARRAY_SIZE(pc_beep_verbs) +#define AZALIA_ARRAY_SIZES \ + size_t azalia_get_mainboard_codecs(struct azalia_codec **codecs) \ + { \ + *codecs = mainboard_azalia_codecs; \ + return ARRAY_SIZE(mainboard_azalia_codecs); \ + } \ + const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs) #endif #define AZALIA_VERB_12B(codec, pin, verb, val) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/89421?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3accc8dbd7bf211f502c365b8c55219fbf42e0b3 Gerrit-Change-Number: 89421 Gerrit-PatchSet: 16 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Julia Kittlinger <julia.kittlinger(a)pm.me> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/bluey/mica: Enable preboot diagnostic
by Matt DeVillier (Code Review) June 30, 2026

June 30, 2026

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/93686?usp=email ) Change subject: mb/google/bluey/mica: Enable preboot diagnostic ...................................................................... mb/google/bluey/mica: Enable preboot diagnostic The SoC attempts to read EDID/DPCD information from the display and performs Link Training. If either operation fails, the AP sends the EC host command to trigger the display failure diagnostic LED pattern. 1. Add macro control to enable the mica preboot diagnostic function. 2. Add function logic for preboot diagnostics. BUG=b:500992986 TEST=emerge-bluey coreboot Verified on the mica device: when no screen is connected, commands can be sent to the EC, and the EC can receive them successfully. Change-Id: I05eb09d6a8fa1db77fbcf0051c061009980171d3 Signed-off-by: KangMin Wang <kangmin.wang(a)luxshare.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/93686 Reviewed-by: Derek Huang <derekhuang(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/bluey/Kconfig M src/mainboard/google/bluey/display.c 2 files changed, 28 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Derek Huang: Looks good to me, approved diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig index afd1f57..274a9cb 100644 --- a/src/mainboard/google/bluey/Kconfig +++ b/src/mainboard/google/bluey/Kconfig @@ -88,6 +88,7 @@ select MAINBOARD_HAS_CHROME_EC select MAINBOARD_HAS_FINGERPRINT_VIA_USB select MAINBOARD_HAS_GOOGLE_TPM + select MAINBOARD_LCD_FAIL_DETECT select SPI_FREQ_75MHZ config BOARD_GOOGLE_MICA @@ -136,6 +137,23 @@ help Enable this option if your mainboard is equipped with a PS8820 retimer. +config MAINBOARD_LCD_FAIL_DETECT + bool "Enable LCD failure detection via LED" + default n + help + Execute a hardware status check on the LCD panel during the preboot + phase. The SoC attempts to read EDID/DPCD information from the display + and performs Link Training. If either operation fails, the SoC sends + a diagnostic command to the EC via SPI to signal the failure state. + +config MAINBOARD_LIGHTBAR_CMD_SEQ_DIAG_LCD + depends on MAINBOARD_LCD_FAIL_DETECT + int + default 101 if BOARD_GOOGLE_MODEL_MICA + default 0 + help + The lightbar command sequence for triggering LCD diagnosis lightbar pattern. + config MAINBOARD_NO_USB_A_PORT bool default n diff --git a/src/mainboard/google/bluey/display.c b/src/mainboard/google/bluey/display.c index 287f252..061b85c 100644 --- a/src/mainboard/google/bluey/display.c +++ b/src/mainboard/google/bluey/display.c @@ -18,6 +18,7 @@ #include <soc/rpmh_config.h> #include <timer.h> #include <timestamp.h> +#include <ec/google/chromeec/ec.h> #include "board.h" #include "display.h" @@ -70,8 +71,16 @@ static void qcom_mdss_edp_init(struct edid *edid, uintptr_t fb_addr) { - if (edp_ctrl_init(edid) != CB_SUCCESS) + if (edp_ctrl_init(edid) != CB_SUCCESS) { + if (CONFIG(MAINBOARD_LCD_FAIL_DETECT)) { + if (google_chromeec_lightbar_sequence( + CONFIG_MAINBOARD_LIGHTBAR_CMD_SEQ_DIAG_LCD)) + printk(BIOS_ERR, + "Failed to send LED/lightbar(0x%x) command to EC.\n", + CONFIG_MAINBOARD_LIGHTBAR_CMD_SEQ_DIAG_LCD); + } return; + } configure_vbif_qos(); mdss_layer_mixer_setup(edid); -- To view, visit https://review.coreboot.org/c/coreboot/+/93686?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05eb09d6a8fa1db77fbcf0051c061009980171d3 Gerrit-Change-Number: 93686 Gerrit-PatchSet: 12 Gerrit-Owner: KangMin Wang <kangmin.wang(a)luxshare.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/bluey: Configure QCOM dload mode to minidump
by Subrata Banik (Code Review) June 30, 2026

June 30, 2026

Attention is currently required from: Kapil Porwal. Subrata Banik has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/93820?usp=email ) Change subject: mb/google/bluey: Configure QCOM dload mode to minidump ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/bluey/romstage.c: https://review.coreboot.org/c/coreboot/+/93820/comment/6d1255c8_3b45b23a?us… : PS2, Line 310: if (CONFIG(QC_RAMDUMP_ENABLE)) { ``` if (!CONFIG(QC_RAMDUMP_ENABLE)) return; printk(BIOS_DEBUG, "Setting ramdump mode to minidump\n"); write32p(TCSR_BOOT_MISC_DETECT, DLOAD_MINI_DUMP); write32p(_shared_imem + IMEM_STORAGE_SELECT_OFFSET, DLOAD_STORAGE); ``` https://review.coreboot.org/c/coreboot/+/93820/comment/211e2804_f6d67df4?us… : PS2, Line 365: qcom_set_dload_mode(); should we set this inside `platform_romstage_postram` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/93820?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c332008587fb9a0e56840ecad85f8428fb44d97 Gerrit-Change-Number: 93820 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 30 Jun 2026 19:23:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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