February 2026 - coreboot-gerrit

Change in ...coreboot[master]: mb/apple: Add MacBook Pro 10,1 (A1398) support
by Evgeny Zinoviev (Code Review) July 17, 2026

July 17, 2026

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32673 Change subject: mb/apple: Add MacBook Pro 10,1 (A1398) support ...................................................................... mb/apple: Add MacBook Pro 10,1 (A1398) support MacBook Pro Retina 15 (Mid 2012) with Ivy Bridge CPU. This is WIP. Not for merging. Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M 3rdparty/vboot A src/mainboard/apple/macbookpro10_1/Kconfig A src/mainboard/apple/macbookpro10_1/Kconfig.name A src/mainboard/apple/macbookpro10_1/Makefile.inc A src/mainboard/apple/macbookpro10_1/acpi/ec.asl A src/mainboard/apple/macbookpro10_1/acpi/platform.asl A src/mainboard/apple/macbookpro10_1/acpi/superio.asl A src/mainboard/apple/macbookpro10_1/acpi_tables.c A src/mainboard/apple/macbookpro10_1/board_info.txt A src/mainboard/apple/macbookpro10_1/devicetree.cb A src/mainboard/apple/macbookpro10_1/dsdt.asl A src/mainboard/apple/macbookpro10_1/gma-mainboard.ads A src/mainboard/apple/macbookpro10_1/gpio.c A src/mainboard/apple/macbookpro10_1/hda_verb.c A src/mainboard/apple/macbookpro10_1/mainboard.c A src/mainboard/apple/macbookpro10_1/romstage.c 16 files changed, 758 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32673/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index e7edff6..304aa42 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit e7edff6653e16ed915c3ad12234d133d1ef4dcc9 +Subproject commit 304aa429c1a04cda3ab2ce37b9e31af84405bfca diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig b/src/mainboard/apple/macbookpro10_1/Kconfig new file mode 100644 index 0000000..603f3ee --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig @@ -0,0 +1,46 @@ +if BOARD_APPLE_MACBOOKPRO10_1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_EDP + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default apple/macbookpro10_1 + +config MAINBOARD_PART_NUMBER + string + default "MacBookPro10,1" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config DRAM_RESET_GATE_GPIO + int + default 28 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig.name b/src/mainboard/apple/macbookpro10_1/Kconfig.name new file mode 100644 index 0000000..c257f7a --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACBOOKPRO10_1 + bool "MacBookPro10,1" diff --git a/src/mainboard/apple/macbookpro10_1/Makefile.inc b/src/mainboard/apple/macbookpro10_1/Makefile.inc new file mode 100644 index 0000000..fd60338 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Makefile.inc @@ -0,0 +1,7 @@ +romstage-y += gpio.c + +cbfs-files-y += spd.bin +spd.bin-file := spd.bin +spd.bin-type := spd + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/apple/macbookpro10_1/acpi/ec.asl b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl new file mode 100644 index 0000000..f70cb3d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/platform.asl b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl new file mode 100644 index 0000000..a17c6ea --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/superio.asl b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl diff --git a/src/mainboard/apple/macbookpro10_1/acpi_tables.c b/src/mainboard/apple/macbookpro10_1/acpi_tables.c new file mode 100644 index 0000000..c48f0bd --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi_tables.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookpro10_1/board_info.txt b/src/mainboard/apple/macbookpro10_1/board_info.txt new file mode 100644 index 0000000..81a5134 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +ROM package: SOIC-8 +ROM socketed: n +Release year: 2012 diff --git a/src/mainboard/apple/macbookpro10_1/devicetree.cb b/src/mainboard/apple/macbookpro10_1/devicetree.cb new file mode 100644 index 0000000..f9e7eb4 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/devicetree.cb @@ -0,0 +1,124 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + #register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0xffffffff" + register "gpu_dp_b_hotplug" = "7" + register "gpu_dp_c_hotplug" = "7" + register "gpu_dp_d_hotplug" = "7" + register "gpu_panel_port_select" = "3" + register "gpu_panel_power_backlight_off_delay" = "8191" + register "gpu_panel_power_backlight_on_delay" = "8191" + register "gpu_panel_power_cycle_delay" = "255" + register "gpu_panel_power_down_delay" = "8191" + register "gpu_panel_power_up_delay" = "8191" + register "gpu_pch_backlight" = "0xffffffff" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x08040201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x8086 0x7270 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x7270 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x8086 0x7270 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x8086 0x7270 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x7270 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x8086 0x7270 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x8086 0x7270 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x8086 0x7270 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x7270 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x7270 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x106b 0x00f7 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x106b 0x00f7 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x106b 0x00f7 + end + device pci 01.2 on + subsystemid 0x106b 0x00f7 + end + device pci 01.1 on + subsystemid 0x106b 0x00f7 + end + end +end diff --git a/src/mainboard/apple/macbookpro10_1/dsdt.asl b/src/mainboard/apple/macbookpro10_1/dsdt.asl new file mode 100644 index 0000000..455ac17 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads new file mode 100644 index 0000000..d4a5d7d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/apple/macbookpro10_1/gpio.c b/src/mainboard/apple/macbookpro10_1/gpio.c new file mode 100644 index 0000000..a445687 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gpio.c @@ -0,0 +1,243 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio11 = GPIO_RESET_RSMRST, + .gpio15 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macbookpro10_1/hda_verb.c b/src/mainboard/apple/macbookpro10_1/hda_verb.c new file mode 100644 index 0000000..b8e4855 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/hda_verb.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b2800, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x106b2800), + + /* NID 0x09. */ + AZALIA_PIN_CFG(0x0, 0x09, 0x002b4020), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x90100112), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x90100110), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x400000f0), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x90a60100), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x004be030), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macbookpro10_1/mainboard.c b/src/mainboard/apple/macbookpro10_1/mainboard.c new file mode 100644 index 0000000..3910541 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/mainboard.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> + +static void mainboard_init(struct device *dev) +{ + +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/apple/macbookpro10_1/romstage.c b/src/mainboard/apple/macbookpro10_1/romstage.c new file mode 100644 index 0000000..c35604b --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/romstage.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <cbfs.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCH_LPC_DEV, 0x82, 0x3f0f); + pci_write_config32(PCH_LPC_DEV, 0x84, 0x000c0681); + pci_write_config32(PCH_LPC_DEV, 0x88, 0x000c1641); + pci_write_config32(PCH_LPC_DEV, 0x8c, 0x001c0301); + pci_write_config32(PCH_LPC_DEV, 0x90, 0x00fc0701); + pci_write_config16(PCH_LPC_DEV, 0x80, 0x0070); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +// FIXME +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + void *spd_file; + size_t spd_file_len = 0; + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (spd_file && spd_file_len >= 128) { + memcpy(&spd[0], spd_file, 128); + memcpy(&spd[2], spd_file, 128); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df Gerrit-Change-Number: 32673 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

11 76

Change in coreboot[master]: {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix
by Angel Pons (Code Review) April 15, 2026

April 15, 2026

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46720 ) Change subject: {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix ...................................................................... {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/northbridge.c 4 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46720/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index fd1ce9e..e0e1e1c 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -84,7 +84,7 @@ /* PCODE MMIO communications live in the MCHBAR. */ #define BIOS_MAILBOX_INTERFACE 0x5da4 -#define MAILBOX_RUN_BUSY (1UL << 31) +#define MAILBOX_RUN_BUSY (1 << 31) #define MAILBOX_BIOS_CMD_READ_PCS 1 #define MAILBOX_BIOS_CMD_WRITE_PCS 2 #define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 1600a42..b95b3fe 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -22,10 +22,10 @@ MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ - MCHBAR32_OR(DMIVCLIM, 1UL << 31); + MCHBAR32_OR(DMIVCLIM, 1 << 31); MCHBAR32_OR(CRDTLCK, 1 << 0); MCHBAR32_OR(MCARBLCK, 1 << 0); - MCHBAR32_OR(REQLIM, 1UL << 31); + MCHBAR32_OR(REQLIM, 1 << 31); MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 66c8d2d..0bca230 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -196,7 +196,7 @@ gtt_write_regs(haswell_gt_setup); /* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1UL << 31), (0UL << 31)); + gtt_poll(0x138124, (1 << 31), (0 << 31)); /* Mailbox Data - RC6 VIDS */ gtt_write(0x138128, 0x00000000); @@ -205,7 +205,7 @@ gtt_write(0x138124, 0x80000004); /* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1UL << 31), (0UL << 31)); + gtt_poll(0x138124, (1 << 31), (0 << 31)); /* Enable PM Interrupts */ gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT | diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 88ccd71..2d19ccd 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -31,18 +31,18 @@ switch ((pciexbar_reg >> 1) & 3) { case 0: /* 256MB */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); *base = pciexbar_reg & mask; *len = 256 * 1024 * 1024; return 1; case 1: /* 128M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27); *base = pciexbar_reg & mask; *len = 128 * 1024 * 1024; return 1; case 2: /* 64M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27) | (1 << 26); *base = pciexbar_reg & mask; *len = 64 * 1024 * 1024; -- To view, visit https://review.coreboot.org/c/coreboot/+/46720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Gerrit-Change-Number: 46720 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: cpu/intel/haswell: Clean up CPUID definitions
by Angel Pons (Code Review) April 14, 2026

April 14, 2026

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46915 ) Change subject: cpu/intel/haswell: Clean up CPUID definitions ...................................................................... cpu/intel/haswell: Clean up CPUID definitions The `mobile` suffix is misleading, since desktop CPUs share the same CPUIDs. Remove unused stepping IDs and add the full CPUIDs instead. Finally, add Broadwell CPUIDs in preparation for merging CPU code. Note that steppings for Haswell in various comments are incorrect. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I19e56b8826b1514550ae95e6363b0df2d08e3cb7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 31 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/46915/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 284ff01..b23fbac 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -5,19 +5,32 @@ #include <stdint.h> -/* Haswell CPU types */ -#define HASWELL_FAMILY_MOBILE 0x306c0 -#define HASWELL_FAMILY_ULT 0x40650 +/* CPU types without stepping */ +#define HASWELL_FAMILY_TRAD 0x306c0 +#define HASWELL_FAMILY_ULT 0x40650 +#define CRYSTALWELL_FAMILY 0x306c0 +#define BROADWELL_FAMILY_ULT 0x306d0 -/* Haswell CPU steppings */ -#define HASWELL_STEPPING_MOBILE_A0 1 -#define HASWELL_STEPPING_MOBILE_B0 2 -#define HASWELL_STEPPING_MOBILE_C0 3 -#define HASWELL_STEPPING_MOBILE_D0 4 -#define HASWELL_STEPPING_ULT_B0 0 -#define HASWELL_STEPPING_ULT_C0 1 +/* Haswell CPUIDs */ +#define CPUID_HASWELL_A0 0x306c1 +#define CPUID_HASWELL_B0 0x306c2 +#define CPUID_HASWELL_C0 0x306c3 -/* Haswell bus clock is fixed at 100MHz */ +#define CPUID_HASWELL_ULT_B0 0x40650 +#define CPUID_HASWELL_ULT_C0 0x40651 + +/* Crystalwell CPUIDs */ +#define CPUID_CRYSTALWELL_B0 0x40660 +#define CPUID_CRYSTALWELL_C0 0x40661 + +/* Broadwell CPUIDs */ +#define CPUID_BROADWELL_C0 0x40671 + +#define CPUID_BROADWELL_ULT_C0 0x306d2 +#define CPUID_BROADWELL_ULT_D0 0x306d3 +#define CPUID_BROADWELL_ULT_E0 0x306d4 + +/* Haswell and Broadwell bus clock is fixed at 100MHz */ #define CPU_BCLK 100 #define MSR_CORE_THREAD_COUNT 0x35 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 44bbbfd..438a317 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -694,13 +694,13 @@ }; static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x306c1 }, /* Intel Haswell 4+2 A0 */ - { X86_VENDOR_INTEL, 0x306c2 }, /* Intel Haswell 4+2 B0 */ - { X86_VENDOR_INTEL, 0x306c3 }, /* Intel Haswell C0 */ - { X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */ - { X86_VENDOR_INTEL, 0x40651 }, /* Intel Haswell ULT B1 */ - { X86_VENDOR_INTEL, 0x40660 }, /* Intel Crystal Well C0 */ - { X86_VENDOR_INTEL, 0x40661 }, /* Intel Crystal Well C1 */ + { X86_VENDOR_INTEL, CPUID_HASWELL_A0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_B0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_C0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_B0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_C0 }, + { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_B0 }, + { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_C0 }, { 0, 0 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/46915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19e56b8826b1514550ae95e6363b0df2d08e3cb7 Gerrit-Change-Number: 46915 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mainboard/dell: Add Latitude E7440
by Pablo Stebler (Code Review) March 10, 2026

March 10, 2026

Pablo Stebler has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46540 ) Change subject: mainboard/dell: Add Latitude E7440 ...................................................................... mainboard/dell: Add Latitude E7440 Based on autoport output. Untested for now. Signed-off-by: Pablo Stebler <pablo(a)stebler.xyz> Change-Id: I9459d8dac9552529fc90633eaadd89f5118b237e --- M src/mainboard/dell/latitude_e7x40/Kconfig M src/mainboard/dell/latitude_e7x40/Kconfig.name A src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/board_info.txt A src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/gpio.c A src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/hda_verb.c A src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/overridetree.cb 6 files changed, 152 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/46540/1 diff --git a/src/mainboard/dell/latitude_e7x40/Kconfig b/src/mainboard/dell/latitude_e7x40/Kconfig index 05ed643..9b9bae7 100644 --- a/src/mainboard/dell/latitude_e7x40/Kconfig +++ b/src/mainboard/dell/latitude_e7x40/Kconfig @@ -23,10 +23,12 @@ config VARIANT_DIR string default "latitude_e7240" if BOARD_DELL_LATITUDE_E7240 + default "latitude_e7440" if BOARD_DELL_LATITUDE_E7440 config MAINBOARD_PART_NUMBER string default "Latitude E7240" if BOARD_DELL_LATITUDE_E7240 + default "Latitude E7440" if BOARD_DELL_LATITUDE_E7440 config VGA_BIOS_FILE string diff --git a/src/mainboard/dell/latitude_e7x40/Kconfig.name b/src/mainboard/dell/latitude_e7x40/Kconfig.name index 5eefdf7..4532758 100644 --- a/src/mainboard/dell/latitude_e7x40/Kconfig.name +++ b/src/mainboard/dell/latitude_e7x40/Kconfig.name @@ -4,3 +4,8 @@ bool "Latitude E7240" select BOARD_DELL_LATITUDE_E7x40 + +config BOARD_DELL_LATITUDE_E7440 + bool "Latitude E7440" + + select BOARD_DELL_LATITUDE_E7x40 diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/board_info.txt b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/board_info.txt new file mode 100644 index 0000000..6d6a545 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/board_info.txt @@ -0,0 +1 @@ +Board URL: https://www.dell.com/support/home/en-us/product-support/product/latitude-e7… diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/gpio.c b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/gpio.c new file mode 100644 index 0000000..89531a3 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/gpio.c @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/lp_gpio.h> + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + [0] = LP_GPIO_OUT_LOW, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [2] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [3] = LP_GPIO_OUT_LOW, + [4] = LP_GPIO_NATIVE, + [5] = LP_GPIO_NATIVE, + [6] = LP_GPIO_NATIVE, + [7] = LP_GPIO_NATIVE, + [8] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [10] = LP_GPIO_OUT_LOW, + [11] = LP_GPIO_NATIVE, + [12] = LP_GPIO_NATIVE, + [13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [14] = LP_GPIO_OUT_LOW, + [15] = LP_GPIO_OUT_LOW, + [16] = LP_GPIO_OUT_HIGH, + [17] = LP_GPIO_OUT_LOW, + [18] = LP_GPIO_NATIVE, + [19] = LP_GPIO_NATIVE, + [20] = LP_GPIO_NATIVE, + [21] = LP_GPIO_NATIVE, + [22] = LP_GPIO_NATIVE, + [23] = LP_GPIO_NATIVE, + [24] = LP_GPIO_OUT_LOW, + [25] = LP_GPIO_OUT_LOW, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = LP_GPIO_OUT_LOW, + [29] = LP_GPIO_NATIVE, + [30] = LP_GPIO_NATIVE, + [31] = LP_GPIO_NATIVE, + [32] = LP_GPIO_NATIVE, + [33] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [34] = LP_GPIO_OUT_HIGH, + [35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [36] = LP_GPIO_OUT_LOW, + [37] = LP_GPIO_NATIVE, + [38] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [40] = LP_GPIO_NATIVE, + [41] = LP_GPIO_NATIVE, + [42] = LP_GPIO_NATIVE, + [43] = LP_GPIO_NATIVE, + [44] = LP_GPIO_OUT_LOW, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [46] = LP_GPIO_OUT_LOW, + [47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [48] = LP_GPIO_OUT_LOW, + [49] = LP_GPIO_OUT_LOW, + [50] = LP_GPIO_OUT_HIGH, + [51] = LP_GPIO_OUT_LOW, + [52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [53] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [54] = LP_GPIO_OUT_LOW, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = LP_GPIO_OUT_HIGH, + [57] = LP_GPIO_OUT_HIGH, + [58] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [60] = LP_GPIO_OUT_LOW, + [61] = LP_GPIO_NATIVE, + [62] = LP_GPIO_NATIVE, + [63] = LP_GPIO_NATIVE, + [64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [65] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [66] = LP_GPIO_OUT_LOW, + [67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [69] = LP_GPIO_OUT_HIGH, + [70] = LP_GPIO_OUT_LOW, + [71] = LP_GPIO_NATIVE, + [72] = LP_GPIO_NATIVE, + [73] = LP_GPIO_OUT_LOW, + [74] = LP_GPIO_NATIVE, + [75] = LP_GPIO_NATIVE, + [76] = LP_GPIO_OUT_HIGH, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [79] = LP_GPIO_NATIVE, + [80] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [81] = LP_GPIO_NATIVE, + [82] = LP_GPIO_NATIVE, + [83] = LP_GPIO_OUT_HIGH, + [84] = LP_GPIO_OUT_HIGH, + [85] = LP_GPIO_OUT_HIGH, + [86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [87] = LP_GPIO_OUT_LOW, + [88] = LP_GPIO_OUT_LOW, + [89] = LP_GPIO_OUT_HIGH, + [90] = LP_GPIO_OUT_HIGH, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [93] = LP_GPIO_OUT_LOW, + [94] = LP_GPIO_OUT_LOW, + LP_GPIO_END +}; diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/hda_verb.c b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/hda_verb.c new file mode 100644 index 0000000..e358006 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ + 0x102805cb, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x102805cb), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x13, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0221401f), + AZALIA_PIN_CFG(0, 0x16, 0x01014020), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x01a19030), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/overridetree.cb b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/overridetree.cb new file mode 100644 index 0000000..cc31dc8 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/overridetree.cb @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/haswell + device domain 0x0 on + subsystemid 0x1028 0x05cb inherit + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/46540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9459d8dac9552529fc90633eaadd89f5118b237e Gerrit-Change-Number: 46540 Gerrit-PatchSet: 1 Gerrit-Owner: Pablo Stebler <pablo(a)stebler.xyz> Gerrit-MessageType: newchange

5 6

[L] Change in coreboot[main]: vc/amd/opensil: Add Phoenix OpenSIL POC directory structure
by Angel Pons (Code Review) Feb. 28, 2026

Feb. 28, 2026

Attention is currently required from: Alicja Michalska, Ana Carolina Cabral, Felix Held, Martin L Roth, Nick Kochlowski. Angel Pons has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/91480?usp=email ) Change subject: vc/amd/opensil: Add Phoenix OpenSIL POC directory structure ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/91480?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04de276c1567c20d1e852efe220efa8131f53843 Gerrit-Change-Number: 91480 Gerrit-PatchSet: 2 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 28 Feb 2026 23:53:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[L] Change in coreboot[main]: vc/amd/opensil: Add Phoenix OpenSIL POC directory structure
by Alicja Michalska (Code Review) Feb. 28, 2026

Feb. 28, 2026

Attention is currently required from: Ana Carolina Cabral, Felix Held, Martin L Roth, Nick Kochlowski. Hello Ana Carolina Cabral, Felix Held, Martin L Roth, Nick Kochlowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/91480?usp=email to look at the new patch set (#2). Change subject: vc/amd/opensil: Add Phoenix OpenSIL POC directory structure ...................................................................... vc/amd/opensil: Add Phoenix OpenSIL POC directory structure Based on genoa_poc, this patch adds directory structure for Phoenix OpenSIL as well as git submodule needed to build it. Subsequent patches will begin adjusting this directory to Phoenix (Zen4) silicon. Change-Id: I04de276c1567c20d1e852efe220efa8131f53843 Signed-off-by: Alicja Michalska <alicja.michalska(a)9elements.com> --- M .gitmodules M src/vendorcode/amd/opensil/Kconfig M src/vendorcode/amd/opensil/Makefile.mk A src/vendorcode/amd/opensil/phoenix_poc/Makefile.mk A src/vendorcode/amd/opensil/phoenix_poc/acpi.c A src/vendorcode/amd/opensil/phoenix_poc/filter.h A src/vendorcode/amd/opensil/phoenix_poc/memmap.c A src/vendorcode/amd/opensil/phoenix_poc/meson_cross.template A src/vendorcode/amd/opensil/phoenix_poc/mpio/Makefile.mk A src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c A src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h A src/vendorcode/amd/opensil/phoenix_poc/opensil A src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template A src/vendorcode/amd/opensil/phoenix_poc/opensil_console.c A src/vendorcode/amd/opensil/phoenix_poc/opensil_console.h A src/vendorcode/amd/opensil/phoenix_poc/ramstage.c A src/vendorcode/amd/opensil/phoenix_poc/romstage.c 17 files changed, 705 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/91480/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/91480?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04de276c1567c20d1e852efe220efa8131f53843 Gerrit-Change-Number: 91480 Gerrit-PatchSet: 2 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[L] Change in coreboot[main]: vendorcode/amd/opensil: Add Phoenix OpenSIL POC directory structure
by Alicja Michalska (Code Review) Feb. 28, 2026

Feb. 28, 2026

Alicja Michalska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/91480?usp=email ) Change subject: vendorcode/amd/opensil: Add Phoenix OpenSIL POC directory structure ...................................................................... vendorcode/amd/opensil: Add Phoenix OpenSIL POC directory structure Based on genoa_poc, this patch adds directory structure for Phoenix OpenSIL as well as git submodule needed to build it. Subsequent patches will begin adjusting this directory to Phoenix (Zen4) silicon. Change-Id: I04de276c1567c20d1e852efe220efa8131f53843 Signed-off-by: Alicja Michalska <alicja.michalska(a)9elements.com> --- M .gitmodules M src/vendorcode/amd/opensil/Kconfig M src/vendorcode/amd/opensil/Makefile.mk A src/vendorcode/amd/opensil/phoenix_poc/Makefile.mk A src/vendorcode/amd/opensil/phoenix_poc/acpi.c A src/vendorcode/amd/opensil/phoenix_poc/filter.h A src/vendorcode/amd/opensil/phoenix_poc/memmap.c A src/vendorcode/amd/opensil/phoenix_poc/meson_cross.template A src/vendorcode/amd/opensil/phoenix_poc/mpio/Makefile.mk A src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c A src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h A src/vendorcode/amd/opensil/phoenix_poc/opensil A src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template A src/vendorcode/amd/opensil/phoenix_poc/opensil_console.c A src/vendorcode/amd/opensil/phoenix_poc/opensil_console.h A src/vendorcode/amd/opensil/phoenix_poc/ramstage.c A src/vendorcode/amd/opensil/phoenix_poc/romstage.c 17 files changed, 705 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/91480/1 diff --git a/.gitmodules b/.gitmodules index 7a8d618..dcb6541 100644 --- a/.gitmodules +++ b/.gitmodules @@ -70,7 +70,12 @@ [submodule "3rdparty/open-power-signing-utils"] path = 3rdparty/open-power-signing-utils url = https://review.coreboot.org/open-power-signing-utils.git +[submodule "src/vendorcode/amd/opensil/phoenix_poc/opensil"] + path = src/vendorcode/amd/opensil/phoenix_poc/opensil + url = https://github.com/openSIL/openSIL.git + branch = phoenix_poc [submodule "src/vendorcode/amd/opensil/turin_poc/opensil"] path = src/vendorcode/amd/opensil/turin_poc/opensil url = https://github.com/openSIL/openSIL.git branch = turin_poc + diff --git a/src/vendorcode/amd/opensil/Kconfig b/src/vendorcode/amd/opensil/Kconfig index 735d6e1..580ea83 100644 --- a/src/vendorcode/amd/opensil/Kconfig +++ b/src/vendorcode/amd/opensil/Kconfig @@ -15,6 +15,12 @@ Select this on SoCs that use the Genoa proof of concept version of openSIL. +config SOC_AMD_OPENSIL_PHOENIX_POC + bool + help + Select this on SoCs that use the Phoenix proof of concept version of + openSIL. + config SOC_AMD_OPENSIL_TURIN_POC bool help @@ -25,6 +31,7 @@ string "Path to openSIL source" depends on !SOC_AMD_OPENSIL_STUB default "$(top)/src/vendorcode/amd/opensil/genoa_poc/opensil" if SOC_AMD_OPENSIL_GENOA_POC + default "$(top)/src/vendorcode/amd/opensil/phoenix_poc/opensil" if SOC_AMD_OPENSIL_PHOENIX_POC default "$(top)/src/vendorcode/amd/opensil/turin_poc/opensil" if SOC_AMD_OPENSIL_TURIN_POC help Set to the path of the openSIL directory containing meson.build. @@ -33,6 +40,7 @@ config AMD_OPENSIL_MPIO_CHIP_H_FILE string "Location of specific MPIO chip.h implementation" default "$(top)/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h" if SOC_AMD_OPENSIL_GENOA_POC + default "$(top)/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h" if SOC_AMD_OPENSIL_PHOENIX_POC default "$(top)/src/vendorcode/amd/opensil/turin_poc/mpio/chip.h" if SOC_AMD_OPENSIL_TURIN_POC default "$(top)/src/vendorcode/amd/opensil/stub/mpio/chip.h" help diff --git a/src/vendorcode/amd/opensil/Makefile.mk b/src/vendorcode/amd/opensil/Makefile.mk index beebaf5..751e6eb 100644 --- a/src/vendorcode/amd/opensil/Makefile.mk +++ b/src/vendorcode/amd/opensil/Makefile.mk @@ -15,6 +15,7 @@ opensil_dir := $(call strip_quotes,$(CONFIG_AMD_OPENSIL_PATH)) subdirs-$(CONFIG_SOC_AMD_OPENSIL_GENOA_POC) += genoa_poc +subdirs-$(CONFIG_SOC_AMD_OPENSIL_PHOENIX_POC) += phoenix_poc subdirs-$(CONFIG_SOC_AMD_OPENSIL_TURIN_POC) += turin_poc ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/Makefile.mk b/src/vendorcode/amd/opensil/phoenix_poc/Makefile.mk new file mode 100644 index 0000000..5d36d56 --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/Makefile.mk @@ -0,0 +1,18 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += mpio + +CPPFLAGS_common += -I$(opensil_dir)/Include -I$(opensil_dir)/xUSL -I$(opensil_dir)/xUSL/Include -I$(opensil_dir)/xUSL/FCH -I$(opensil_dir)/xUSL/FCH/Common -I$(opensil_dir)/xSIM -I$(opensil_dir)/xPRF + +romstage-y += opensil_console.c +romstage-y += romstage.c + +ramstage-y += acpi.c +ramstage-y += memmap.c +ramstage-y += opensil_console.c +ramstage-y += ramstage.c + +$(obj)/romstage/vendorcode/amd/opensil/phoenix_poc/opensil_console.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas +$(obj)/romstage/vendorcode/amd/opensil/phoenix_poc/romstage.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas + +$(obj)/ramstage/vendorcode/amd/opensil/phoenix_poc/opensil_console.o: CFLAGS_ramstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas diff --git a/src/vendorcode/amd/opensil/phoenix_poc/acpi.c b/src/vendorcode/amd/opensil/phoenix_poc/acpi.c new file mode 100644 index 0000000..fcdf167 --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/acpi.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <Sil-api.h> +#include <SilCommon.h> +#include <xSIM-api.h> +#include <FCH/Common/FchCommonCfg.h> + +#include "../opensil.h" + +void opensil_fill_fadt(acpi_fadt_t *fadt) +{ + FCHHWACPI_INPUT_BLK *blk = SilFindStructure(SilId_FchHwAcpiP, 0); + + fadt->pm1a_evt_blk = blk->AcpiPm1EvtBlkAddr; + fadt->pm1a_cnt_blk = blk->AcpiPm1CntBlkAddr; + fadt->pm_tmr_blk = blk->AcpiPmTmrBlkAddr; + fadt->gpe0_blk = blk->AcpiGpe0BlkAddr; +} + +unsigned long add_opensil_acpi_table(unsigned long current, acpi_rsdp_t *rsdp) +{ + return current; +} diff --git a/src/vendorcode/amd/opensil/phoenix_poc/filter.h b/src/vendorcode/amd/opensil/phoenix_poc/filter.h new file mode 100644 index 0000000..f0817f7 --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/filter.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Keep this in sync with openSIL SilCommon.h file */ +#define DEBUG_FILTER_APOB 0x00000001UL +#define DEBUG_FILTER_NBIO 0x00000002UL +#define DEBUG_FILTER_CCX 0x00000004UL +#define DEBUG_FILTER_SMU 0x00000008UL +#define DEBUG_FILTER_DF 0x00000010UL +#define DEBUG_FILTER_MEM 0x00000040UL +#define DEBUG_FILTER_FCH 0x00000080UL +#define DEBUG_FILTER_RAS 0x00000100UL + +#define SIL_DEBUG(topic) (CONFIG(OPENSIL_DEBUG_##topic) ? DEBUG_FILTER_##topic : 0) + +#define SIL_DEBUG_MODULE_FILTER ( \ + SIL_DEBUG(APOB) | \ + SIL_DEBUG(NBIO) | \ + SIL_DEBUG(CCX) | \ + SIL_DEBUG(SMU) | \ + SIL_DEBUG(DF) | \ + SIL_DEBUG(MEM) | \ + SIL_DEBUG(FCH) | \ + SIL_DEBUG(RAS) ) diff --git a/src/vendorcode/amd/opensil/phoenix_poc/memmap.c b/src/vendorcode/amd/opensil/phoenix_poc/memmap.c new file mode 100644 index 0000000..eed1be7 --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/memmap.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <SilCommon.h> +#include <Sil-api.h> // needed above ApobCmn.h +#include <ApobCmn.h> +#include <xPRF-api.h> + +#include "../opensil.h" + +_Static_assert(sizeof(uint32_t) == sizeof(((MEMORY_HOLE_DESCRIPTOR){0}).Type), + "Unexpected size of MEMORY_HOLE_TYPES in the MEMORY_HOLE_DESCRIPTOR " + "struct which doesn't match the code in drivers/amd/opensil/memmap.c"); + +const char *opensil_get_hole_info_type(uint32_t type) +{ + const struct hole_type { + MEMORY_HOLE_TYPES type; + const char *string; + } types[] = { + {UMA, "UMA"}, + {MMIO, "MMIO"}, + {PrivilegedDRAM, "PrivilegedDRAM"}, + {Reserved1TbRemap, "Reserved1TbRemap"}, + {ReservedSLink, "ReservedSLink"}, + {ReservedSLinkAlignment, "ReservedSLinkAlignment"}, + {ReservedDrtm, "ReservedDrtm"}, + {ReservedCvip, "ReservedCvip"}, + {ReservedSmuFeatures, "ReservedSmuFeatures"}, + {ReservedFwtpm, "ReservedFwtpm"}, + {ReservedMpioC20, "ReservedMpioC20"}, + {ReservedNbif, "ReservedNbif"}, + {ReservedCxl, "ReservedCxl"}, + {ReservedCxlAlignment, "ReservedCxlAlignment"}, + {ReservedCpuTmr, "ReservedCpuTmr"}, + {ReservedRasEinj, "ReservedRasEinj"}, + {MaxMemoryHoleTypes, "MaxMemoryHoleTypes"}, + }; + + int i; + MEMORY_HOLE_TYPES enum_type = (MEMORY_HOLE_TYPES)type; // Cast int to enum + for (i = 0; i < ARRAY_SIZE(types); i++) + if (enum_type == types[i].type) + return types[i].string; + return "Unknown type"; +} + +void opensil_get_hole_info(uint32_t *n_holes, uint64_t *top_of_mem, void **hole_info) +{ + SIL_STATUS status = xPrfGetSystemMemoryMap(n_holes, top_of_mem, hole_info); + SIL_STATUS_report("xPrfGetSystemMemoryMap", status); + // Make sure hole_info does not get initialized to something odd by xPRF on failure + if (status != SilPass) { + *hole_info = NULL; + *n_holes = 0; + *top_of_mem = 0; + } +} diff --git a/src/vendorcode/amd/opensil/phoenix_poc/meson_cross.template b/src/vendorcode/amd/opensil/phoenix_poc/meson_cross.template new file mode 100644 index 0000000..6473b65 --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/meson_cross.template @@ -0,0 +1,35 @@ +[binaries] +c = '##COMPILER##' +ar = '##AR##' +nasm = '##NASM##' + +[built-in options] +c_args = ['-nostdinc', + '-I##OBJPATH##', + '-I##COREBOOT_DIR##/src/include', + '-I##COREBOOT_DIR##/src/arch/x86/include', + '-I##COREBOOT_DIR##/src/commonlib/include', + '-I##COREBOOT_DIR##/src/commonlib/bsd/include', + '-include', '##COREBOOT_DIR##/src/include/kconfig.h', + '-include', '##OBJPATH##/config.h', + '-include', '##COREBOOT_DIR##/src/commonlib/bsd/include/commonlib/bsd/compiler.h', + '-include', '##OPENSIL_DIR##/../filter.h', + '-DHAS_STRING_H=1', + # openSIL isn't compatible with coreboot's assert implementation, so use special case + '-D_PORTING_H_=1', + '-DSIL_DEBUG_ENABLE=##SIL_DEBUG_ENABLE##', + # openSIL uses coreboot assert which uses printk which warns about unused-param + '-Wno-unused-parameter', + # ubiquitous problem in openSIL + '-Wno-missing-field-initializers', + ##CLANG_ARGS## + ] + +[host_machine] +system = 'linux' +cpu_family = '##CPU_FAMILY##' +cpu = '##CPU##' +endian = 'little' + +[properties] +is32bit = ##IS32BIT## diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/Makefile.mk b/src/vendorcode/amd/opensil/phoenix_poc/mpio/Makefile.mk new file mode 100644 index 0000000..523ebe7 --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += chip.c + +$(obj)/ramstage/vendorcode/amd/opensil/phoenix_poc/mpio/chip.o: CFLAGS_ramstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c new file mode 100644 index 0000000..587ab81 --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c @@ -0,0 +1,202 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <device/pci_def.h> +#include <Mpio/Common/MpioStructs.h> +#include <Mpio/MpioClass-api.h> +#include <NBIO/NbioClass-api.h> +#include <RcMgr/DfX/RcManager4-api.h> +#include <vendorcode/amd/opensil/opensil.h> +#include <xSIM-api.h> + +#include "chip.h" + +static void mpio_params_config(void) +{ + MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0); + mpio_data->CfgDxioClockGating = 1; + mpio_data->PcieDxioTimingControlEnable = 0; + mpio_data->PCIELinkReceiverDetectionPolling = 0; + mpio_data->PCIELinkResetToTrainingTime = 0; + mpio_data->PCIELinkL0Polling = 0; + mpio_data->PCIeExactMatchEnable = 0; + mpio_data->DxioPhyValid = 1; + mpio_data->DxioPhyProgramming = 1; + mpio_data->CfgSkipPspMessage = 1; + mpio_data->DxioSaveRestoreModes = 0xff; + mpio_data->AmdAllowCompliance = 0; + mpio_data->AmdAllowCompliance = 0xff; + mpio_data->SrisEnableMode = 0xff; + mpio_data->SrisSkipInterval = 0; + mpio_data->SrisSkpIntervalSel = 1; + mpio_data->SrisCfgType = 0; + mpio_data->SrisAutoDetectMode = 0xff; + mpio_data->SrisAutodetectFactor = 0; + mpio_data->SrisLowerSkpOsGenSup = 0; + mpio_data->SrisLowerSkpOsRcvSup = 0; + mpio_data->AmdCxlOnAllPorts = 1; + mpio_data->CxlCorrectableErrorLogging = 1; + mpio_data->CxlUnCorrectableErrorLogging = 1; + // This is also available in Nbio. How to handle duplicate entries? + mpio_data->CfgAEREnable = 1; + mpio_data->CfgMcCapEnable = 0; + mpio_data->CfgRcvErrEnable = 0; + mpio_data->EarlyBmcLinkTraining = 1; + mpio_data->SurpriseDownFeature = 1; + mpio_data->LcMultAutoSpdChgOnLastRateEnable = 0; + mpio_data->AmdRxMarginEnabled = 1; + mpio_data->CfgPcieCVTestWA = 1; + mpio_data->CfgPcieAriSupport = 1; + mpio_data->CfgNbioCTOtoSC = 0; + mpio_data->CfgNbioCTOIgnoreError = 1; + mpio_data->CfgNbioSsid = 0; + mpio_data->CfgIommuSsid = 0; + mpio_data->CfgPspccpSsid = 0; + mpio_data->CfgNtbccpSsid = 0; + mpio_data->CfgNbifF0Ssid = 0; + mpio_data->CfgNtbSsid = 0; + mpio_data->AmdPcieSubsystemDeviceID = 0x1453; + mpio_data->AmdPcieSubsystemVendorID = 0x1022; + mpio_data->GppAtomicOps = 1; + mpio_data->GfxAtomicOps = 1; + mpio_data->AmdNbioReportEdbErrors = 0; + mpio_data->OpnSpare = 0; + mpio_data->AmdPreSilCtrl0 = 0; + mpio_data->MPIOAncDataSupport = 1; + mpio_data->AfterResetDelay = 0; + mpio_data->CfgEarlyLink = 0; + mpio_data->AmdCfgExposeUnusedPciePorts = 1; // Show all ports + mpio_data->CfgForcePcieGenSpeed = 0; + mpio_data->CfgSataPhyTuning = 0; + mpio_data->PcieLinkComplianceModeAllPorts = 0; + mpio_data->AmdMCTPEnable = 0; + mpio_data->SbrBrokenLaneAvoidanceSup = 1; + mpio_data->AutoFullMarginSup = 1; + // A getter and setter, both are needed for this PCD. + mpio_data->AmdPciePresetMask8GtAllPort = 0xffffffff; + // A getter and setter, both are needed for this PCD. + mpio_data->AmdPciePresetMask16GtAllPort = 0xffffffff; + // A getter and setter, both are needed for this PCD. + mpio_data->AmdPciePresetMask32GtAllPort = 0xffffffff; + mpio_data->PcieLinkAspmAllPort = 0xff; + + mpio_data->SyncHeaderByPass = 1; + mpio_data->CxlTempGen5AdvertAltPtcl = 0; + + /* TODO handle this differently on multisocket */ + mpio_data->PcieTopologyData.PlatformData[0].Flags = DESCRIPTOR_TERMINATE_LIST; + mpio_data->PcieTopologyData.PlatformData[0].PciePortList = mpio_data->PcieTopologyData.PortList; +} + +static void nbio_params_config(void) +{ + NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilId_NbioClass, 0); + NBIOCLASS_INPUT_BLK *input = &nbio_data->NbioInputBlk; + input->CfgHdAudioEnable = false; + input->EsmEnableAllRootPorts = false; + input->EsmTargetSpeed = 16; + input->CfgRxMarginPersistenceMode = 1; + input->CfgDxioFrequencyVetting = false; + input->CfgSkipPspMessage = 1; + input->CfgEarlyTrainTwoPcieLinks = false; + input->EarlyBmcLinkTraining = true; + input->EdpcEnable = 0; + input->PcieAerReportMechanism = 2; + input->SevSnpSupport = false; +} + +static void setup_bmc_lanes(uint8_t lane, uint8_t socket) +{ + DFX_RCMGR_INPUT_BLK *rc_mgr_input_block = SilFindStructure(SilId_RcManager, 0); + rc_mgr_input_block->BmcSocket = socket; + rc_mgr_input_block->EarlyBmcLinkLaneNum = lane; + + NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilId_NbioClass, 0); + NBIOCLASS_INPUT_BLK *nbio_input = &nbio_data->NbioInputBlk; + nbio_input->EarlyBmcLinkSocket = socket; + nbio_input->EarlyBmcLinkLaneNum = lane; + nbio_input->EarlyBmcLinkDie = 0; + + MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0); + mpio_data->EarlyBmcLinkSocket = socket; + mpio_data->EarlyBmcLinkLaneNum = lane; + mpio_data->EarlyBmcLinkDie = 0; +} + +void opensil_mpio_per_device_config(struct device *dev) +{ + /* Cache *mpio_data from SilFindStructure */ + static MPIOCLASS_INPUT_BLK *mpio_data = NULL; + if (mpio_data == NULL) { + mpio_data = SilFindStructure(SilId_MpioClass, 0); + } + + static uint32_t slot_num; + const uint32_t domain = dev_get_domain_id(dev); + const uint32_t devfn = dev->path.pci.devfn; + const struct drivers_amd_opensil_mpio_config *const config = dev->chip_info; + printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n", + domain, PCI_SLOT(devfn), PCI_FUNC(devfn)); + + if (config->type == IFTYPE_UNUSED) { + if (is_dev_enabled(dev)) { + printk(BIOS_WARNING, "Unused MPIO chip, disabling PCI device.\n"); + dev->enabled = false; + } else { + printk(BIOS_DEBUG, "Unused MPIO chip, skipping.\n"); + } + return; + } + + if (config->bmc) { + setup_bmc_lanes(config->start_lane, 0); // TODO support multiple sockets + return; + } + + static int mpio_port = 0; + MPIO_PORT_DESCRIPTOR port = { .Flags = DESCRIPTOR_TERMINATE_LIST }; + if (config->type == IFTYPE_PCIE) { + const MPIO_ENGINE_DATA engine_data = + MPIO_ENGINE_DATA_INITIALIZER(MpioPcieEngine, + config->start_lane, config->end_lane, + config->hotplug == HotplugDisabled ? 0 : 1, + config->gpio_group); + port.EngineData = engine_data; + const MPIO_PORT_DATA port_data = + MPIO_PORT_DATA_INITIALIZER_PCIE(is_dev_enabled(dev) ? + MpioPortEnabled : MpioPortDisabled, + PCI_SLOT(devfn), + PCI_FUNC(devfn), + config->hotplug, + config->speed, + 0, // No backup PCIe speed + config->aspm, + config->aspm_l1_1, + config->aspm_l1_2, + config->clock_pm); + port.Port = port_data; + } else if (config->type == IFTYPE_SATA) { + const MPIO_ENGINE_DATA engine_data = + MPIO_ENGINE_DATA_INITIALIZER(MpioSATAEngine, + config->start_lane, config->end_lane, + 0, // meaningless field + config->gpio_group); + port.EngineData = engine_data; + const MPIO_PORT_DATA port_data = { .PortPresent = 1 }; + port.Port = port_data; + + } + port.Port.AlwaysExpose = 1; + port.Port.SlotNum = ++slot_num; + mpio_data->PcieTopologyData.PortList[mpio_port] = port; + /* Update TERMINATE list */ + if (mpio_port > 0) + mpio_data->PcieTopologyData.PortList[mpio_port - 1].Flags = 0; + mpio_port++; +} + +void opensil_mpio_global_config(void) +{ + mpio_params_config(); + nbio_params_config(); +} diff --git a/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h new file mode 100644 index 0000000..0e0e160 --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef OPENSIL_PHOENIX_POC_MPIO_CHIP_H +#define OPENSIL_PHOENIX_POC_MPIO_CHIP_H + +#include <stdint.h> + +/* + * PHOENIX MPIO mapping + * P0 -> [0-15] + * G0 -> [16-31] + * P1 -> [32-47] + * G1 -> [48-63] + * P2 -> [64-79] + * G2 -> [80-95] + * P3 -> [96-111] + * G3 -> [112-127] + * P4 -> [128-131] + * P5 -> [132-136] + */ + +enum mpio_type { + IFTYPE_UNUSED, + IFTYPE_PCIE, + IFTYPE_SATA, +}; + +/* Sync with PCIE_HOTPLUG_TYPE */ +enum mpio_hotplug { + HotplugDisabled, ///< Hotplug disable + Basic, ///< Basic Hotplug + ServerExpress, ///< Server Hotplug Express Module + Enhanced, ///< Enhanced + Inboard, ///< Inboard + ServerEntSSD, ///< Server Hotplug Enterprise SSD + UBM, ///< UBM Backplane + OCP, ///< OCP NIC 3.0 +}; + +enum pcie_link_speed { + MaxSupported, + Gen1, + Gen2, + Gen3, + Gen4, + Gen5, +}; + +/* Sync with PCIE_ASPM_TYPE */ +enum pcie_aspm { + aspm_disabled, + L0s, + L1, + L0sL1, +}; + +struct drivers_amd_opensil_mpio_config { + enum mpio_type type; + uint8_t start_lane; + uint8_t end_lane; + uint8_t gpio_group; + enum mpio_hotplug hotplug; + enum pcie_link_speed speed; + enum pcie_aspm aspm; + uint8_t aspm_l1_1 : 1; + uint8_t aspm_l1_2 : 1; + uint8_t clock_pm : 1; + uint8_t bmc : 1; +}; + +#endif /* OPENSIL_PHOENIX_POC_MPIO_CHIP_H */ diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil b/src/vendorcode/amd/opensil/phoenix_poc/opensil new file mode 160000 index 0000000..52b83c5 --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil @@ -0,0 +1 @@ +Subproject commit 52b83c56a3a653c287f5839a5986eda22677f304 diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template b/src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template new file mode 100644 index 0000000..2ddd3b4 --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template @@ -0,0 +1,5 @@ +CONFIG_PLAT_APOB_ADDRESS=##APOB_BASE## +CONFIG_PSP_BIOS_BIN_BASE=##BIOS_ENTRY_BASE## +CONFIG_PSP_BIOS_BIN_SIZE=##BIOS_ENTRY_SIZE## +CONFIG_PLAT_NUMBER_SOCKETS=1 +CONFIG_SOC_F19M10=y diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil_console.c b/src/vendorcode/amd/opensil/phoenix_poc/opensil_console.c new file mode 100644 index 0000000..35e5eeb --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil_console.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <stdio.h> +#include <string.h> +#include <console/console.h> +#include "opensil_console.h" +#include <SilCommon.h> + +static int translate_opensil_debug_level(size_t MsgLevel) +{ + switch (MsgLevel) { + case SIL_TRACE_ERROR: + return BIOS_ERR; + case SIL_TRACE_WARNING: + return BIOS_WARNING; + case SIL_TRACE_ENTRY: + case SIL_TRACE_EXIT: + return BIOS_SPEW; + case SIL_TRACE_INFO: + return BIOS_DEBUG; + default: + return BIOS_NEVER; + } +} + +void HostDebugService(size_t MsgLevel, const char *SilPrefix, const char *Message, + const char *Function, size_t Line, ...) +{ + if (!CONFIG(OPENSIL_DEBUG_OUTPUT)) + return; + + const int loglevel = translate_opensil_debug_level(MsgLevel); + + /* print fomatted prefix */ + if (CONFIG(OPENSIL_DEBUG_PREFIX)) + printk(loglevel, "%s%s:%zu:", SilPrefix, Function, Line); + + /* print formatted message */ + va_list args; + va_start(args, Line); + vprintk(loglevel, Message, args); + va_end(args); +} diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil_console.h b/src/vendorcode/amd/opensil/phoenix_poc/opensil_console.h new file mode 100644 index 0000000..d3ffb68 --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil_console.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _VENDORCODE_AND_OPENSIL_CONSOLE +#define _VENDORCODE_AND_OPENSIL_CONSOLE + +void HostDebugService(size_t MsgLevel, const char *SilPrefix, const char *Message, + const char *Function, size_t Line, ...); + +#endif diff --git a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c new file mode 100644 index 0000000..5a037fe --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <FCH/Common/FchCommonCfg.h> +#include <FCH/Common/FchCore/FchSata/FchSata.h> +#include <RcMgr/DfX/RcManager4-api.h> +#include <amdblocks/reset.h> +#include <bootstate.h> +#include <cbmem.h> +#include <cpu/cpu.h> +#include <device/device.h> +#include <soc/soc_chip.h> +#include <static.h> +#include <stdio.h> +#include <xSIM-api.h> + +#include "opensil_console.h" +#include "../opensil.h" + +void SIL_STATUS_report(const char *function, const int status) +{ + const int log_level = status == SilPass ? BIOS_DEBUG : BIOS_ERR; + const char *error_string = "Unknown error"; + + const struct error_string_entry { + SIL_STATUS status; + const char *string; + } errors[] = { + {SilPass, "SilPass"}, + {SilUnsupportedHardware, "SilUnsupportedHardware"}, + {SilUnsupported, "SilUnsupported"}, + {SilInvalidParameter, "SilInvalidParameter"}, + {SilAborted, "SilAborted"}, + {SilOutOfResources, "SilOutOfResources"}, + {SilNotFound, "SilNotFound"}, + {SilOutOfBounds, "SilOutOfBounds"}, + {SilDeviceError, "SilDeviceError"}, + {SilResetRequestColdImm, "SilResetRequestColdImm"}, + {SilResetRequestColdDef, "SilResetRequestColdDef"}, + {SilResetRequestWarmImm, "SilResetRequestWarmImm"}, + {SilResetRequestWarmDef, "SilResetRequestWarmDef"}, + }; + + int i; + for (i = 0; i < ARRAY_SIZE(errors); i++) { + if (errors[i].status == status) + error_string = errors[i].string; + } + printk(log_level, "%s returned %d (%s)\n", function, status, error_string); +} + +static void setup_rc_manager_default(void) +{ + DFX_RCMGR_INPUT_BLK *rc_mgr_input_block = SilFindStructure(SilId_RcManager, 0); + /* Let openSIL distribute the resources to the different PCI roots */ + rc_mgr_input_block->SetRcBasedOnNv = false; + + /* Currently 1P is the only supported configuration */ + rc_mgr_input_block->SocketNumber = 1; + rc_mgr_input_block->RbsPerSocket = 4; /* PCI root bridges per socket */ + rc_mgr_input_block->McptEnable = true; + rc_mgr_input_block->PciExpressBaseAddress = CONFIG_ECAM_MMCONF_BASE_ADDRESS; + rc_mgr_input_block->BottomMmioReservedForPrimaryRb = 4ull * GiB - 32 * MiB; + rc_mgr_input_block->MmioSizePerRbForNonPciDevice = 16 * MiB; + /* MmioAbove4GLimit will be adjusted down in openSIL */ + rc_mgr_input_block->MmioAbove4GLimit = POWER_OF_2(cpu_phys_address_size()); + rc_mgr_input_block->Above4GMmioSizePerRbForNonPciDevice = 0; +} + +#define NUM_XHCI_CONTROLLERS 2 +static void configure_usb(void) +{ + const struct soc_amd_phoenix_poc_config *soc_config = config_of_soc(); + const struct soc_usb_config *usb = &soc_config->usb; + + FCHUSB_INPUT_BLK *fch_usb_data = SilFindStructure(SilId_FchUsb, 0); + fch_usb_data->Xhci0Enable = usb->xhci0_enable; + fch_usb_data->Xhci1Enable = usb->xhci1_enable; + fch_usb_data->Xhci2Enable = false; /* there's no XHCI2 on this SoC */ + for (int i = 0; i < NUM_XHCI_CONTROLLERS; i++) { + memcpy(&fch_usb_data->XhciOCpinSelect[i].Usb20OcPin, &usb->usb2_oc_pins[i], + sizeof(fch_usb_data->XhciOCpinSelect[i].Usb20OcPin)); + memcpy(&fch_usb_data->XhciOCpinSelect[i].Usb31OcPin, &usb->usb3_oc_pins[i], + sizeof(fch_usb_data->XhciOCpinSelect[i].Usb31OcPin)); + } + fch_usb_data->XhciOcPolarityCfgLow = usb->polarity_cfg_low; + fch_usb_data->Usb3PortForceGen1 = usb->usb3_force_gen1.raw; + + /* Instead of overwriting the whole OemUsbConfigurationTable, only copy the relevant + fields to the pre-populated data structure */ + fch_usb_data->OemUsbConfigurationTable.Usb31PhyEnable = usb->usb31_phy_enable; + if (usb->usb31_phy_enable) + memcpy(&fch_usb_data->OemUsbConfigurationTable.Usb31PhyPort, usb->usb31_phy, + sizeof(fch_usb_data->OemUsbConfigurationTable.Usb31PhyPort)); + fch_usb_data->OemUsbConfigurationTable.Usb31PhyEnable = usb->s1_usb31_phy_enable; + if (usb->s1_usb31_phy_enable) + memcpy(&fch_usb_data->OemUsbConfigurationTable.S1Usb31PhyPort, usb->s1_usb31_phy, + sizeof(fch_usb_data->OemUsbConfigurationTable.S1Usb31PhyPort)); +} + +#define NUM_SATA_CONTROLLERS 4 +static void configure_sata(void) +{ + FCHSATA_INPUT_BLK *fch_sata_data = SilFindStructure(SilId_FchSata, 0); + FCH_SATA2 *fch_sata_defaults = GetFchSataData(); + for (int i = 0; i < NUM_SATA_CONTROLLERS; i++) { + fch_sata_data[i] = fch_sata_defaults[i]; + fch_sata_data[i].SataSetMaxGen2 = false; + fch_sata_data[i].SataMsiEnable = true; + fch_sata_data[i].SataEspPort = 0xFF; + fch_sata_data[i].SataRasSupport = true; + fch_sata_data[i].SataDevSlpPort1Num = 1; + fch_sata_data[i].SataMsiEnable = true; + fch_sata_data[i].SataControllerAutoShutdown = true; + fch_sata_data[i].SataRxPolarity = 0xFF; + } +} + +void setup_opensil(void) +{ + const SIL_STATUS debug_ret = SilDebugSetup(HostDebugService); + SIL_STATUS_report("SilDebugSetup", debug_ret); + const size_t mem_req = xSimQueryMemoryRequirements(); + void *buf = cbmem_add(CBMEM_ID_AMD_OPENSIL, mem_req); + assert(buf); + /* We run all openSIL timepoints in the same stage so using TP1 as argument is fine. */ + const SIL_STATUS assign_mem_ret = xSimAssignMemoryTp1(buf, mem_req); + SIL_STATUS_report("xSimAssignMemory", assign_mem_ret); + + setup_rc_manager_default(); + configure_usb(); + configure_sata(); +} + +static void opensil_entry(SIL_TIMEPOINT timepoint) +{ + SIL_STATUS ret; + SIL_TIMEPOINT tp = (uintptr_t)timepoint; + + switch (tp) { + case SIL_TP1: + ret = InitializeSiTp1(); + break; + case SIL_TP2: + ret = InitializeSiTp2(); + break; + case SIL_TP3: + ret = InitializeSiTp3(); + break; + default: + printk(BIOS_ERR, "Unknown openSIL timepoint\n"); + return; + } + char opensil_function[16]; + snprintf(opensil_function, sizeof(opensil_function), "InitializeSiTp%d", tp + 1); + SIL_STATUS_report(opensil_function, ret); + if (ret == SilResetRequestColdImm || ret == SilResetRequestColdDef) { + printk(BIOS_INFO, "openSIL requested a cold reset"); + do_cold_reset(); + } else if (ret == SilResetRequestWarmImm || ret == SilResetRequestWarmDef) { + printk(BIOS_INFO, "openSIL requested a warm reset"); + do_warm_reset(); + } +} + +void opensil_xSIM_timepoint_1(void) +{ + opensil_entry(SIL_TP1); +} + +void opensil_xSIM_timepoint_2(void) +{ + opensil_entry(SIL_TP2); +} + +void opensil_xSIM_timepoint_3(void) +{ + opensil_entry(SIL_TP3); +} + +/* TODO: also call timepoints 2 and 3 from coreboot. Are they NOOP? */ diff --git a/src/vendorcode/amd/opensil/phoenix_poc/romstage.c b/src/vendorcode/amd/opensil/phoenix_poc/romstage.c new file mode 100644 index 0000000..5b871f6 --- /dev/null +++ b/src/vendorcode/amd/opensil/phoenix_poc/romstage.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include "opensil_console.h" +#include <xSIM-api.h> +#include <xPRF-api.h> + +#include "../opensil.h" + +uintptr_t opensil_get_low_usable_dram_address(void) +{ + SilDebugSetup(HostDebugService); + uintptr_t low_usable_dram_addr = xPrfGetLowUsableDramAddress(0); + printk(BIOS_DEBUG, "xPrfGetLowUsableDramAddress: 0x%lx\n", low_usable_dram_addr); + + return low_usable_dram_addr; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/91480?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04de276c1567c20d1e852efe220efa8131f53843 Gerrit-Change-Number: 91480 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com>

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[L] Change in coreboot[main]: security/tcg/opal_s3: hook into default SMI/resume paths
by Sean Rhodes (Code Review) Feb. 28, 2026

Feb. 28, 2026

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Martin L Roth, Sean Rhodes. Hello Felix Held, Intel coreboot Reviewers, Jérémy Compostella, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/91045?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: security/tcg/opal_s3: hook into default SMI/resume paths ...................................................................... security/tcg/opal_s3: hook into default SMI/resume paths Provide common entry points for the OPAL S3 unlock feature and wire them into the generic x86 SMM and S3 resume code. - Add opal_s3_smi_{apmc,sleep,sleep_finalize} helpers. - Call these helpers from the default weak mainboard SMI hooks when CONFIG(TCG_OPAL_S3_UNLOCK) is enabled. This keeps the feature usable without forcing boards to implement new SMI handlers. - Trigger the SMM unlock on S3 resume from arch/x86/acpi_s3.c. The SMM side continues to whitelist only the OPAL service and unlock APMC commands and fails closed if any invariant is violated. Change-Id: I86a44760a189219a95914bd3549997880fb0242b Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/arch/x86/acpi_s3.c A src/include/security/tcg/opal_s3_resume.h A src/include/security/tcg/opal_s3_smm.h A src/security/tcg/opal_s3/opal_s3_resume.c A src/security/tcg/opal_s3/opal_s3_smm.c M src/soc/amd/cezanne/smihandler.c M src/soc/amd/common/block/cpu/smm/smi_apmc.c M src/soc/amd/genoa_poc/smihandler.c M src/soc/amd/glinda/smihandler.c M src/soc/amd/mendocino/smihandler.c M src/soc/amd/phoenix/smihandler.c M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/smihandler.c M src/soc/amd/turin_poc/smihandler.c M src/soc/intel/common/block/smm/smihandler.c 15 files changed, 421 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/91045/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/91045?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86a44760a189219a95914bd3549997880fb0242b Gerrit-Change-Number: 91045 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: mb/starlabs/lite: compress FSP-M/S with LZMA
by Sean Rhodes (Code Review) Feb. 28, 2026

Feb. 28, 2026

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/91479?usp=email ) Change subject: mb/starlabs/lite: compress FSP-M/S with LZMA ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/91479?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id135ded10dbe50f5f378e3d2ab126a48634b9d9e Gerrit-Change-Number: 91479 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sat, 28 Feb 2026 21:20:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel: disable S0ix when ME is disabled
by Sean Rhodes (Code Review) Feb. 28, 2026

Feb. 28, 2026

Attention is currently required from: Angel Pons, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Sean Rhodes, Subrata Banik, Tarun, Werner Zeh. Hello Angel Pons, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, Tarun, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/91254?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: soc/intel: disable S0ix when ME is disabled ...................................................................... soc/intel: disable S0ix when ME is disabled S0ix requires an enabled and operational ME. If S0ix is requested but ME is disabled or not in a normal state, force S0ix off before programming FSP parameters. When me_state is Disabled, also clear the s0ix_enable option so setup stays consistent. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Idf642ecd571fb095de9b588f3733d035b6e17bf7 --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/fsp_params.c 10 files changed, 41 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/91254/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/91254?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf642ecd571fb095de9b588f3733d035b6e17bf7 Gerrit-Change-Number: 91254 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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