September 2025 - coreboot-gerrit

Change in ...coreboot[master]: mb/apple: Add MacBook Pro 10,1 (A1398) support
by Evgeny Zinoviev (Code Review) Jan. 17, 2026

Jan. 17, 2026

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32673 Change subject: mb/apple: Add MacBook Pro 10,1 (A1398) support ...................................................................... mb/apple: Add MacBook Pro 10,1 (A1398) support MacBook Pro Retina 15 (Mid 2012) with Ivy Bridge CPU. This is WIP. Not for merging. Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M 3rdparty/vboot A src/mainboard/apple/macbookpro10_1/Kconfig A src/mainboard/apple/macbookpro10_1/Kconfig.name A src/mainboard/apple/macbookpro10_1/Makefile.inc A src/mainboard/apple/macbookpro10_1/acpi/ec.asl A src/mainboard/apple/macbookpro10_1/acpi/platform.asl A src/mainboard/apple/macbookpro10_1/acpi/superio.asl A src/mainboard/apple/macbookpro10_1/acpi_tables.c A src/mainboard/apple/macbookpro10_1/board_info.txt A src/mainboard/apple/macbookpro10_1/devicetree.cb A src/mainboard/apple/macbookpro10_1/dsdt.asl A src/mainboard/apple/macbookpro10_1/gma-mainboard.ads A src/mainboard/apple/macbookpro10_1/gpio.c A src/mainboard/apple/macbookpro10_1/hda_verb.c A src/mainboard/apple/macbookpro10_1/mainboard.c A src/mainboard/apple/macbookpro10_1/romstage.c 16 files changed, 758 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32673/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index e7edff6..304aa42 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit e7edff6653e16ed915c3ad12234d133d1ef4dcc9 +Subproject commit 304aa429c1a04cda3ab2ce37b9e31af84405bfca diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig b/src/mainboard/apple/macbookpro10_1/Kconfig new file mode 100644 index 0000000..603f3ee --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig @@ -0,0 +1,46 @@ +if BOARD_APPLE_MACBOOKPRO10_1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_EDP + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default apple/macbookpro10_1 + +config MAINBOARD_PART_NUMBER + string + default "MacBookPro10,1" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config DRAM_RESET_GATE_GPIO + int + default 28 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig.name b/src/mainboard/apple/macbookpro10_1/Kconfig.name new file mode 100644 index 0000000..c257f7a --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACBOOKPRO10_1 + bool "MacBookPro10,1" diff --git a/src/mainboard/apple/macbookpro10_1/Makefile.inc b/src/mainboard/apple/macbookpro10_1/Makefile.inc new file mode 100644 index 0000000..fd60338 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Makefile.inc @@ -0,0 +1,7 @@ +romstage-y += gpio.c + +cbfs-files-y += spd.bin +spd.bin-file := spd.bin +spd.bin-type := spd + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/apple/macbookpro10_1/acpi/ec.asl b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl new file mode 100644 index 0000000..f70cb3d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/platform.asl b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl new file mode 100644 index 0000000..a17c6ea --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/superio.asl b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl diff --git a/src/mainboard/apple/macbookpro10_1/acpi_tables.c b/src/mainboard/apple/macbookpro10_1/acpi_tables.c new file mode 100644 index 0000000..c48f0bd --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi_tables.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookpro10_1/board_info.txt b/src/mainboard/apple/macbookpro10_1/board_info.txt new file mode 100644 index 0000000..81a5134 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +ROM package: SOIC-8 +ROM socketed: n +Release year: 2012 diff --git a/src/mainboard/apple/macbookpro10_1/devicetree.cb b/src/mainboard/apple/macbookpro10_1/devicetree.cb new file mode 100644 index 0000000..f9e7eb4 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/devicetree.cb @@ -0,0 +1,124 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + #register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0xffffffff" + register "gpu_dp_b_hotplug" = "7" + register "gpu_dp_c_hotplug" = "7" + register "gpu_dp_d_hotplug" = "7" + register "gpu_panel_port_select" = "3" + register "gpu_panel_power_backlight_off_delay" = "8191" + register "gpu_panel_power_backlight_on_delay" = "8191" + register "gpu_panel_power_cycle_delay" = "255" + register "gpu_panel_power_down_delay" = "8191" + register "gpu_panel_power_up_delay" = "8191" + register "gpu_pch_backlight" = "0xffffffff" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x08040201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x8086 0x7270 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x7270 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x8086 0x7270 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x8086 0x7270 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x7270 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x8086 0x7270 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x8086 0x7270 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x8086 0x7270 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x7270 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x7270 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x106b 0x00f7 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x106b 0x00f7 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x106b 0x00f7 + end + device pci 01.2 on + subsystemid 0x106b 0x00f7 + end + device pci 01.1 on + subsystemid 0x106b 0x00f7 + end + end +end diff --git a/src/mainboard/apple/macbookpro10_1/dsdt.asl b/src/mainboard/apple/macbookpro10_1/dsdt.asl new file mode 100644 index 0000000..455ac17 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads new file mode 100644 index 0000000..d4a5d7d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/apple/macbookpro10_1/gpio.c b/src/mainboard/apple/macbookpro10_1/gpio.c new file mode 100644 index 0000000..a445687 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gpio.c @@ -0,0 +1,243 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio11 = GPIO_RESET_RSMRST, + .gpio15 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macbookpro10_1/hda_verb.c b/src/mainboard/apple/macbookpro10_1/hda_verb.c new file mode 100644 index 0000000..b8e4855 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/hda_verb.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b2800, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x106b2800), + + /* NID 0x09. */ + AZALIA_PIN_CFG(0x0, 0x09, 0x002b4020), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x90100112), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x90100110), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x400000f0), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x90a60100), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x004be030), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macbookpro10_1/mainboard.c b/src/mainboard/apple/macbookpro10_1/mainboard.c new file mode 100644 index 0000000..3910541 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/mainboard.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> + +static void mainboard_init(struct device *dev) +{ + +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/apple/macbookpro10_1/romstage.c b/src/mainboard/apple/macbookpro10_1/romstage.c new file mode 100644 index 0000000..c35604b --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/romstage.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <cbfs.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCH_LPC_DEV, 0x82, 0x3f0f); + pci_write_config32(PCH_LPC_DEV, 0x84, 0x000c0681); + pci_write_config32(PCH_LPC_DEV, 0x88, 0x000c1641); + pci_write_config32(PCH_LPC_DEV, 0x8c, 0x001c0301); + pci_write_config32(PCH_LPC_DEV, 0x90, 0x00fc0701); + pci_write_config16(PCH_LPC_DEV, 0x80, 0x0070); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +// FIXME +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + void *spd_file; + size_t spd_file_len = 0; + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (spd_file && spd_file_len >= 128) { + memcpy(&spd[0], spd_file, 128); + memcpy(&spd[2], spd_file, 128); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df Gerrit-Change-Number: 32673 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

11 70

Change in coreboot[master]: mb/google/octopus/variants/dood: Disable XHCI LFPS power management
by Kenneth Chan (Code Review) Nov. 27, 2025

Nov. 27, 2025

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41143 ) Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ...................................................................... mb/google/octopus/variants/dood: Disable XHCI LFPS power management LTE module is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c --- M src/mainboard/google/octopus/variants/dood/overridetree.cb M src/mainboard/google/octopus/variants/dood/variant.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41143/1 diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index 6df9f53..e1f12cf 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -149,4 +149,5 @@ # Disable compliance mode register "DisableComplianceMode" = "1" + register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index e728fe3..ab049a8 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -8,6 +8,7 @@ #include <delay.h> #include <gpio.h> #include <ec/google/chromeec/ec.h> +#include <soc/intel/apollolake/chip.h> enum { SKU_1_LTE = 1, /* Wifi + LTE */ @@ -61,3 +62,21 @@ return; } } + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + + if (cfg != NULL && cfg->disable_xhci_lfps_pm) { + switch (google_chromeec_get_board_sku()) { + case SKU_1_LTE: + case SKU_3_LTE_2CAM: + cfg->disable_xhci_lfps_pm = 1; + return; + default: + return; + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c Gerrit-Change-Number: 41143 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 13

[S] Change in coreboot[main]: mb/google/fatcat/var/lapis: Configure gpio of fingerprint sensor
by Matt DeVillier (Code Review) Sept. 30, 2025

Sept. 30, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/89305?usp=email ) Change subject: mb/google/fatcat/var/lapis: Configure gpio of fingerprint sensor ...................................................................... mb/google/fatcat/var/lapis: Configure gpio of fingerprint sensor Configure PWR_EN and RST GPIO of fingerprint sensor. BUG=b:438785495 TEST='emerge-fatcat coreboot' and boot into os, fingerprint function is ok. Change-Id: If896fa5c0600c4bef9ea2c67a30205bcf2689bd1 Signed-off-by: Hualin Wei <weihualin(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89305 Reviewed-by: Pranava Y N <pranavayn(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/lapis/gpio.c 1 file changed, 8 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved Subrata Banik: Looks good to me, approved Weimin Wu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/fatcat/variants/lapis/gpio.c b/src/mainboard/google/fatcat/variants/lapis/gpio.c index ea6c89f..b288420 100644 --- a/src/mainboard/google/fatcat/variants/lapis/gpio.c +++ b/src/mainboard/google/fatcat/variants/lapis/gpio.c @@ -130,6 +130,8 @@ PAD_NC(GPP_C13, NONE), /* GPP_C14: Not used */ PAD_NC(GPP_C14, NONE), + /* GPP_C15: FP_RST_N */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), /* GPP_C16: USB_C0_LSX_TX ==> TBT_LSX0_TXD */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GPP_C17: USB_C0_LSX_RX ==> TBT_LSX0_RXD */ @@ -232,8 +234,6 @@ PAD_CFG_GPI_APIC(GPP_E17, NONE, PLTRST, LEVEL, NONE), /* GPP_E18: TCHPAD_INT_ODL_LS ==> Not used */ PAD_NC(GPP_E18, NONE), - /* GPP_E19: Not used ==> PANEL_ID0 */ - PAD_NC(GPP_E19, NONE), /* GPP_E20: Not used ==> PANEL_ID1 */ PAD_NC(GPP_E20, NONE), /* GPP_E21: PMC_I2C_PD_INT_ODL ==> PD_SMB1_INT# */ @@ -392,6 +392,12 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* GPP_C15: FP_RST_N */ + PAD_CFG_GPO(GPP_C15, 0, DEEP), + + /* GPP_E19: FP_PWR_EN */ + PAD_CFG_GPO(GPP_E19, 1, PLTRST), + /* GPP_H08: UART0_BUF_RXD */ PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* GPP_H09: UART0_BUF_TXD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/89305?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If896fa5c0600c4bef9ea2c67a30205bcf2689bd1 Gerrit-Change-Number: 89305 Gerrit-PatchSet: 6 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[L] Change in coreboot[main]: acpi: Move most of HEST ACPI table to common code
by Matt DeVillier (Code Review) Sept. 30, 2025

Sept. 30, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/88034?usp=email ) Change subject: acpi: Move most of HEST ACPI table to common code ...................................................................... acpi: Move most of HEST ACPI table to common code This moves most of the vendor and architecture independent code into common ACPI code. Change-Id: I7dca939612a5f3d8d6a148fa67bf0ce891952584 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88034 Reviewed-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/Kconfig M src/acpi/acpi.c M src/include/acpi/acpi.h A src/include/acpi/acpi_apei.h M src/northbridge/amd/pi/00730F01/Kconfig M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/northbridge.c M src/soc/intel/xeon_sp/Kconfig D src/soc/intel/xeon_sp/include/soc/hest.h D src/soc/intel/xeon_sp/ras/Kconfig M src/soc/intel/xeon_sp/ras/Makefile.mk M src/soc/intel/xeon_sp/ras/hest.c M src/soc/intel/xeon_sp/spr/acpi/uncore.asl M src/soc/intel/xeon_sp/uncore_acpi.c 15 files changed, 113 insertions(+), 167 deletions(-) Approvals: build bot (Jenkins): Verified Shuo Liu: Looks good to me, but someone else must approve Anand Vaikar: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 2bb56ba..0d3730b 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -127,3 +127,16 @@ help Selected by platforms that support and fill ACPI Watchdog Action Table (WDAT). + +config ACPI_HEST + bool + depends on HAVE_ACPI_TABLES + help + Selected by platforms that support and fill ACPI Hardware Error Source Table (HEST) + +config ACPI_HEST_ERROR_LOG_BUFFER_SIZE + hex + default 0x4000 + depends on ACPI_HEST + help + Define the size of the HEST ACPI error log buffer diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 07e84f6d..7dad21f 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -14,6 +14,8 @@ */ #include <acpi/acpi.h> +#include <acpi/acpi_apei.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpi_iort.h> #include <acpi/acpi_ivrs.h> #include <acpi/acpigen.h> @@ -1062,20 +1064,32 @@ } /* ACPI 4.0 */ -void acpi_write_hest(acpi_hest_t *hest, - unsigned long (*acpi_fill_hest)(acpi_hest_t *hest)) +static void acpi_create_hest(acpi_header_t *header, void *unused) { - acpi_header_t *header = &(hest->header); + if (!CONFIG(ACPI_HEST)) + return; + + /* Reserve memory for Enhanced error logging */ + void *log_mem = cbmem_add(CBMEM_ID_ACPI_HEST, CONFIG_ACPI_HEST_ERROR_LOG_BUFFER_SIZE); + if (!log_mem) { + printk(BIOS_ERR, "Unable to allocate HEST memory\n"); + return; + } + printk(BIOS_DEBUG, "HEST elog_addr: %p, size:%d\n", log_mem, + CONFIG_ACPI_HEST_ERROR_LOG_BUFFER_SIZE); + + acpi_hest_t *hest = (acpi_hest_t *)header; + uintptr_t current = (uintptr_t)(hest + 1); memset(hest, 0, sizeof(acpi_hest_t)); if (acpi_fill_header(header, "HEST", HEST, sizeof(acpi_hest_t)) != CB_SUCCESS) return; - acpi_fill_hest(hest); + current = acpi_soc_fill_hest(hest, current, log_mem); - /* Calculate checksums. */ - header->checksum = acpi_checksum((void *)hest, header->length); + /* (Re)calculate length. */ + header->length = current - (uintptr_t)hest; } /* ACPI 3.0b */ @@ -1456,6 +1470,7 @@ { acpi_create_tpm2, NULL, sizeof(acpi_tpm2_t) }, { acpi_create_lpit, NULL, sizeof(acpi_lpit_t) }, { acpi_create_madt, NULL, sizeof(acpi_header_t) }, + { acpi_create_hest, NULL, sizeof(acpi_hest_t) }, { acpi_create_bert, NULL, sizeof(acpi_bert_t) }, { acpi_create_spcr, NULL, sizeof(acpi_spcr_t) }, { acpi_create_gtdt, NULL, sizeof(acpi_gtdt_t) }, diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 06dba65..1acdd7f 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1879,11 +1879,9 @@ unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current, u8 enumeration_id, u8 bus, u8 dev, u8 fn); -void acpi_write_hest(acpi_hest_t *hest, - unsigned long (*acpi_fill_hest)(acpi_hest_t *hest)); -unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, - acpi_hest_esd_t *esd, u16 type, void *data, u16 len); +unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, + void *data, u16 len); unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid); diff --git a/src/include/acpi/acpi_apei.h b/src/include/acpi/acpi_apei.h new file mode 100644 index 0000000..b2edc2d --- /dev/null +++ b/src/include/acpi/acpi_apei.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Contains ACPI Platform Error Interfaces (APEI) definitions and declarations. + * These are mostly used by: + * - BERT (Boot Error Record Table) ACPI Table. + * - HEST (Hardware Error Source Table) ACPI Table. + */ + +#ifndef _ACPI_APEI_H_ +#define _ACPI_APEI_H_ + +#include <acpi/acpi.h> + +/* Generic Hardware Error Source Descriptor */ +typedef struct acpi_ghes_esd { + u16 type; + u16 source_id; + u16 related_src_id; + u8 flags; + u8 enabled; + u32 prealloc_erecords; + u32 max_section_per_record; +} __packed acpi_ghes_esd_t; + +typedef struct ghes_record { + acpi_ghes_esd_t esd; + u32 max_raw_data_length; + acpi_addr64_t sts_addr; + acpi_hest_hen_t notify; + u32 err_sts_blk_len; +} __packed ghes_record_t; + +uintptr_t acpi_soc_fill_hest(acpi_hest_t *hest, uintptr_t current, void *log_mem); + +#endif diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index 3c2829e..76a0aa3 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -3,6 +3,7 @@ config NORTHBRIDGE_AMD_PI_00730F01 bool select DRAM_SUPPORT_DDR3 + select ACPI_HEST if NORTHBRIDGE_AMD_PI_00730F01 diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 826c19e..c391451 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_apei.h> #include <commonlib/helpers.h> #include <console/console.h> #include <device/pci_ops.h> @@ -91,22 +92,19 @@ register_new_ioapic(IO_APIC2_ADDR); } -static unsigned long acpi_fill_hest(acpi_hest_t *hest) +uintptr_t acpi_soc_fill_hest(acpi_hest_t *hest, uintptr_t current, void *log_mem) { - void *addr, *current; - - /* Skip the HEST header. */ - current = (void *)(hest + 1); + void *addr; addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, (acpi_hest_esd_t *)current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, (acpi_hest_esd_t *)current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); - return (unsigned long)current; + return current; } static unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) @@ -430,12 +428,6 @@ acpi_header_t *alib; acpi_ivrs_t *ivrs; - /* HEST */ - current = ALIGN_UP(current, 8); - acpi_write_hest((void *)current, acpi_fill_hest); - acpi_add_table(rsdp, (void *)current); - current += ((acpi_header_t *)current)->length; - /* IVRS */ if (is_dev_enabled(DEV_PTR(iommu))) { current = ALIGN_UP(current, 8); diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 2abd9d7..1d23636 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -3,6 +3,7 @@ config SOC_AMD_STONEYRIDGE bool select ACPI_SOC_NVS + select ACPI_HEST select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select COLLECT_TIMESTAMPS_NO_TSC diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index b6ebf4d..e8c3110 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_apei.h> #include <assert.h> #include <amdblocks/acpi.h> #include <amdblocks/biosram.h> @@ -102,24 +103,21 @@ acpigen_pop_len(); } -static unsigned long acpi_fill_hest(acpi_hest_t *hest) +uintptr_t acpi_soc_fill_hest(acpi_hest_t *hest, uintptr_t current, void *log_mem) { - void *addr, *current; - - /* Skip the HEST header. */ - current = (void *)(hest + 1); + void *addr; addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, + current += acpi_create_hest_error_source(hest, (acpi_hest_esd_t *)current, 0, (void *)((u32)addr + 2), *(uint16_t *)addr - 2); addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, + current += acpi_create_hest_error_source(hest, (acpi_hest_esd_t *)current, 1, (void *)((u32)addr + 2), *(uint16_t *)addr - 2); - return (unsigned long)current; + return current; } unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current, @@ -129,14 +127,6 @@ acpi_slit_t *slit; acpi_header_t *alib; acpi_header_t *ivrs; - acpi_hest_t *hest; - - /* HEST */ - current = acpi_align_current(current); - hest = (acpi_hest_t *)current; - acpi_write_hest(hest, acpi_fill_hest); - acpi_add_table(rsdp, (void *)current); - current += hest->header.length; current = acpi_align_current(current); printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 24923a5..eed04fb 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -108,8 +108,7 @@ config SOC_INTEL_XEON_RAS bool - select SOC_ACPI_HEST - select SOC_RAS_ELOG + select ACPI_HEST config HAVE_IOAT_DOMAINS bool diff --git a/src/soc/intel/xeon_sp/include/soc/hest.h b/src/soc/intel/xeon_sp/include/soc/hest.h deleted file mode 100644 index ad79d45..0000000 --- a/src/soc/intel/xeon_sp/include/soc/hest.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _HEST_H_ -#define _HEST_H_ -#include <acpi/acpi.h> - -#define MCE_ERR_POLL_MS_INTERVAL 1000 -#define HEST_PCIE_RP_AER_DESC_TYPE 6 -#define HEST_GHES_DESC_TYPE 9 -#define GHES_MAX_RAW_DATA_LENGTH (((CONFIG_ERROR_LOG_BUFFER_SIZE) >> 1) - 8) -#define GHEST_ERROR_STATUS_BLOCK_LENGTH ((CONFIG_ERROR_LOG_BUFFER_SIZE) >> 1) -#define GHEST_ASSIST (1 << 2) -#define FIRMWARE_FIRST (1 << 0) -#define MEM_VALID_BITS 0x66ff -#define PCIE_VALID_BITS 0xef -#define QWORD_ACCESS 4 -#define NOTIFY_TYPE_SCI 3 - -/* Generic Error Source Descriptor */ -typedef struct acpi_ghes_esd { - u16 type; - u16 source_id; - u16 related_src_id; - u8 flags; - u8 enabled; - u32 prealloc_erecords; - u32 max_section_per_record; -} __packed acpi_ghes_esd_t; - -typedef struct ghes_record { - acpi_ghes_esd_t esd; - u32 max_raw_data_length; - acpi_addr64_t sts_addr; - acpi_hest_hen_t notify; - u32 err_sts_blk_len; -} __packed ghes_record_t; - -unsigned long hest_create(unsigned long current, struct acpi_rsdp *rsdp); - -#endif diff --git a/src/soc/intel/xeon_sp/ras/Kconfig b/src/soc/intel/xeon_sp/ras/Kconfig deleted file mode 100644 index 79c599c..0000000 --- a/src/soc/intel/xeon_sp/ras/Kconfig +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -config SOC_ACPI_HEST - def_bool n - depends on HAVE_ACPI_TABLES - help - This variable provides control for ACPI hardware error source table (HEST) - -config SOC_RAS_ELOG - def_bool n - depends on SOC_ACPI_HEST - help - This variable provides enhanced error logging support used with HEST - -config ERROR_LOG_BUFFER_SIZE - hex - default 0x4000 - depends on SOC_RAS_ELOG - help - This variable allows a configurable error log based on system requirements diff --git a/src/soc/intel/xeon_sp/ras/Makefile.mk b/src/soc/intel/xeon_sp/ras/Makefile.mk index 93c8705..a4c2923 100644 --- a/src/soc/intel/xeon_sp/ras/Makefile.mk +++ b/src/soc/intel/xeon_sp/ras/Makefile.mk @@ -1,3 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -ramstage-$(CONFIG_SOC_ACPI_HEST) += hest.c +ramstage-$(CONFIG_ACPI_HEST) += hest.c diff --git a/src/soc/intel/xeon_sp/ras/hest.c b/src/soc/intel/xeon_sp/ras/hest.c index 2da720a..eb46b00 100644 --- a/src/soc/intel/xeon_sp/ras/hest.c +++ b/src/soc/intel/xeon_sp/ras/hest.c @@ -1,29 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <soc/acpi.h> +#include <acpi/acpi_apei.h> #include <acpi/acpi_gnvs.h> #include <cbmem.h> #include <console/console.h> -#include <soc/hest.h> #include <intelblocks/nvs.h> +#include <soc/acpi.h> -static u64 hest_get_elog_addr(void) -{ - /* The elog address comes from reserved memory */ - struct global_nvs *gnvs; - gnvs = acpi_get_gnvs(); - if (!gnvs) { - printk(BIOS_ERR, "Unable to get gnvs\n"); - return 0; - } +#define MCE_ERR_POLL_MS_INTERVAL 1000 +#define HEST_PCIE_RP_AER_DESC_TYPE 6 +#define HEST_GHES_DESC_TYPE 9 +#define GHES_MAX_RAW_DATA_LENGTH (((CONFIG_ACPI_HEST_ERROR_LOG_BUFFER_SIZE) >> 1) - 8) +#define GHEST_ERROR_STATUS_BLOCK_LENGTH ((CONFIG_ACPI_HEST_ERROR_LOG_BUFFER_SIZE) >> 1) +#define GHEST_ASSIST (1 << 2) +#define FIRMWARE_FIRST (1 << 0) +#define MEM_VALID_BITS 0x66ff +#define PCIE_VALID_BITS 0xef +#define QWORD_ACCESS 4 +#define NOTIFY_TYPE_SCI 3 - /* Runtime logging address */ - printk(BIOS_DEBUG, "\t status blk start addr = %llx\n", gnvs->hest_log_addr); - printk(BIOS_DEBUG, "\t size = %x\n", CONFIG_ERROR_LOG_BUFFER_SIZE); - return gnvs->hest_log_addr; -} - -static u32 acpi_hest_add_ghes(void *current) +static u32 acpi_hest_add_ghes(uintptr_t current, uintptr_t log_mem) { ghes_record_t *rec = (ghes_record_t *)current; u32 size = sizeof(ghes_record_t); @@ -50,51 +46,22 @@ rec->err_sts_blk_len = GHEST_ERROR_STATUS_BLOCK_LENGTH; /* error status block entries start address */ - if (CONFIG(SOC_ACPI_HEST)) - rec->sts_addr.addr = hest_get_elog_addr(); + rec->sts_addr.addr = log_mem; return size; } -static unsigned long acpi_fill_hest(acpi_hest_t *hest) +uintptr_t acpi_soc_fill_hest(acpi_hest_t *hest, uintptr_t current, void *log_mem) { - acpi_header_t *header = &(hest->header); - void *current; - current = (void *)(hest); - void *next = current; - next = hest + 1; - next += acpi_hest_add_ghes(next); + // fill ACPI global non volatile storage with hest elog addr + struct global_nvs *gnvs = acpi_get_gnvs(); + if (gnvs) + gnvs->hest_log_addr = (uintptr_t)log_mem; + else + printk(BIOS_ERR, "ACPI fill HEST: Unable to get gnvs\n"); + + current = acpi_hest_add_ghes(current, (uintptr_t)log_mem); // add first entry hest->error_source_count += 1; - header->length = next - current; - return header->length; -} -unsigned long hest_create(unsigned long current, struct acpi_rsdp *rsdp) -{ - struct global_nvs *gnvs; - acpi_hest_t *hest; - - /* Reserve memory for Enhanced error logging */ - void *mem = cbmem_add(CBMEM_ID_ACPI_HEST, CONFIG_ERROR_LOG_BUFFER_SIZE); - if (!mem) { - printk(BIOS_ERR, "Unable to allocate HEST memory\n"); - return current; - } - - printk(BIOS_DEBUG, "HEST memory created: %p\n", mem); - gnvs = acpi_get_gnvs(); - if (!gnvs) { - printk(BIOS_ERR, "Unable to get gnvs\n"); - return current; - } - gnvs->hest_log_addr = (uintptr_t)mem; - printk(BIOS_DEBUG, "elog_addr: %llx, size:%x\n", gnvs->hest_log_addr, - CONFIG_ERROR_LOG_BUFFER_SIZE); - - current = ALIGN_UP(current, 8); - hest = (acpi_hest_t *)current; - acpi_write_hest(hest, acpi_fill_hest); - acpi_add_table(rsdp, (void *)current); - current += hest->header.length; return current; } diff --git a/src/soc/intel/xeon_sp/spr/acpi/uncore.asl b/src/soc/intel/xeon_sp/spr/acpi/uncore.asl index ab2c3eb..7606624 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/uncore.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/uncore.asl @@ -18,7 +18,7 @@ #include "iiostack.asl" #undef SOCKET - #if CONFIG(SOC_ACPI_HEST) + #if CONFIG(ACPI_HEST) Method (_OSC, 4, NotSerialized) { CreateDWordField (Arg3, 0x00, CDW1) diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index 8651944..7acae31 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -13,7 +13,6 @@ #include <device/pci_ops.h> #include <soc/acpi.h> #include <soc/chip_common.h> -#include <soc/hest.h> #include <soc/iomap.h> #include <soc/numa.h> #include <soc/pci_devs.h> @@ -633,10 +632,5 @@ } } - if (CONFIG(SOC_ACPI_HEST)) { - printk(BIOS_DEBUG, "ACPI: * HEST at %lx\n", current); - current = hest_create(current, rsdp); - } - return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/88034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7dca939612a5f3d8d6a148fa67bf0ce891952584 Gerrit-Change-Number: 88034 Gerrit-PatchSet: 19 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>

1 0

[S] Change in coreboot[main]: mb/intel/ptlrvp: Fix WIFI driver device settings under root port 4
by Matt DeVillier (Code Review) Sept. 30, 2025

Sept. 30, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/89374?usp=email ) Change subject: mb/intel/ptlrvp: Fix WIFI driver device settings under root port 4 ...................................................................... mb/intel/ptlrvp: Fix WIFI driver device settings under root port 4 The commit addresses an issue with discrete WIFI driver configuration under root port 4 in the Intel PtlRvp mainboard. The problem involved incorrect probe settings that allowed the WIFI driver device to remain enabled even when its upstream device was disabled. This led to orphan devices being misidentified as root devices within the Intel Power Engine (PEP) structure, which in turn caused unnecessary MCHC devices to be added under the root port. The fix involves ensuring that the probe settings for the devices managed by the driver are consistent with their upstream device settings. Additionally, the RTD3 driver device type is now set to generic, ensuring that only one PCI device exists under the root port. This prevents the binding of device operations (ops) for the RTD3 driver from interfering with the WIFI generic driver during the scan process. The commit also resolves warnings related to leftover static devices and prompts to check the devicetree.cb. The fix ensures that the probe settings for WIFI_PCIE_6 and WIFI_PCIE_7 are properly configured, preventing device misidentification and ensuring correct functionality. BUG=none TEST=Boot to OS and verify the DSDT tables. Ensure the _DSM function of the PEPD Device returns only one MCHE in a package, specifically \_SB.PCI0.MCHC. Check kernel boot messages for absence of errors like AE_NOT_FOUND related to named reference package elements such as \_SB_.PCI0.RP04.MCHC. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I0a38cfc9bd38393cbf44f0e560c9525526d6bbf2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/89374 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb M src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb 2 files changed, 16 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb index 62a7b59..f88f10f 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb @@ -573,13 +573,19 @@ chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" register "srcclk_pin" = "4" - device pci 00.0 on end + device generic 0 on + probe WIFI WIFI_PCIE_6 + probe WIFI WIFI_PCIE_7 + end end chip drivers/wifi/generic register "add_acpi_dma_property" = "true" register "wake" = "GPE0_DW0_12" # GPP_A12 use usb2_port7 as bluetooth_companion - device pci 00.0 on end + device pci 00.0 on + probe WIFI WIFI_PCIE_6 + probe WIFI WIFI_PCIE_7 + end end end # discrete WLAN device ref pcie_rp5 on diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb index de6cf41..a3f2eaf 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp_chromeec/overridetree.cb @@ -573,13 +573,19 @@ chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" register "srcclk_pin" = "4" - device pci 00.0 on end + device generic 0 on + probe WIFI WIFI_PCIE_6 + probe WIFI WIFI_PCIE_7 + end end chip drivers/wifi/generic register "add_acpi_dma_property" = "true" register "wake" = "GPE0_DW0_12" # GPP_A12 use usb2_port7 as bluetooth_companion - device pci 00.0 on end + device pci 00.0 on + probe WIFI WIFI_PCIE_6 + probe WIFI WIFI_PCIE_7 + end end end # discrete WLAN device ref pcie_rp5 on -- To view, visit https://review.coreboot.org/c/coreboot/+/89374?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0a38cfc9bd38393cbf44f0e560c9525526d6bbf2 Gerrit-Change-Number: 89374 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: mb/google/fatcat: Fix WIFI driver device settings under root port 4
by Matt DeVillier (Code Review) Sept. 30, 2025

Sept. 30, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/89373?usp=email ) Change subject: mb/google/fatcat: Fix WIFI driver device settings under root port 4 ...................................................................... mb/google/fatcat: Fix WIFI driver device settings under root port 4 The commit addresses an issue with discrete WIFI driver configuration under root port 4 in the Google Fatcat mainboard. The problem involved incorrect probe settings that allowed the WIFI driver device to remain enabled even when its upstream device was disabled. This led to orphan devices being misidentified as root devices within the Intel Power Engine (PEP) structure, which in turn caused unnecessary MCHC devices to be added under the root port. The fix involves ensuring that the probe settings for the devices managed by the driver are consistent with their upstream device settings. Additionally, the RTD3 driver device type is now set to generic, ensuring that only one PCI device exists under the root port. This prevents the binding of device operations (ops) for the RTD3 driver from interfering with the WIFI generic driver during the scan process. The commit also resolves warnings related to leftover static devices and prompts to check the devicetree.cb. The fix ensures that the probe settings for WIFI_PCIE_6 and WIFI_PCIE_7 are properly configured, preventing device misidentification and ensuring correct functionality. BUG=none TEST=Boot to OS and verify the DSDT tables. Ensure the _DSM function of the PEPD Device returns only one MCHE in a package, specifically \_SB.PCI0.MCHC. Check kernel boot messages for absence of errors like AE_NOT_FOUND related to named reference package elements such as \_SB_.PCI0.RP04.MCHC. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I40be48c056355d9e2a38b604849eb16565b8699d Reviewed-on: https://review.coreboot.org/c/coreboot/+/89373 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb M src/mainboard/google/fatcat/variants/felino/overridetree.cb 2 files changed, 16 insertions(+), 4 deletions(-) Approvals: Jérémy Compostella: Looks good to me, but someone else must approve build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index 47da1d9..4c75c33 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -579,13 +579,19 @@ chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" register "srcclk_pin" = "4" - device pci 00.0 on end + device generic 0 on + probe WIFI WIFI_PCIE_6 + probe WIFI WIFI_PCIE_7 + end end chip drivers/wifi/generic register "add_acpi_dma_property" = "true" register "wake" = "GPE0_DW0_12" # GPP_A12 use usb2_port7 as bluetooth_companion - device pci 00.0 on end + device pci 00.0 on + probe WIFI WIFI_PCIE_6 + probe WIFI WIFI_PCIE_7 + end end end # discrete WLAN device ref pcie_rp5 on diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb index 7e8c972..7d80164 100644 --- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb @@ -225,13 +225,19 @@ chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" register "srcclk_pin" = "4" - device pci 00.0 on end + device generic 0 on + probe WIFI WIFI_PCIE_6 + probe WIFI WIFI_PCIE_7 + end end chip drivers/wifi/generic register "add_acpi_dma_property" = "true" register "wake" = "GPE0_DW0_12" # GPP_A12 use usb2_port7 as bluetooth_companion - device pci 00.0 on end + device pci 00.0 on + probe WIFI WIFI_PCIE_6 + probe WIFI WIFI_PCIE_7 + end end end # WLAN -- To view, visit https://review.coreboot.org/c/coreboot/+/89373?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40be48c056355d9e2a38b604849eb16565b8699d Gerrit-Change-Number: 89373 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/asrock/imb-1222: Use macros for HDA verb table
by Nicholas Sudsgaard (Code Review) Sept. 30, 2025

Sept. 30, 2025

Attention is currently required from: Maxim Polyakov, Paul Menzel. Nicholas Sudsgaard has posted comments on this change by Maxim Polyakov. ( https://review.coreboot.org/c/coreboot/+/89371?usp=email ) Change subject: mb/asrock/imb-1222: Use macros for HDA verb table ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/89371/comment/0b7a813d_e99082cb?us… : PS3, Line 9: , commit 33b2fb93bbf3 Could remove this commit, as it has no relation to this change. -- To view, visit https://review.coreboot.org/c/coreboot/+/89371?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33d693a483c43a31d6dbb75a97b3ca5f5149fd69 Gerrit-Change-Number: 89371 Gerrit-PatchSet: 3 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 30 Sep 2025 23:45:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/purism: add missing terminators to azalia codec tables
by Nicholas Sudsgaard (Code Review) Sept. 30, 2025

Sept. 30, 2025

Attention is currently required from: Angel Pons. Nicholas Sudsgaard has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/89376?usp=email ) Change subject: mb/purism: add missing terminators to azalia codec tables ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Makes me wonder if using something like `AZALIA_ARRAY_SIZES` to autocompute the codec list's length […] Yeah, the reason why I chose to use a terminator was because it couples the data and size into a single variable. This makes things easier (or less ugly) to handle when you have multiple verb tables. This would be useful as I intend to separate the platform codecs (e.g. intel display audio) from the mainboard codecs. However losing the compiler check does hurt a bit. Maybe we could use a weak function to return the mainboard codecs instead. ``` // Rough code here, just as an example size_t azalia_get_mainboard_codecs(struct azalia_codec **codecs) { *codecs = mainboard_azalia_codecs; return ARRAY_SIZE(mainboard_azalia_codecs); } ``` I suppose this has a few benefits: 1. Has the same amount of compiler checking as `AZALIA_ARRAY_SIZES`. 2. Since weak functions can act like a "default setting", if there are no codecs on the mainboard we can omit the table entirely. Currently we would have to write `struct azalia_codec mainboard_azalia_codecs[] = {};` and when certain boards (e.g. Librem L1UM v2) omit this, the compiler throws `undefined reference to 'mainboard_azalia_codecs'` when address sanitizer is enabled. 3. Could possibly replace `mainboard_azalia_program_runtime_verbs()` as well. 4. Not a global variable? This should also work well when looking for a codec from multiple tables. For example a modified version of the current `find_codec()`: ``` // Rough code here, just as an example // Eh, I always forget how to write function pointer signatures. size_t (*tables)(struct azalia_codecs**)[] = { azalia_get_mainboard_codecs, azalia_get_platform_codecs, }; struct azalia_codec *table; size_t count; for (size_t i = 0; i < ARRAY_SIZE(tables); i++) { count = tables[i](&table); for (size_t j = 0; j < count; j++) { if (table[j]->vendor_id == vid && table[j]->address == addr) return table[j]; } } return NULL; ``` Now, another thing to consider is whether we need `pc_beep_verbs` at all (they seem like regular HDA verbs to me?). Since I haven't looked into it I can't draw any conclusions, but in the case we don't need them then I feel like there is no "advantage" to using the macro compared to the weak function above. Just some ideas, any opinions on this? -- To view, visit https://review.coreboot.org/c/coreboot/+/89376?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea964fb8b92814b57d4c82412c47cf31fa48de66 Gerrit-Change-Number: 89376 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 30 Sep 2025 23:39:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: Haswell NRI: Implement SMBIOS type 16/17
by Ron Nazarov (Code Review) Sept. 30, 2025

Sept. 30, 2025

Ron Nazarov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/89385?usp=email ) Change subject: Haswell NRI: Implement SMBIOS type 16/17 ...................................................................... Haswell NRI: Implement SMBIOS type 16/17 Based on the implementation from Ivy/Sandy Bridge NRI. Tested on a Dell OptiPlex 9020 SFF with libreboot. Change-Id: I5e153258f9f88726f54c98baac0b1788a839f934 Signed-off-by: Ron Nazarov <ron(a)noisytoot.org> --- M src/northbridge/intel/haswell/native_raminit/raminit_main.c M src/northbridge/intel/haswell/native_raminit/raminit_native.c M src/northbridge/intel/haswell/native_raminit/raminit_native.h 3 files changed, 81 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/89385/1 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c index 84db33e..328f777 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c @@ -245,7 +245,7 @@ return status; } -void raminit_main(const enum raminit_boot_mode bootmode) +const struct sysinfo *raminit_main(const enum raminit_boot_mode bootmode) { /* * The mighty_ctrl struct. Will happily nuke the pre-RAM stack @@ -261,7 +261,7 @@ if (bootmode != BOOTMODE_COLD) { status = try_raminit(&mighty_ctrl, fast_boot, ARRAY_SIZE(fast_boot)); if (status == RAMINIT_STATUS_SUCCESS) - return; + return &mighty_ctrl; } /** TODO: Try more than once **/ @@ -269,4 +269,6 @@ if (status != RAMINIT_STATUS_SUCCESS) die("Memory initialization was met with utmost failure and misery\n"); + + return &mighty_ctrl; } diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c index 3ad8ce2..7353259 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c @@ -16,6 +16,73 @@ #include "raminit_native.h" +static uint8_t nb_get_ecc_type(const uint32_t capid0_a) +{ + return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; +} + +static uint16_t nb_slots_per_channel(const uint32_t capid0_a) +{ + return !(capid0_a & CAPID_DDPCD) + 1; +} + +static uint16_t nb_number_of_channels(const uint32_t capid0_a) +{ + return !(capid0_a & CAPID_PDCD) + 1; +} + +static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a) +{ + uint32_t ddrsz; + + /* Values from documentation, which assume two DIMMs per channel */ + switch (CAPID_DDRSZ(capid0_a)) { + case 1: + ddrsz = 8192; + break; + case 2: + ddrsz = 2048; + break; + case 3: + ddrsz = 512; + break; + default: + ddrsz = 16384; + break; + } + + /* Account for the maximum number of DIMMs per channel */ + return (ddrsz / 2) * nb_slots_per_channel(capid0_a); +} + +/* Fill cbmem with information for SMBIOS type 16 and type 17 */ +static void setup_sdram_meminfo(const struct sysinfo *ctrl) +{ + const u16 ddr_freq = (1000 << 8) / ctrl->tCK; + + for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { + for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) { + enum cb_err ret = spd_add_smbios17(channel, slot, ddr_freq, + &ctrl->dimms[channel][slot].data); + if (ret != CB_SUCCESS) + printk(BIOS_ERR, "RAMINIT: Failed to add SMBIOS17\n"); + } + } + + /* The 'spd_add_smbios17' function allocates this CBMEM area */ + struct memory_info *m = cbmem_find(CBMEM_ID_MEMINFO); + if (!m) + return; + + const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); + + const uint16_t channels = nb_number_of_channels(capid0_a); + + m->ecc_type = nb_get_ecc_type(capid0_a); + m->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); + m->number_of_devices = channels * nb_slots_per_channel(capid0_a); +} + static void wait_txt_clear(void) { const struct cpuid_result cpuid = cpuid_ext(1, 0); @@ -90,7 +157,8 @@ static enum raminit_boot_mode do_actual_raminit( const bool s3resume, const bool cpu_replaced, - const enum raminit_boot_mode orig_bootmode) + const enum raminit_boot_mode orig_bootmode, + const struct sysinfo **ctrl) { struct mrc_data md = prepare_mrc_cache(); @@ -158,7 +226,7 @@ * And now, the actual memory initialization thing. */ printk(RAM_DEBUG, "\nStarting native raminit\n"); - raminit_main(bootmode); + *ctrl = raminit_main(bootmode); return bootmode; } @@ -176,8 +244,9 @@ wait_txt_clear(); wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0}); + const struct sysinfo *ctrl; const enum raminit_boot_mode bootmode = - do_actual_raminit(s3resume, cpu_replaced, orig_bootmode); + do_actual_raminit(s3resume, cpu_replaced, orig_bootmode, &ctrl); /** TODO: report_memory_config **/ @@ -204,9 +273,9 @@ system_reset(); } - /* Save training data on non-S3 resumes */ - if (!s3resume) + /* Save training data and set up SMBIOS type 16/17 on non-S3 resumes */ + if (!s3resume) { save_mrc_data(); - - /** TODO: setup_sdram_meminfo **/ + setup_sdram_meminfo(ctrl); + } } diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h index b9e84a1..1401fee 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -476,7 +476,7 @@ "m"(mmxsave)); } -void raminit_main(enum raminit_boot_mode bootmode); +const struct sysinfo *raminit_main(enum raminit_boot_mode bootmode); enum raminit_status collect_spd_info(struct sysinfo *ctrl); enum raminit_status initialise_mpll(struct sysinfo *ctrl); -- To view, visit https://review.coreboot.org/c/coreboot/+/89385?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e153258f9f88726f54c98baac0b1788a839f934 Gerrit-Change-Number: 89385 Gerrit-PatchSet: 1 Gerrit-Owner: Ron Nazarov <ron(a)noisytoot.org>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Use CPU ID mask for all stepping
by Jamie Ryu (Code Review) Sept. 30, 2025

Sept. 30, 2025

Attention is currently required from: Avi Uday, Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N. Jamie Ryu has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/89375?usp=email ) Change subject: soc/intel/pantherlake: Use CPU ID mask for all stepping ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/89375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie52ed860c096a3d157ae6580aeedf3acb8c723ab Gerrit-Change-Number: 89375 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 30 Sep 2025 20:59:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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