August 2025 - coreboot-gerrit - mail.coreboot.org

[M] Change in coreboot[main]: [TEST] soc/qc/sc7280, mb/google/herobrine: Enable firmware splash screen
by Kapil Porwal (Code Review) Aug. 31, 2025

Aug. 31, 2025

Attention is currently required from: Julius Werner, Subrata Banik. Hello Julius Werner, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/88363?usp=email to look at the new patch set (#10). Change subject: [TEST] soc/qc/sc7280, mb/google/herobrine: Enable firmware splash screen ...................................................................... [TEST] soc/qc/sc7280, mb/google/herobrine: Enable firmware splash screen BUG=b:427387842 TEST=Verify firmware splash screen on google/herobrine. Change-Id: Icb74e093d16ab79a75e6de0f48c187a6a6474f00 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/arch/arm64/bl31.c M src/arch/arm64/include/bl31.h M src/mainboard/google/herobrine/Kconfig M src/mainboard/google/herobrine/mainboard.c M src/soc/qualcomm/sc7280/Makefile.mk M src/soc/qualcomm/sc7280/include/soc/addressmap.h M src/soc/qualcomm/sc7280/memlayout.ld M src/soc/qualcomm/sc7280/soc.c 8 files changed, 120 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/88363/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/88363?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb74e093d16ab79a75e6de0f48c187a6a6474f00 Gerrit-Change-Number: 88363 Gerrit-PatchSet: 10 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: [TEST] mb/google/herobrine: Shutdown on critically low battery
by Kapil Porwal (Code Review) Aug. 31, 2025

Aug. 31, 2025

Kapil Porwal has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/88472?usp=email ) Change subject: [TEST] mb/google/herobrine: Shutdown on critically low battery ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/88472?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib220089f6822a8a9ea38352a62489a73f274eb15 Gerrit-Change-Number: 88472 Gerrit-PatchSet: 4 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/qc/common,sc7280: Add support for Qualcomm SPMI
by Kapil Porwal (Code Review) Aug. 31, 2025

Aug. 31, 2025

Kapil Porwal has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/88362?usp=email ) Change subject: soc/qc/common,sc7280: Add support for Qualcomm SPMI ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/88362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6479e0f012f351053128d16275302a5c47e93646 Gerrit-Change-Number: 88362 Gerrit-PatchSet: 5 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/qc/sc7280, mb/google/herobrine: Enable firmware splash screen
by Kapil Porwal (Code Review) Aug. 31, 2025

Aug. 31, 2025

Attention is currently required from: Kapil Porwal, Subrata Banik. Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/88363?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/qc/sc7280, mb/google/herobrine: Enable firmware splash screen ...................................................................... soc/qc/sc7280, mb/google/herobrine: Enable firmware splash screen BUG=b:427387842 TEST=Verify firmware splash screen on google/herobrine. Change-Id: Icb74e093d16ab79a75e6de0f48c187a6a6474f00 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/arch/arm64/bl31.c M src/arch/arm64/include/bl31.h M src/mainboard/google/herobrine/Kconfig M src/mainboard/google/herobrine/mainboard.c M src/soc/qualcomm/sc7280/Makefile.mk M src/soc/qualcomm/sc7280/include/soc/addressmap.h M src/soc/qualcomm/sc7280/memlayout.ld M src/soc/qualcomm/sc7280/soc.c 8 files changed, 120 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/88363/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/88363?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb74e093d16ab79a75e6de0f48c187a6a6474f00 Gerrit-Change-Number: 88363 Gerrit-PatchSet: 9 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>

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[XS] Change in coreboot[main]: util/inteltool/cpu.c: fix compilation using GCC + -Oz
by Fabian Groffen (Code Review) Aug. 31, 2025

Aug. 31, 2025

Fabian Groffen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/89005?usp=email ) Change subject: util/inteltool/cpu.c: fix compilation using GCC + -Oz ...................................................................... util/inteltool/cpu.c: fix compilation using GCC + -Oz x86_64-pc-linux-gnu-gcc -Oz -pipe -march=native -fno-diagnostics-color -I/var/tmp/portage/app-admin/coreboot-utils-4.18-r2/work/coreboot-4.18/util/inteltool -I/var/tmp/portage/app-admin/coreboot-utils-4.18-r2/work/coreboot-4.18/src/commonlib/include -I/var/tmp/portage/app-admin/coreboot-utils-4.18-r /usr/lib/gcc/x86_64-pc-linux-gnu/16/../../../../x86_64-pc-linux-gnu/bin/ld: cpu.o: in function `print_sgx': cpu.c:(.text+0x271): undefined reference to `cpuid_ext' /usr/lib/gcc/x86_64-pc-linux-gnu/16/../../../../x86_64-pc-linux-gnu/bin/ld: cpu.o: in function `print_tme': cpu.c:(.text+0x340): undefined reference to `cpuid_ext' Declaring cpuid_ext static (it isn't exported through inteltool.h) fixes the issue to the function is properly inlined. Signed-off-by: Fabian Groffen <grobian(a)bitzolder.nl> Change-Id: I849d7b7f8415dd5c9336056a6de4bc0c125a2285 --- M util/inteltool/cpu.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/89005/1 diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index ecd3eb4..bd301a0 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -53,7 +53,7 @@ return ret; } -inline cpuid_result_t cpuid_ext(int op, unsigned int ecx) +inline static cpuid_result_t cpuid_ext(int op, unsigned int ecx) { cpuid_result_t result; -- To view, visit https://review.coreboot.org/c/coreboot/+/89005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I849d7b7f8415dd5c9336056a6de4bc0c125a2285 Gerrit-Change-Number: 89005 Gerrit-PatchSet: 1 Gerrit-Owner: Fabian Groffen <grobian(a)bitzolder.nl>

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[XS] Change in coreboot[main]: util/intelmetool/Makefile: ensure bsd include is always used
by Fabian Groffen (Code Review) Aug. 31, 2025

Aug. 31, 2025

Fabian Groffen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/89004?usp=email ) Change subject: util/intelmetool/Makefile: ensure bsd include is always used ...................................................................... util/intelmetool/Makefile: ensure bsd include is always used Ensure that when CFLAGS is already set by the caller, the bsd/includes is added to ensure compilation succeeds. Signed-off-by: Fabian Groffen <grobian(a)bitzolder.nl> Change-Id: Id329bcedb88ea6e84211d5ab3113646af5771b91 --- M util/intelmetool/Makefile 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/89004/1 diff --git a/util/intelmetool/Makefile b/util/intelmetool/Makefile index 3751185..5dd7c20 100644 --- a/util/intelmetool/Makefile +++ b/util/intelmetool/Makefile @@ -6,8 +6,8 @@ CC ?= gcc INSTALL ?= /usr/bin/env install PREFIX ?= /usr/local -CFLAGS ?= -O0 -g -Wall -Wextra -Wno-unused-parameter -Wno-sign-compare -Wno-unused-function \ - -I $(TOP)/src/commonlib/bsd/include +CFLAGS ?= -O0 -g -Wall -Wextra -Wno-unused-parameter -Wno-sign-compare -Wno-unused-function +CFLAGS += -I $(TOP)/src/commonlib/bsd/include LDFLAGS += -lpci -lz OBJS = intelmetool.o me.o me_status.o mmap.o rcba.o msr.o -- To view, visit https://review.coreboot.org/c/coreboot/+/89004?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id329bcedb88ea6e84211d5ab3113646af5771b91 Gerrit-Change-Number: 89004 Gerrit-PatchSet: 1 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org>

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[S] Change in coreboot[main]: tree: use boolean for PcieRpLtrEnable[]
by Elyes Haouas (Code Review) Aug. 30, 2025

Aug. 30, 2025

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/89000?usp=email ) Change subject: tree: use boolean for PcieRpLtrEnable[] ...................................................................... tree: use boolean for PcieRpLtrEnable[] PcieRpLtrEnable[] is a boolean, so use true false. Change-Id: I3ccc64d7bb1a756efe8fc109c51c029a5483c316 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89000 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb M src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb 3 files changed, 11 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb index 14cbb7a..3b05ae9 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb @@ -41,7 +41,7 @@ register "PcieRpClkReqNumber[0]" = "0" register "PcieRpClkSrcNumber[0]" = "0" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" device generic 0 alias dgpu on end end @@ -59,7 +59,7 @@ register "PcieRpClkReqNumber[6]" = "2" register "PcieRpClkSrcNumber[6]" = "2" register "PcieRpAdvancedErrorReporting[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" end # M.2 WWAN - x2 @@ -68,7 +68,7 @@ register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" end # TB3 (Alpine Ridge LP) - x2 @@ -77,7 +77,7 @@ register "PcieRpClkReqNumber[8]" = "4" register "PcieRpClkSrcNumber[8]" = "4" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieRpHotPlug[8]" = "1" end @@ -87,7 +87,7 @@ register "PcieRpClkReqNumber[10]" = "5" register "PcieRpClkSrcNumber[10]" = "5" register "PcieRpAdvancedErrorReporting[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" end end end diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb index 50de1a0..6a933c4 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb @@ -41,7 +41,7 @@ register "PcieRpClkReqNumber[0]" = "0" register "PcieRpClkSrcNumber[0]" = "0" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" device generic 0 alias dgpu on end end @@ -51,7 +51,7 @@ register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" register "PcieRpAdvancedErrorReporting[3]" = "1" - register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "true" end # Ethernet (clobbers RP8) @@ -68,7 +68,7 @@ register "PcieRpClkReqNumber[6]" = "3" register "PcieRpClkSrcNumber[6]" = "3" register "PcieRpAdvancedErrorReporting[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" end # TB3 (Alpine Ridge LP) - x2 @@ -77,7 +77,7 @@ register "PcieRpClkReqNumber[4]" = "4" register "PcieRpClkSrcNumber[4]" = "4" register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpHotPlug[4]" = "1" end @@ -87,7 +87,7 @@ register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" end end end diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index 16df1ef..37dc077 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -179,7 +179,7 @@ device ref uart2 on end device ref pcie_rp9 on register "HybridStorageMode" = "0" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[3]" = "0x08" register "PcieClkSrcClkReq[3]" = "3" register "PcieRpSlotImplemented[8]" = "true" -- To view, visit https://review.coreboot.org/c/coreboot/+/89000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ccc64d7bb1a756efe8fc109c51c029a5483c316 Gerrit-Change-Number: 89000 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: vendorcode/starlabs: Move DMIC disabling code to vendorcode
by Matt DeVillier (Code Review) Aug. 30, 2025

Aug. 30, 2025

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/88942?usp=email ) Change subject: vendorcode/starlabs: Move DMIC disabling code to vendorcode ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: I think a better approach here would be to put these things in `src/mainboard/starlabs/common/` rather than vendorcode, as the latter is intended for code not written for coreboot, and is excluded from some code checks and statistics -- To view, visit https://review.coreboot.org/c/coreboot/+/88942?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If861c479c975c804a7eebbfb88d67e44807323ab Gerrit-Change-Number: 88942 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sat, 30 Aug 2025 22:08:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/dedede/var/dexi: Add and use VBT
by Felix Singer (Code Review) Aug. 30, 2025

Aug. 30, 2025

Attention is currently required from: Matt DeVillier. Felix Singer has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/89003?usp=email ) Change subject: mb/google/dedede/var/dexi: Add and use VBT ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/89003?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ed620cb4b8a9b42ca97a96df4b5d30196945084 Gerrit-Change-Number: 89003 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sat, 30 Aug 2025 20:54:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/dedede/var/dita: Add and use VBT
by Felix Singer (Code Review) Aug. 30, 2025

Aug. 30, 2025

Attention is currently required from: Matt DeVillier. Felix Singer has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/89002?usp=email ) Change subject: mb/google/dedede/var/dita: Add and use VBT ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/89002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idbc25deeaa011581221019119dbe4923db428850 Gerrit-Change-Number: 89002 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sat, 30 Aug 2025 20:54:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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