August 2025 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: sb/intel/lynxpoint: Use Broadwell SerialIO implementation
by Angel Pons (Code Review) Feb. 27, 2026

Feb. 27, 2026

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46969 ) Change subject: sb/intel/lynxpoint: Use Broadwell SerialIO implementation ...................................................................... sb/intel/lynxpoint: Use Broadwell SerialIO implementation Add power state control methods for more devices using helper methods. Change-Id: I96a3b896346f6f1e5aa4a1dc45638cbcff01b7dd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/serialio.asl 1 file changed, 96 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46969/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 845949c..0e246f7 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -16,6 +16,28 @@ External (\S6EN) External (\S7EN) +// Put SerialIO device in D0 state +// Arg0 - Ref to offset 0x84 of device's PCI config space +Method (LPD0, 1, Serialized) +{ + DeRefOf (Arg0) &= 0xFFFFFFFC + Local0 = DeRefOf (Arg0) // Read back after writing + + // Use Local0 to avoid iasl warning: Method Local is set but never used + Local0 &= Ones +} + +// Put SerialIO device in D3 state +// Arg0 - Ref to offset 0x84 of device's PCI config space +Method (LPD3, 1, Serialized) +{ + DeRefOf (Arg0) |= 0x3 + Local0 = DeRefOf (Arg0) // Read back after writing + + // Use Local0 to avoid iasl warning: Method Local is set but never used + Local0 &= Ones +} + // Serial IO Resource Consumption for BAR1 Device (SIOR) { @@ -193,32 +215,20 @@ } } - // Access to PCI Config in ACPI mode - OperationRegion (KEYS, SystemMemory, \S1B1, 0x100) - Field (KEYS, DWordAcc, NoLock, Preserve) + OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) { - Offset (0x84), - PSAT, 32, + SPCS, 32 } - // Put controller in D0 state Method (_PS0, 0, Serialized) { - ^PSAT &= 0xfffffffc - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD0 (RefOf (SPCS)) } - // Put controller in D3Hot state Method (_PS3, 0, Serialized) { - ^PSAT |= 0x00000003 - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD3 (RefOf (SPCS)) } } @@ -273,32 +283,20 @@ } } - // Access to PCI Config in ACPI mode - OperationRegion (KEYS, SystemMemory, \S2B1, 0x100) - Field (KEYS, DWordAcc, NoLock, Preserve) + OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) { - Offset (0x84), - PSAT, 32, + SPCS, 32 } - // Put controller in D0 state Method (_PS0, 0, Serialized) { - ^PSAT &= 0xfffffffc - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD0 (RefOf (SPCS)) } - // Put controller in D3Hot state Method (_PS3, 0, Serialized) { - ^PSAT |= 0x00000003 - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD3 (RefOf (SPCS)) } } @@ -337,6 +335,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (SPI1) @@ -386,6 +400,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (UAR0) @@ -435,6 +465,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (UAR1) @@ -472,6 +518,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (SDIO) -- To view, visit https://review.coreboot.org/c/coreboot/+/46969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96a3b896346f6f1e5aa4a1dc45638cbcff01b7dd Gerrit-Change-Number: 46969 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods
by Angel Pons (Code Review) Feb. 27, 2026

Feb. 27, 2026

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46967 ) Change subject: soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods ...................................................................... soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods Creating named objects within a method is highly inefficient. So, pass a reference to the OperationRegion field that needs to be updated instead. Change-Id: I88272fc5cbe35427ccb5fc50789d47b66ace88fe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 54 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46967/1 diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index b03bcdd..35b15b4 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -6,34 +6,22 @@ #define SIO_BAR_LEN 0x1000 // Put SerialIO device in D0 state -// Arg0 - BAR1 of device +// Arg0 - Ref to offset 0x84 of device's PCI config space Method (LPD0, 1, Serialized) { - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) - Field (SPRT, DWordAcc, NoLock, Preserve) - { - SPCS, 32 - } - - SPCS &= 0xFFFFFFFC - Local0 = SPCS // Read back after writing + DeRefOf (Arg0) &= 0xFFFFFFFC + Local0 = DeRefOf (Arg0) // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used Local0 &= Ones } // Put SerialIO device in D3 state -// Arg0 - BAR1 of device +// Arg0 - Ref to offset 0x84 of device's PCI config space Method (LPD3, 1, Serialized) { - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) - Field (SPRT, DWordAcc, NoLock, Preserve) - { - SPCS, 32 - } - - SPCS |= 0x3 - Local0 = SPCS // Read back after writing + DeRefOf (Arg0) |= 0x3 + Local0 = DeRefOf (Arg0) // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used Local0 &= Ones @@ -226,14 +214,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S1B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S1B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -297,14 +291,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S2B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S2B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -353,14 +353,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S3B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S3B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -421,14 +427,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S4B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S4B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -489,14 +501,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S5B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S5B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -545,14 +563,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S6B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S6B1) + ^^LPD3 (RefOf (SPCS)) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88272fc5cbe35427ccb5fc50789d47b66ace88fe Gerrit-Change-Number: 46967 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/variants/dood: Disable XHCI LFPS power management
by Kenneth Chan (Code Review) Nov. 27, 2025

Nov. 27, 2025

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41143 ) Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ...................................................................... mb/google/octopus/variants/dood: Disable XHCI LFPS power management LTE module is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c --- M src/mainboard/google/octopus/variants/dood/overridetree.cb M src/mainboard/google/octopus/variants/dood/variant.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41143/1 diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index 6df9f53..e1f12cf 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -149,4 +149,5 @@ # Disable compliance mode register "DisableComplianceMode" = "1" + register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index e728fe3..ab049a8 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -8,6 +8,7 @@ #include <delay.h> #include <gpio.h> #include <ec/google/chromeec/ec.h> +#include <soc/intel/apollolake/chip.h> enum { SKU_1_LTE = 1, /* Wifi + LTE */ @@ -61,3 +62,21 @@ return; } } + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + + if (cfg != NULL && cfg->disable_xhci_lfps_pm) { + switch (google_chromeec_get_board_sku()) { + case SKU_1_LTE: + case SKU_3_LTE_2CAM: + cfg->disable_xhci_lfps_pm = 1; + return; + default: + return; + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c Gerrit-Change-Number: 41143 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/magolor: Configure I2C high and low time
by Ren Kuo (Code Review) Sept. 16, 2025

Sept. 16, 2025

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46613 ) Change subject: mb/google/dedede/var/magolor: Configure I2C high and low time ...................................................................... mb/google/dedede/var/magolor: Configure I2C high and low time Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:168783630 TEST=Measured the I2C bus frequency reduce to 387 KHz. Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1 --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/46613/1 diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index f41e9fa..625546e 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -25,18 +25,42 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[3] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/46613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1 Gerrit-Change-Number: 46613 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mainboard/emulation/qemu-q35: Do not compile memmap into SMM
by Matt DeVillier (Code Review) Aug. 31, 2025

Aug. 31, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/88995?usp=email ) Change subject: mainboard/emulation/qemu-q35: Do not compile memmap into SMM ...................................................................... mainboard/emulation/qemu-q35: Do not compile memmap into SMM This file contains functions related to PCIe and SMM, and so it's needed by bootblock and ramstage, and possibly romstage. It's not needed by SMM, and in a follow-up, the SMI handler will define `smm_region`, causing a function redefinition error. As this file isn't needed in SMM, and the SMI handler's function will work for this board too, as it works for all silicon (it returns values populated during ramstage, by board/silicon implementations of the function), drop this compilation unit from SMM. Change-Id: I0195e7d42b0669d675879fb4d2596aa4607095b9 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88995 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/emulation/qemu-q35/Makefile.mk 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/emulation/qemu-q35/Makefile.mk b/src/mainboard/emulation/qemu-q35/Makefile.mk index fc85e64..2ad19b9 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.mk +++ b/src/mainboard/emulation/qemu-q35/Makefile.mk @@ -21,5 +21,4 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c smm-y += ../qemu-i440fx/rom_media.c -smm-y += memmap.c smm-y += smihandler.c -- To view, visit https://review.coreboot.org/c/coreboot/+/88995?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0195e7d42b0669d675879fb4d2596aa4607095b9 Gerrit-Change-Number: 88995 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/dedede/var/dexi: Add and use VBT
by Matt DeVillier (Code Review) Aug. 31, 2025

Aug. 31, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/89003?usp=email ) Change subject: mb/google/dedede/var/dexi: Add and use VBT ...................................................................... mb/google/dedede/var/dexi: Add and use VBT Extracted from coreboot-Google_Dexi.13606.639.0.bin TEST=build google/dexi, verify image built with VBT. Change-Id: I7ed620cb4b8a9b42ca97a96df4b5d30196945084 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89003 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/google/dedede/Kconfig A src/mainboard/google/dedede/variants/dexi/data.vbt 2 files changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 2bff7fb..19dd260 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -121,6 +121,7 @@ select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_DIBBI select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 diff --git a/src/mainboard/google/dedede/variants/dexi/data.vbt b/src/mainboard/google/dedede/variants/dexi/data.vbt new file mode 100644 index 0000000..31bf653 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dexi/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/89003?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ed620cb4b8a9b42ca97a96df4b5d30196945084 Gerrit-Change-Number: 89003 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/dedede/var/dita: Add and use VBT
by Matt DeVillier (Code Review) Aug. 31, 2025

Aug. 31, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/89002?usp=email ) Change subject: mb/google/dedede/var/dita: Add and use VBT ...................................................................... mb/google/dedede/var/dita: Add and use VBT Extracted from coreboot-Google_Dita.13606.639.0.bin TEST=build google/dita, verify image built with VBT. Change-Id: Idbc25deeaa011581221019119dbe4923db428850 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89002 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/Kconfig A src/mainboard/google/dedede/variants/dita/data.vbt 2 files changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 2f94fa6..2bff7fb 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -135,6 +135,7 @@ select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_DRAWCIA select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 diff --git a/src/mainboard/google/dedede/variants/dita/data.vbt b/src/mainboard/google/dedede/variants/dita/data.vbt new file mode 100644 index 0000000..31bf653 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dita/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/89002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idbc25deeaa011581221019119dbe4923db428850 Gerrit-Change-Number: 89002 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: util/kconfig: Fix xconfig
by Dmytro (Code Review) Aug. 31, 2025

Aug. 31, 2025

Dmytro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/89006?usp=email ) Change subject: util/kconfig: Fix xconfig ...................................................................... util/kconfig: Fix xconfig The QT based xconfig util is broken for several reasons. 1. On systems with qt6 (which is a majority on modern distros), the qconf-cfg.sh script appends a c++17 flag to the output file, which makes the value of $(HOSTCXXFLAGS_qconf.o) - a multiline string. This causes problem during compiler invocation, thus we can observe: 'g++: fatal error: no input files' Flattening the HOSTCXXFLAGS_ with $strip function resolves the problem 2. The missing Qt's Meta-Object file "qconf-moc.cc", which should be autogenerated during build by invoking "moc" tool. The current set of recipes in Makefile.mk aren't triggering the moc generation. Explicitly adding "qconf-moc.o" target, with dependency on "qconf-moc.cc" resolves the problem. 3. "$(call if_changed,moc)" used to invoke "moc" tool isn't working, due to missing "if_changed" macro. Replace it with direct call to "cmd_moc" in "Makefile.real". Bringing the full implementation of "if_changed" seem to be impractical, as it uses too many dependent functions and macros. BUG=https://ticket.coreboot.org/issues/518 Change-Id: I7eb1e71aeb6a92b8d3c194a369bd3bd6dc708863 Signed-off-by: Dmytro Aleksandrov <alkersan(a)gmail.com> --- M util/kconfig/Makefile.mk 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/89006/1 diff --git a/util/kconfig/Makefile.mk b/util/kconfig/Makefile.mk index 83fad88..4fb8631 100644 --- a/util/kconfig/Makefile.mk +++ b/util/kconfig/Makefile.mk @@ -20,6 +20,7 @@ -e "s,\$$(srctree)/arch/\$$(SRCARCH)/configs/\$$(KBUILD_DEFCONFIG),\$$(KBUILD_DEFCONFIG)," \ -e "s,--defconfig=arch/\$$(SRCARCH)/configs/\$$(KBUILD_DEFCONFIG),--defconfig=\$$(KBUILD_DEFCONFIG)," \ -e "/^unexport CONFIG_$$/d" \ + -e "s/if_changed,moc/cmd_moc/g" \ $< > $@.tmp mv $@.tmp $@ @@ -57,16 +58,16 @@ filechk=$< > $@ $(objk)/%.o: $(srck)/%.c - $(HOSTCC) -I $(srck) -I $(objk) -c $(HOSTCFLAGS_$(notdir $@)) -o $@ $< + $(HOSTCC) -I $(srck) -I $(objk) -c $(strip $(HOSTCFLAGS_$(notdir $@))) -o $@ $< $(objk)/%.o: $(srck)/%.cc - $(HOSTCXX) -I $(srck) -I $(objk) -c $(HOSTCXXFLAGS_$(notdir $@)) -o $@ $< + $(HOSTCXX) -I $(srck) -I $(objk) -c $(strip $(HOSTCXXFLAGS_$(notdir $@))) -o $@ $< $(objk)/%.o: $(objk)/%.c $(HOSTCC) -I $(srck) -I $(objk) -c -o $@ $< -$(objk)/%.moc: $(srck)/%.h | $(objk)/qconf-cfg - $(call cmd_moc) +$(objk)/qconf-moc.o: $(objk)/qconf-moc.cc + $(HOSTCXX) -I $(srck) -I $(objk) -c $(strip $(HOSTCXXFLAGS_$(notdir $@))) -o $@ $< define hostprogs_template # $1 entry in hostprogs -- To view, visit https://review.coreboot.org/c/coreboot/+/89006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7eb1e71aeb6a92b8d3c194a369bd3bd6dc708863 Gerrit-Change-Number: 89006 Gerrit-PatchSet: 1 Gerrit-Owner: Dmytro

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[XS] Change in coreboot[main]: ec/lenovo/h8: Disable POST codes
by Patrick Rudolph (Code Review) Aug. 31, 2025

Aug. 31, 2025

Attention is currently required from: Alexander Couzens, Angel Pons. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/88999?usp=email ) Change subject: ec/lenovo/h8: Disable POST codes ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/88999/comment/d8931001_0310688a?us… : PS1, Line 10: no POST code display on the laptops > Is the LPC bus accessible or exposed anywhere? Some laptops have connections for LPC on the mPCIe sl […] There are debug LPC connectors, though not sure if they are soldered down on production boards. -- To view, visit https://review.coreboot.org/c/coreboot/+/88999?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf666796d3cbb504c6e68d84521359d7e2fe98d0 Gerrit-Change-Number: 88999 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 31 Aug 2025 16:39:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: ec/lenovo/h8: Turn on PWR LED
by Patrick Rudolph (Code Review) Aug. 31, 2025

Aug. 31, 2025

Attention is currently required from: Alexander Couzens, Angel Pons, Patrick Rudolph, Paul Menzel. Hello Alexander Couzens, Angel Pons, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/88998?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Code-Review+2 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: ec/lenovo/h8: Turn on PWR LED ...................................................................... ec/lenovo/h8: Turn on PWR LED On warm reboot the PWR LED isn't automatically turned on by the EC. Turn it on in the ramstage code, which allows to see when the reboot has happened. TEST=PWR LED is on after warm reboot on Lenovo X220. Change-Id: Ia5fe3a52a6be622785c9588a94242ac0de0e19fa Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/ec/lenovo/h8/h8.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/88998/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/88998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5fe3a52a6be622785c9588a94242ac0de0e19fa Gerrit-Change-Number: 88998 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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