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Change in coreboot[master]: cpu/intel/haswell: Clean up CPUID definitions
by Angel Pons (Code Review) March 7, 2026

March 7, 2026

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46915 ) Change subject: cpu/intel/haswell: Clean up CPUID definitions ...................................................................... cpu/intel/haswell: Clean up CPUID definitions The `mobile` suffix is misleading, since desktop CPUs share the same CPUIDs. Remove unused stepping IDs and add the full CPUIDs instead. Finally, add Broadwell CPUIDs in preparation for merging CPU code. Note that steppings for Haswell in various comments are incorrect. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I19e56b8826b1514550ae95e6363b0df2d08e3cb7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 31 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/46915/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 284ff01..b23fbac 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -5,19 +5,32 @@ #include <stdint.h> -/* Haswell CPU types */ -#define HASWELL_FAMILY_MOBILE 0x306c0 -#define HASWELL_FAMILY_ULT 0x40650 +/* CPU types without stepping */ +#define HASWELL_FAMILY_TRAD 0x306c0 +#define HASWELL_FAMILY_ULT 0x40650 +#define CRYSTALWELL_FAMILY 0x306c0 +#define BROADWELL_FAMILY_ULT 0x306d0 -/* Haswell CPU steppings */ -#define HASWELL_STEPPING_MOBILE_A0 1 -#define HASWELL_STEPPING_MOBILE_B0 2 -#define HASWELL_STEPPING_MOBILE_C0 3 -#define HASWELL_STEPPING_MOBILE_D0 4 -#define HASWELL_STEPPING_ULT_B0 0 -#define HASWELL_STEPPING_ULT_C0 1 +/* Haswell CPUIDs */ +#define CPUID_HASWELL_A0 0x306c1 +#define CPUID_HASWELL_B0 0x306c2 +#define CPUID_HASWELL_C0 0x306c3 -/* Haswell bus clock is fixed at 100MHz */ +#define CPUID_HASWELL_ULT_B0 0x40650 +#define CPUID_HASWELL_ULT_C0 0x40651 + +/* Crystalwell CPUIDs */ +#define CPUID_CRYSTALWELL_B0 0x40660 +#define CPUID_CRYSTALWELL_C0 0x40661 + +/* Broadwell CPUIDs */ +#define CPUID_BROADWELL_C0 0x40671 + +#define CPUID_BROADWELL_ULT_C0 0x306d2 +#define CPUID_BROADWELL_ULT_D0 0x306d3 +#define CPUID_BROADWELL_ULT_E0 0x306d4 + +/* Haswell and Broadwell bus clock is fixed at 100MHz */ #define CPU_BCLK 100 #define MSR_CORE_THREAD_COUNT 0x35 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 44bbbfd..438a317 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -694,13 +694,13 @@ }; static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x306c1 }, /* Intel Haswell 4+2 A0 */ - { X86_VENDOR_INTEL, 0x306c2 }, /* Intel Haswell 4+2 B0 */ - { X86_VENDOR_INTEL, 0x306c3 }, /* Intel Haswell C0 */ - { X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */ - { X86_VENDOR_INTEL, 0x40651 }, /* Intel Haswell ULT B1 */ - { X86_VENDOR_INTEL, 0x40660 }, /* Intel Crystal Well C0 */ - { X86_VENDOR_INTEL, 0x40661 }, /* Intel Crystal Well C1 */ + { X86_VENDOR_INTEL, CPUID_HASWELL_A0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_B0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_C0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_B0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_C0 }, + { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_B0 }, + { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_C0 }, { 0, 0 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/46915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19e56b8826b1514550ae95e6363b0df2d08e3cb7 Gerrit-Change-Number: 46915 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: sb/intel/lynxpoint: Use Broadwell SerialIO implementation
by Angel Pons (Code Review) Feb. 27, 2026

Feb. 27, 2026

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46969 ) Change subject: sb/intel/lynxpoint: Use Broadwell SerialIO implementation ...................................................................... sb/intel/lynxpoint: Use Broadwell SerialIO implementation Add power state control methods for more devices using helper methods. Change-Id: I96a3b896346f6f1e5aa4a1dc45638cbcff01b7dd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/serialio.asl 1 file changed, 96 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46969/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 845949c..0e246f7 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -16,6 +16,28 @@ External (\S6EN) External (\S7EN) +// Put SerialIO device in D0 state +// Arg0 - Ref to offset 0x84 of device's PCI config space +Method (LPD0, 1, Serialized) +{ + DeRefOf (Arg0) &= 0xFFFFFFFC + Local0 = DeRefOf (Arg0) // Read back after writing + + // Use Local0 to avoid iasl warning: Method Local is set but never used + Local0 &= Ones +} + +// Put SerialIO device in D3 state +// Arg0 - Ref to offset 0x84 of device's PCI config space +Method (LPD3, 1, Serialized) +{ + DeRefOf (Arg0) |= 0x3 + Local0 = DeRefOf (Arg0) // Read back after writing + + // Use Local0 to avoid iasl warning: Method Local is set but never used + Local0 &= Ones +} + // Serial IO Resource Consumption for BAR1 Device (SIOR) { @@ -193,32 +215,20 @@ } } - // Access to PCI Config in ACPI mode - OperationRegion (KEYS, SystemMemory, \S1B1, 0x100) - Field (KEYS, DWordAcc, NoLock, Preserve) + OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) { - Offset (0x84), - PSAT, 32, + SPCS, 32 } - // Put controller in D0 state Method (_PS0, 0, Serialized) { - ^PSAT &= 0xfffffffc - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD0 (RefOf (SPCS)) } - // Put controller in D3Hot state Method (_PS3, 0, Serialized) { - ^PSAT |= 0x00000003 - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD3 (RefOf (SPCS)) } } @@ -273,32 +283,20 @@ } } - // Access to PCI Config in ACPI mode - OperationRegion (KEYS, SystemMemory, \S2B1, 0x100) - Field (KEYS, DWordAcc, NoLock, Preserve) + OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) { - Offset (0x84), - PSAT, 32, + SPCS, 32 } - // Put controller in D0 state Method (_PS0, 0, Serialized) { - ^PSAT &= 0xfffffffc - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD0 (RefOf (SPCS)) } - // Put controller in D3Hot state Method (_PS3, 0, Serialized) { - ^PSAT |= 0x00000003 - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD3 (RefOf (SPCS)) } } @@ -337,6 +335,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (SPI1) @@ -386,6 +400,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (UAR0) @@ -435,6 +465,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (UAR1) @@ -472,6 +518,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (SDIO) -- To view, visit https://review.coreboot.org/c/coreboot/+/46969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96a3b896346f6f1e5aa4a1dc45638cbcff01b7dd Gerrit-Change-Number: 46969 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods
by Angel Pons (Code Review) Feb. 27, 2026

Feb. 27, 2026

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46967 ) Change subject: soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods ...................................................................... soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods Creating named objects within a method is highly inefficient. So, pass a reference to the OperationRegion field that needs to be updated instead. Change-Id: I88272fc5cbe35427ccb5fc50789d47b66ace88fe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 54 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46967/1 diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index b03bcdd..35b15b4 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -6,34 +6,22 @@ #define SIO_BAR_LEN 0x1000 // Put SerialIO device in D0 state -// Arg0 - BAR1 of device +// Arg0 - Ref to offset 0x84 of device's PCI config space Method (LPD0, 1, Serialized) { - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) - Field (SPRT, DWordAcc, NoLock, Preserve) - { - SPCS, 32 - } - - SPCS &= 0xFFFFFFFC - Local0 = SPCS // Read back after writing + DeRefOf (Arg0) &= 0xFFFFFFFC + Local0 = DeRefOf (Arg0) // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used Local0 &= Ones } // Put SerialIO device in D3 state -// Arg0 - BAR1 of device +// Arg0 - Ref to offset 0x84 of device's PCI config space Method (LPD3, 1, Serialized) { - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) - Field (SPRT, DWordAcc, NoLock, Preserve) - { - SPCS, 32 - } - - SPCS |= 0x3 - Local0 = SPCS // Read back after writing + DeRefOf (Arg0) |= 0x3 + Local0 = DeRefOf (Arg0) // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used Local0 &= Ones @@ -226,14 +214,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S1B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S1B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -297,14 +291,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S2B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S2B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -353,14 +353,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S3B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S3B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -421,14 +427,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S4B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S4B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -489,14 +501,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S5B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S5B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -545,14 +563,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S6B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S6B1) + ^^LPD3 (RefOf (SPCS)) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88272fc5cbe35427ccb5fc50789d47b66ace88fe Gerrit-Change-Number: 46967 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/apple: Add MacBook Pro 10,1 (A1398) support
by Evgeny Zinoviev (Code Review) Jan. 17, 2026

Jan. 17, 2026

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32673 Change subject: mb/apple: Add MacBook Pro 10,1 (A1398) support ...................................................................... mb/apple: Add MacBook Pro 10,1 (A1398) support MacBook Pro Retina 15 (Mid 2012) with Ivy Bridge CPU. This is WIP. Not for merging. Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M 3rdparty/vboot A src/mainboard/apple/macbookpro10_1/Kconfig A src/mainboard/apple/macbookpro10_1/Kconfig.name A src/mainboard/apple/macbookpro10_1/Makefile.inc A src/mainboard/apple/macbookpro10_1/acpi/ec.asl A src/mainboard/apple/macbookpro10_1/acpi/platform.asl A src/mainboard/apple/macbookpro10_1/acpi/superio.asl A src/mainboard/apple/macbookpro10_1/acpi_tables.c A src/mainboard/apple/macbookpro10_1/board_info.txt A src/mainboard/apple/macbookpro10_1/devicetree.cb A src/mainboard/apple/macbookpro10_1/dsdt.asl A src/mainboard/apple/macbookpro10_1/gma-mainboard.ads A src/mainboard/apple/macbookpro10_1/gpio.c A src/mainboard/apple/macbookpro10_1/hda_verb.c A src/mainboard/apple/macbookpro10_1/mainboard.c A src/mainboard/apple/macbookpro10_1/romstage.c 16 files changed, 758 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32673/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index e7edff6..304aa42 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit e7edff6653e16ed915c3ad12234d133d1ef4dcc9 +Subproject commit 304aa429c1a04cda3ab2ce37b9e31af84405bfca diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig b/src/mainboard/apple/macbookpro10_1/Kconfig new file mode 100644 index 0000000..603f3ee --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig @@ -0,0 +1,46 @@ +if BOARD_APPLE_MACBOOKPRO10_1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_EDP + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default apple/macbookpro10_1 + +config MAINBOARD_PART_NUMBER + string + default "MacBookPro10,1" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config DRAM_RESET_GATE_GPIO + int + default 28 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig.name b/src/mainboard/apple/macbookpro10_1/Kconfig.name new file mode 100644 index 0000000..c257f7a --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACBOOKPRO10_1 + bool "MacBookPro10,1" diff --git a/src/mainboard/apple/macbookpro10_1/Makefile.inc b/src/mainboard/apple/macbookpro10_1/Makefile.inc new file mode 100644 index 0000000..fd60338 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Makefile.inc @@ -0,0 +1,7 @@ +romstage-y += gpio.c + +cbfs-files-y += spd.bin +spd.bin-file := spd.bin +spd.bin-type := spd + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/apple/macbookpro10_1/acpi/ec.asl b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl new file mode 100644 index 0000000..f70cb3d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/platform.asl b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl new file mode 100644 index 0000000..a17c6ea --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/superio.asl b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl diff --git a/src/mainboard/apple/macbookpro10_1/acpi_tables.c b/src/mainboard/apple/macbookpro10_1/acpi_tables.c new file mode 100644 index 0000000..c48f0bd --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi_tables.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookpro10_1/board_info.txt b/src/mainboard/apple/macbookpro10_1/board_info.txt new file mode 100644 index 0000000..81a5134 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +ROM package: SOIC-8 +ROM socketed: n +Release year: 2012 diff --git a/src/mainboard/apple/macbookpro10_1/devicetree.cb b/src/mainboard/apple/macbookpro10_1/devicetree.cb new file mode 100644 index 0000000..f9e7eb4 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/devicetree.cb @@ -0,0 +1,124 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + #register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0xffffffff" + register "gpu_dp_b_hotplug" = "7" + register "gpu_dp_c_hotplug" = "7" + register "gpu_dp_d_hotplug" = "7" + register "gpu_panel_port_select" = "3" + register "gpu_panel_power_backlight_off_delay" = "8191" + register "gpu_panel_power_backlight_on_delay" = "8191" + register "gpu_panel_power_cycle_delay" = "255" + register "gpu_panel_power_down_delay" = "8191" + register "gpu_panel_power_up_delay" = "8191" + register "gpu_pch_backlight" = "0xffffffff" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x08040201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x8086 0x7270 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x7270 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x8086 0x7270 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x8086 0x7270 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x7270 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x8086 0x7270 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x8086 0x7270 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x8086 0x7270 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x7270 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x7270 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x106b 0x00f7 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x106b 0x00f7 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x106b 0x00f7 + end + device pci 01.2 on + subsystemid 0x106b 0x00f7 + end + device pci 01.1 on + subsystemid 0x106b 0x00f7 + end + end +end diff --git a/src/mainboard/apple/macbookpro10_1/dsdt.asl b/src/mainboard/apple/macbookpro10_1/dsdt.asl new file mode 100644 index 0000000..455ac17 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads new file mode 100644 index 0000000..d4a5d7d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/apple/macbookpro10_1/gpio.c b/src/mainboard/apple/macbookpro10_1/gpio.c new file mode 100644 index 0000000..a445687 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gpio.c @@ -0,0 +1,243 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio11 = GPIO_RESET_RSMRST, + .gpio15 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macbookpro10_1/hda_verb.c b/src/mainboard/apple/macbookpro10_1/hda_verb.c new file mode 100644 index 0000000..b8e4855 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/hda_verb.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b2800, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x106b2800), + + /* NID 0x09. */ + AZALIA_PIN_CFG(0x0, 0x09, 0x002b4020), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x90100112), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x90100110), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x400000f0), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x90a60100), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x004be030), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macbookpro10_1/mainboard.c b/src/mainboard/apple/macbookpro10_1/mainboard.c new file mode 100644 index 0000000..3910541 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/mainboard.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> + +static void mainboard_init(struct device *dev) +{ + +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/apple/macbookpro10_1/romstage.c b/src/mainboard/apple/macbookpro10_1/romstage.c new file mode 100644 index 0000000..c35604b --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/romstage.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <cbfs.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCH_LPC_DEV, 0x82, 0x3f0f); + pci_write_config32(PCH_LPC_DEV, 0x84, 0x000c0681); + pci_write_config32(PCH_LPC_DEV, 0x88, 0x000c1641); + pci_write_config32(PCH_LPC_DEV, 0x8c, 0x001c0301); + pci_write_config32(PCH_LPC_DEV, 0x90, 0x00fc0701); + pci_write_config16(PCH_LPC_DEV, 0x80, 0x0070); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +// FIXME +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + void *spd_file; + size_t spd_file_len = 0; + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (spd_file && spd_file_len >= 128) { + memcpy(&spd[0], spd_file, 128); + memcpy(&spd[2], spd_file, 128); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df Gerrit-Change-Number: 32673 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/variants/dood: Disable XHCI LFPS power management
by Kenneth Chan (Code Review) Nov. 28, 2025

Nov. 28, 2025

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41143 ) Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ...................................................................... mb/google/octopus/variants/dood: Disable XHCI LFPS power management LTE module is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c --- M src/mainboard/google/octopus/variants/dood/overridetree.cb M src/mainboard/google/octopus/variants/dood/variant.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41143/1 diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index 6df9f53..e1f12cf 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -149,4 +149,5 @@ # Disable compliance mode register "DisableComplianceMode" = "1" + register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index e728fe3..ab049a8 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -8,6 +8,7 @@ #include <delay.h> #include <gpio.h> #include <ec/google/chromeec/ec.h> +#include <soc/intel/apollolake/chip.h> enum { SKU_1_LTE = 1, /* Wifi + LTE */ @@ -61,3 +62,21 @@ return; } } + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + + if (cfg != NULL && cfg->disable_xhci_lfps_pm) { + switch (google_chromeec_get_board_sku()) { + case SKU_1_LTE: + case SKU_3_LTE_2CAM: + cfg->disable_xhci_lfps_pm = 1; + return; + default: + return; + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c Gerrit-Change-Number: 41143 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/magolor: Configure I2C high and low time
by Ren Kuo (Code Review) Sept. 17, 2025

Sept. 17, 2025

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46613 ) Change subject: mb/google/dedede/var/magolor: Configure I2C high and low time ...................................................................... mb/google/dedede/var/magolor: Configure I2C high and low time Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:168783630 TEST=Measured the I2C bus frequency reduce to 387 KHz. Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1 --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/46613/1 diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index f41e9fa..625546e 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -25,18 +25,42 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[3] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/46613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1 Gerrit-Change-Number: 46613 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mainboard/emulation/qemu-q35: Do not compile memmap into SMM
by Matt DeVillier (Code Review) Aug. 31, 2025

Aug. 31, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/88995?usp=email ) Change subject: mainboard/emulation/qemu-q35: Do not compile memmap into SMM ...................................................................... mainboard/emulation/qemu-q35: Do not compile memmap into SMM This file contains functions related to PCIe and SMM, and so it's needed by bootblock and ramstage, and possibly romstage. It's not needed by SMM, and in a follow-up, the SMI handler will define `smm_region`, causing a function redefinition error. As this file isn't needed in SMM, and the SMI handler's function will work for this board too, as it works for all silicon (it returns values populated during ramstage, by board/silicon implementations of the function), drop this compilation unit from SMM. Change-Id: I0195e7d42b0669d675879fb4d2596aa4607095b9 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88995 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/emulation/qemu-q35/Makefile.mk 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/emulation/qemu-q35/Makefile.mk b/src/mainboard/emulation/qemu-q35/Makefile.mk index fc85e64..2ad19b9 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.mk +++ b/src/mainboard/emulation/qemu-q35/Makefile.mk @@ -21,5 +21,4 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c smm-y += ../qemu-i440fx/rom_media.c -smm-y += memmap.c smm-y += smihandler.c -- To view, visit https://review.coreboot.org/c/coreboot/+/88995?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0195e7d42b0669d675879fb4d2596aa4607095b9 Gerrit-Change-Number: 88995 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/dedede/var/dexi: Add and use VBT
by Matt DeVillier (Code Review) Aug. 31, 2025

Aug. 31, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/89003?usp=email ) Change subject: mb/google/dedede/var/dexi: Add and use VBT ...................................................................... mb/google/dedede/var/dexi: Add and use VBT Extracted from coreboot-Google_Dexi.13606.639.0.bin TEST=build google/dexi, verify image built with VBT. Change-Id: I7ed620cb4b8a9b42ca97a96df4b5d30196945084 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89003 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/google/dedede/Kconfig A src/mainboard/google/dedede/variants/dexi/data.vbt 2 files changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 2bff7fb..19dd260 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -121,6 +121,7 @@ select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_DIBBI select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 diff --git a/src/mainboard/google/dedede/variants/dexi/data.vbt b/src/mainboard/google/dedede/variants/dexi/data.vbt new file mode 100644 index 0000000..31bf653 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dexi/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/89003?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ed620cb4b8a9b42ca97a96df4b5d30196945084 Gerrit-Change-Number: 89003 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/dedede/var/dita: Add and use VBT
by Matt DeVillier (Code Review) Aug. 31, 2025

Aug. 31, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/89002?usp=email ) Change subject: mb/google/dedede/var/dita: Add and use VBT ...................................................................... mb/google/dedede/var/dita: Add and use VBT Extracted from coreboot-Google_Dita.13606.639.0.bin TEST=build google/dita, verify image built with VBT. Change-Id: Idbc25deeaa011581221019119dbe4923db428850 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89002 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/Kconfig A src/mainboard/google/dedede/variants/dita/data.vbt 2 files changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 2f94fa6..2bff7fb 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -135,6 +135,7 @@ select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_DRAWCIA select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 diff --git a/src/mainboard/google/dedede/variants/dita/data.vbt b/src/mainboard/google/dedede/variants/dita/data.vbt new file mode 100644 index 0000000..31bf653 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dita/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/89002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idbc25deeaa011581221019119dbe4923db428850 Gerrit-Change-Number: 89002 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: util/kconfig: Fix xconfig
by Dmytro (Code Review) Aug. 31, 2025

Aug. 31, 2025

Dmytro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/89006?usp=email ) Change subject: util/kconfig: Fix xconfig ...................................................................... util/kconfig: Fix xconfig The QT based xconfig util is broken for several reasons. 1. On systems with qt6 (which is a majority on modern distros), the qconf-cfg.sh script appends a c++17 flag to the output file, which makes the value of $(HOSTCXXFLAGS_qconf.o) - a multiline string. This causes problem during compiler invocation, thus we can observe: 'g++: fatal error: no input files' Flattening the HOSTCXXFLAGS_ with $strip function resolves the problem 2. The missing Qt's Meta-Object file "qconf-moc.cc", which should be autogenerated during build by invoking "moc" tool. The current set of recipes in Makefile.mk aren't triggering the moc generation. Explicitly adding "qconf-moc.o" target, with dependency on "qconf-moc.cc" resolves the problem. 3. "$(call if_changed,moc)" used to invoke "moc" tool isn't working, due to missing "if_changed" macro. Replace it with direct call to "cmd_moc" in "Makefile.real". Bringing the full implementation of "if_changed" seem to be impractical, as it uses too many dependent functions and macros. BUG=https://ticket.coreboot.org/issues/518 Change-Id: I7eb1e71aeb6a92b8d3c194a369bd3bd6dc708863 Signed-off-by: Dmytro Aleksandrov <alkersan(a)gmail.com> --- M util/kconfig/Makefile.mk 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/89006/1 diff --git a/util/kconfig/Makefile.mk b/util/kconfig/Makefile.mk index 83fad88..4fb8631 100644 --- a/util/kconfig/Makefile.mk +++ b/util/kconfig/Makefile.mk @@ -20,6 +20,7 @@ -e "s,\$$(srctree)/arch/\$$(SRCARCH)/configs/\$$(KBUILD_DEFCONFIG),\$$(KBUILD_DEFCONFIG)," \ -e "s,--defconfig=arch/\$$(SRCARCH)/configs/\$$(KBUILD_DEFCONFIG),--defconfig=\$$(KBUILD_DEFCONFIG)," \ -e "/^unexport CONFIG_$$/d" \ + -e "s/if_changed,moc/cmd_moc/g" \ $< > $@.tmp mv $@.tmp $@ @@ -57,16 +58,16 @@ filechk=$< > $@ $(objk)/%.o: $(srck)/%.c - $(HOSTCC) -I $(srck) -I $(objk) -c $(HOSTCFLAGS_$(notdir $@)) -o $@ $< + $(HOSTCC) -I $(srck) -I $(objk) -c $(strip $(HOSTCFLAGS_$(notdir $@))) -o $@ $< $(objk)/%.o: $(srck)/%.cc - $(HOSTCXX) -I $(srck) -I $(objk) -c $(HOSTCXXFLAGS_$(notdir $@)) -o $@ $< + $(HOSTCXX) -I $(srck) -I $(objk) -c $(strip $(HOSTCXXFLAGS_$(notdir $@))) -o $@ $< $(objk)/%.o: $(objk)/%.c $(HOSTCC) -I $(srck) -I $(objk) -c -o $@ $< -$(objk)/%.moc: $(srck)/%.h | $(objk)/qconf-cfg - $(call cmd_moc) +$(objk)/qconf-moc.o: $(objk)/qconf-moc.cc + $(HOSTCXX) -I $(srck) -I $(objk) -c $(strip $(HOSTCXXFLAGS_$(notdir $@))) -o $@ $< define hostprogs_template # $1 entry in hostprogs -- To view, visit https://review.coreboot.org/c/coreboot/+/89006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7eb1e71aeb6a92b8d3c194a369bd3bd6dc708863 Gerrit-Change-Number: 89006 Gerrit-PatchSet: 1 Gerrit-Owner: Dmytro

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