June 2025 - coreboot-gerrit - mail.coreboot.org

[S] Change in coreboot[main]: soc/mediatek/mt8189: Use pmif_spmi_v2 for MT8189
by Yidi Lin (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Vince Liu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/88244?usp=email ) Change subject: soc/mediatek/mt8189: Use pmif_spmi_v2 for MT8189 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/88244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib3eeba7ca9bd446b641a17fbe97bcda373cb4a24 Gerrit-Change-Number: 88244 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 08:15:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek/pmif_spmi: Move pmif_spmi_force_normal_mode() to common
by Yidi Lin (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Vince Liu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/88243?usp=email ) Change subject: soc/mediatek/pmif_spmi: Move pmif_spmi_force_normal_mode() to common ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/88243?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47c6260872e0922feeab6e849b0ded8d2f7f4eb5 Gerrit-Change-Number: 88243 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 08:14:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/protectli/vault_kbl/romstage.c: remove custom Dq and Dqs maps
by Michał Żygowski (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Andrei Purdea, Paul Menzel. Michał Żygowski has posted comments on this change by Andrei Purdea. ( https://review.coreboot.org/c/coreboot/+/88222?usp=email ) Change subject: mb/protectli/vault_kbl/romstage.c: remove custom Dq and Dqs maps ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/88222/comment/900476f4_cf508eea?us… : PS4, Line 30: This results in the Default Dq : and Dqs maps being used. > ## The short answer is: […] IN hoirt, yes, the DQ/DQS maps are supposed to be provided only for soldered down LPDDR memory, so removing it for slotted RAM board is the way to go. Let's add that to commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/88222?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29977d077f3e7bae4f1eab15246d879c2b929460 Gerrit-Change-Number: 88222 Gerrit-PatchSet: 5 Gerrit-Owner: Andrei Purdea <purdea.andrei(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrei Purdea <purdea.andrei(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 08:12:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Andrei Purdea <purdea.andrei(a)gmail.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8189: Use pmif_spmi_v2 for MT8189
by Yu-Ping Wu (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Vince Liu. Yu-Ping Wu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/88244?usp=email ) Change subject: soc/mediatek/mt8189: Use pmif_spmi_v2 for MT8189 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/88244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib3eeba7ca9bd446b641a17fbe97bcda373cb4a24 Gerrit-Change-Number: 88244 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 07:20:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek/pmif_spmi: Move pmif_spmi_force_normal_mode() to common
by Yu-Ping Wu (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Vince Liu. Yu-Ping Wu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/88243?usp=email ) Change subject: soc/mediatek/pmif_spmi: Move pmif_spmi_force_normal_mode() to common ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/88243?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47c6260872e0922feeab6e849b0ded8d2f7f4eb5 Gerrit-Change-Number: 88243 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 07:19:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: util/qualcomm: Add MBN v7 format support
by Subrata Banik (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Sasirekaa Madhesu, Varadarajan Narayanan, snlakshm snlakshm. Subrata Banik has posted comments on this change by Sasirekaa Madhesu. ( https://review.coreboot.org/c/coreboot/+/88240?usp=email ) Change subject: util/qualcomm: Add MBN v7 format support ...................................................................... Patch Set 1: (1 comment) File util/qualcomm/mbn_tools.py: https://review.coreboot.org/c/coreboot/+/88240/comment/757095b5_20f51d8f?us… : PS1, Line 635: else > MBNv7 header has different versions of Common Metadata and Authority (OEM/QTI) Metadata. The versions here are 0.0 and 2.0 respectively. I want to have a clear distinction between the code for V7 and <V7 so that the header structure getting packed is highlighted distinctively, i.e., without patches inserted (e.g. values.insert(10, self.metadata_size_qti)). > For any new header version, support for the header fields would have to be added by checking the version of the header supported and its fields, version of Common Metadata and its fields and the version of Authority Metadata and its fields. These could vary and need not follow an incremental update. Following YAGNI principle, I think it's okay to leave it as such for now and re-visit the requirements depending on the versions of header/metadata and its fields when required in the future. I understand the difference hence suggesting to keep if case for <7 version so gerrit doesn't show any difference for existing code and start adding > = 7 version checks for else case. That way, in future if any new fields are required to be inserted here, it grows inside else case. If you feel this is the best possible that you could do, I don't have any objection. -- To view, visit https://review.coreboot.org/c/coreboot/+/88240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I484df537ac7d1e51ec86dcae74a74dc211710616 Gerrit-Change-Number: 88240 Gerrit-PatchSet: 1 Gerrit-Owner: Sasirekaa Madhesu <smadhesu(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Varadarajan Narayanan <vnarayan(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: snlakshm snlakshm <snlakshm(a)qualcomm.corp-partner.google.com> Gerrit-CC: Pavan Garimella <garimell(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Varadarajan Narayanan <vnarayan(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Sasirekaa Madhesu <smadhesu(a)qualcomm.corp-partner.google.com> Gerrit-Attention: snlakshm snlakshm <snlakshm(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 07:19:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Pavan Garimella <garimell(a)qualcomm.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/dirks: Update power limits
by David Wu (Code Review) June 29, 2025

June 29, 2025

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/88246?usp=email ) Change subject: mb/google/nissa/var/dirks: Update power limits ...................................................................... mb/google/nissa/var/dirks: Update power limits Update PsysPL2 and PsysPmax values on dirks. BUG=b:399236160 TEST=emerge-nissa coreboot and check PsysPL2 and PsysPmax values on dirks Change-Id: I45f11cccc0c77fcdb73629065f71e1284c36857b Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/dirks/ramstage.c 1 file changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/88246/1 diff --git a/src/mainboard/google/brya/variants/dirks/ramstage.c b/src/mainboard/google/brya/variants/dirks/ramstage.c index d66241f..04f9c6d 100644 --- a/src/mainboard/google/brya/variants/dirks/ramstage.c +++ b/src/mainboard/google/brya/variants/dirks/ramstage.c @@ -1,5 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <baseboard/variants.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/power_limit.h> #include <soc/ramstage.h> void mainboard_silicon_init_params(FSP_S_CONFIG *params) @@ -10,3 +17,49 @@ params->MappingPchXhciUsbA[1] = 2; } + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DID_INTEL_ADL_N_ID_1, 7, 3000, 6000, 25000, 25000, 78000 }, + { PCI_DID_INTEL_ADL_N_ID_2, 6, 3000, 6000, 25000, 25000, 78000 }, + { PCI_DID_INTEL_ADL_N_ID_3, 6, 3000, 6000, 25000, 25000, 78000 }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DID_INTEL_ADL_N_ID_1, 7, 63 }, + { PCI_DID_INTEL_ADL_N_ID_2, 6, 63 }, + { PCI_DID_INTEL_ADL_N_ID_3, 6, 63 }, +}; + +/* + * Psys_pmax considerations. + * + * Given the hardware design in dirks, the serial shunt resistor is 0.01ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 6.009A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v ~= (0.01ohm x 6.009A) x 50 (INA213, gain 50V/V) x PR222/(PR222 + R3193) + * PR222/(PR222 + R3193) = 0.5325 = 36K / (36K + 31.6K) + * + * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping between system input + * current and the actual system power. Since there is no voltage information + * from PSYS, different voltage input would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax should be 15v x 6.009A = 90.135W + * For Type-C 20V, the Psys_pmax should be 20v x 6.009A = 120.18W + * For a barrel jack, the Psys_pmax should be 19v x 6.009A = 114.171W + * + * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, + * and the Psys_pmax setting is 120W. Then IMVP9.1 can calculate the current system + * power = 120W * 5A / 6.009A = 100W, which is the actual system power. + */ +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 6009, + .bj_volts_mv = 19000, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/88246?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45f11cccc0c77fcdb73629065f71e1284c36857b Gerrit-Change-Number: 88246 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/baseboard/nissa: Add power limits functions
by David Wu (Code Review) June 29, 2025

June 29, 2025

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/88245?usp=email ) Change subject: mb/google/nissa/var/baseboard/nissa: Add power limits functions ...................................................................... mb/google/nissa/var/baseboard/nissa: Add power limits functions Support variant specific power limits BUG=b:399236160 TEST=emerge-nissa coreboot and check correct value on dirks. Change-Id: If09a8f4d157c6fd01aabae1e455e289d3908b39b Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c 1 file changed, 86 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/88245/1 diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c b/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c index a45b1eb..ec7c927 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c @@ -3,6 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <device/pci_ops.h> +#include <ec/google/chromeec/ec.h> #include <gpio.h> #include <soc/gpio.h> #include <soc/ramstage.h> @@ -10,6 +11,8 @@ #include <static.h> #include <intelblocks/power_limit.h> +#define SET_PSYSPL2(e, w) ((e) * (w) / 100) + struct soc_power_limits_config *variant_get_soc_power_limit_config(void) { config_t *config = config_of_soc(); @@ -38,6 +41,89 @@ return NULL; } +static bool get_sku_index(const struct cpu_power_limits *limits, size_t num_entries, + size_t *intel_idx, size_t *nissa_idx) +{ + uint16_t mch_id = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + u8 tdp = get_cpu_tdp(); + size_t i = 0; + + for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) { + if (mch_id == cpuid_to_adl[i].cpu_id && tdp == cpuid_to_adl[i].cpu_tdp) { + *intel_idx = cpuid_to_adl[i].limits; + break; + } + } + + if (i == ARRAY_SIZE(cpuid_to_adl)) { + printk(BIOS_ERR, "Cannot find correct intel sku index.\n"); + return false; + } + + for (i = 0; i < num_entries; i++) { + if (mch_id == limits[i].mchid && tdp == limits[i].cpu_tdp) { + *nissa_idx = i; + break; + } + } + + if (i == num_entries) { + printk(BIOS_ERR, "Cannot find correct nissa sku index.\n"); + return false; + } + + return true; +} + +void variant_update_psys_power_limits(const struct cpu_power_limits *limits, + const struct system_power_limits *sys_limits, + size_t num_entries, + const struct psys_config *config_psys) + +{ + struct soc_power_limits_config *soc_config; + size_t intel_idx, nissa_idx; + u16 volts_mv, current_ma; + enum usb_chg_type type; + u32 psyspl2; + config_t *conf; + u32 watts; + int rv; + + if (!num_entries) + return; + + if (!get_sku_index(limits, num_entries, &intel_idx, &nissa_idx)) + return; + + conf = config_of_soc(); + soc_config = &conf->power_limits_config[intel_idx]; + + rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv); + + if (rv == 0 && type == USB_CHG_TYPE_PD) { + /* Detected USB-PD. Base on max value of adapter */ + watts = ((u32)current_ma * volts_mv) / 1000000; + + /* set psyspl2 to 97% of adapter rating */ + psyspl2 = SET_PSYSPL2(config_psys->efficiency, watts); + } else { + /* Input type is barrel jack */ + volts_mv = config_psys->bj_volts_mv; + psyspl2 = sys_limits[nissa_idx].psys_pl2_power; + } + + /* voltage unit is milliVolts and current is in milliAmps */ + soc_config->psys_pmax = (u16)(((u32)config_psys->psys_imax_ma * volts_mv) / 1000000); + conf->platform_pmax = soc_config->psys_pmax; + + soc_config->tdp_psyspl2 = psyspl2; + + printk(BIOS_INFO, "Overriding PsysPL2 (%u) Psys_Pmax (%u)\n", + soc_config->tdp_psyspl2, + soc_config->psys_pmax); +} + void variant_configure_pads(void) { const struct pad_config *base_pads; -- To view, visit https://review.coreboot.org/c/coreboot/+/88245?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If09a8f4d157c6fd01aabae1e455e289d3908b39b Gerrit-Change-Number: 88245 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com>

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[L] Change in coreboot[dev_bd]: payloads/libpayload: Add support for RISC-V 64-bit architecture
by Ziang Wang (Code Review) June 29, 2025

June 29, 2025

Attention is currently required from: Paul Menzel, Ziang Wang. Hello Paul Menzel, weidongwd, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/88187?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by Ziang Wang Change subject: payloads/libpayload: Add support for RISC-V 64-bit architecture ...................................................................... payloads/libpayload: Add support for RISC-V 64-bit architecture This patch adds config ARCH_RISCV_RV64 to support build of riscv64 payloads. New files under arch/riscv contain: - Basic ldscript and payload entry point. - Functions for riscv64 io and cache operations. Besides, drivers/timer/none.c is added to avoid build error when CONFIG_DRIVERS_TIMER_NONE is selected. Change-Id: I5bdfe290837f46aee58aaf997e7845f5cd57404a Signed-off-by: Ziang Wang <wangziang.ok(a)bytedance.com> Signed-off-by: Dong Wei <weidong.wd(a)bytedance.com> --- M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.mk A payloads/libpayload/arch/riscv/Kconfig A payloads/libpayload/arch/riscv/Makefile.mk A payloads/libpayload/arch/riscv/cache.c A payloads/libpayload/arch/riscv/coreboot.c A payloads/libpayload/arch/riscv/head.S A payloads/libpayload/arch/riscv/libpayload.ldscript A payloads/libpayload/arch/riscv/main.c A payloads/libpayload/arch/riscv/sysinfo.c A payloads/libpayload/arch/riscv/timer.c A payloads/libpayload/arch/riscv/util.S A payloads/libpayload/arch/riscv/virtual.c M payloads/libpayload/drivers/Makefile.mk A payloads/libpayload/drivers/timer/none.c A payloads/libpayload/include/riscv/arch/asm.h A payloads/libpayload/include/riscv/arch/cache.h A payloads/libpayload/include/riscv/arch/io.h A payloads/libpayload/include/riscv/arch/types.h A payloads/libpayload/include/riscv/arch/virtual.h 21 files changed, 600 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/88187/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/88187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: dev_bd Gerrit-Change-Id: I5bdfe290837f46aee58aaf997e7845f5cd57404a Gerrit-Change-Number: 88187 Gerrit-PatchSet: 3 Gerrit-Owner: Ziang Wang <wangziang.ok(a)bytedance.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ziang Wang <wangziang.ok(a)bytedance.com> Gerrit-CC: Nill Ge <geshijian(a)bytedance.com> Gerrit-CC: niehaitao(a)bytedance.com Gerrit-CC: weidongwd <weidong.wd(a)bytedance.com> Gerrit-Attention: Ziang Wang <wangziang.ok(a)bytedance.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[dev_bd]: arch/riscv: [Experimental] Pass coreboot table to payloads via OpenSBI
by Ziang Wang (Code Review) June 29, 2025

June 29, 2025

Attention is currently required from: Maximilian Brune, Paul Menzel, Philipp Hug. Ziang Wang has posted comments on this change by Ziang Wang. ( https://review.coreboot.org/c/coreboot/+/88215?usp=email ) Change subject: arch/riscv: [Experimental] Pass coreboot table to payloads via OpenSBI ...................................................................... Patch Set 2: (1 comment) File src/arch/riscv/opensbi.c: https://review.coreboot.org/c/coreboot/+/88215/comment/282a8606_5d5b1bdc?us… : PS1, Line 50: : "r"(hart_id), "r"(fdt), "r"(&info) > Ok then. This patch has become more concise due to your review, thanks! <3 -- To view, visit https://review.coreboot.org/c/coreboot/+/88215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: dev_bd Gerrit-Change-Id: I8cbc085e4b10eb406e85124f252dcde778fd106d Gerrit-Change-Number: 88215 Gerrit-PatchSet: 2 Gerrit-Owner: Ziang Wang <wangziang.ok(a)bytedance.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ziang Wang <wangziang.ok(a)bytedance.com> Gerrit-CC: Nill Ge <geshijian(a)bytedance.com> Gerrit-CC: niehaitao(a)bytedance.com Gerrit-CC: weidongwd <weidong.wd(a)bytedance.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 06:27:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ziang Wang <wangziang.ok(a)bytedance.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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