June 2025 - coreboot-gerrit - mail.coreboot.org

[L] Change in coreboot[main]: [WIP]drivers/amd/ftpm: Add fTPM driver for PSP emulated CRB TPMs
by Patrick Rudolph (Code Review) June 30, 2025

June 30, 2025

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/88247?usp=email ) Change subject: [WIP]drivers/amd/ftpm: Add fTPM driver for PSP emulated CRB TPMs ...................................................................... [WIP]drivers/amd/ftpm: Add fTPM driver for PSP emulated CRB TPMs The AMD fTPM uses the CRB interface, but doesn't implement all registers defined in the TCG specification. Add a new driver that deals with the reduced register set. The driver is intended to work with AMD family 1Ah SoCs only. The TPM interface also assumes that the DRTM is always using locality 0. TODO: Test on real hardware. Change-Id: I780bdab621228e12b37f3a89868e16bc62a05e7b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/acpi/acpi.c A src/drivers/amd/ftpm/Kconfig A src/drivers/amd/ftpm/Makefile.mk A src/drivers/amd/ftpm/chip.h A src/drivers/amd/ftpm/tis.c A src/drivers/amd/ftpm/tpm.c A src/drivers/amd/ftpm/tpm.h M src/security/tpm/tss/tss.c 8 files changed, 515 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/88247/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 84e314c..fd9f461 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -258,7 +258,7 @@ if (tlcl_get_family() != TPM_2) return; - if (CONFIG(CRB_TPM) && !(CONFIG(SPI_TPM) || CONFIG(I2C_TPM) || CONFIG(MEMORY_MAPPED_TPM))) + if ((CONFIG(CRB_TPM) || CONFIG(AMD_CRB_FTPM)) && !(CONFIG(SPI_TPM) || CONFIG(I2C_TPM) || CONFIG(MEMORY_MAPPED_TPM))) if (!crb_tpm_is_active()) return; @@ -279,7 +279,7 @@ /* Hard to detect for coreboot. Just set it to 0 */ tpm2->platform_class = 0; - if (CONFIG(CRB_TPM)) { + if (CONFIG(CRB_TPM) || CONFIG(AMD_CRB_FTPM)) { /* Must be set to 7 for CRB Support */ tpm2->control_area = CONFIG_CRB_TPM_BASE_ADDRESS + 0x40; tpm2->start_method = 7; diff --git a/src/drivers/amd/ftpm/Kconfig b/src/drivers/amd/ftpm/Kconfig new file mode 100644 index 0000000..20d7927 --- /dev/null +++ b/src/drivers/amd/ftpm/Kconfig @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config AMD_CRB_FTPM + bool + default n + depends on !CRB_TPM + depends on SOC_AMD_COMMON_BLOCK_PSP + help + Mainboard has fTPM with Command Response Buffer support diff --git a/src/drivers/amd/ftpm/Makefile.mk b/src/drivers/amd/ftpm/Makefile.mk new file mode 100644 index 0000000..4b7eaf7 --- /dev/null +++ b/src/drivers/amd/ftpm/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_AMD_CRB_FTPM),y) +all-y += tis.c tpm.c +endif diff --git a/src/drivers/amd/ftpm/chip.h b/src/drivers/amd/ftpm/chip.h new file mode 100644 index 0000000..7e69509 --- /dev/null +++ b/src/drivers/amd/ftpm/chip.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DRIVERS_AMD_FTPM_CHIP_H +#define DRIVERS_AMD_FTPM_CHIP_H + +struct drivers_amd_ftpm_config { +}; + +#endif /* DRIVERS_AMD_FTPM_CHIP_H */ diff --git a/src/drivers/amd/ftpm/tis.c b/src/drivers/amd/ftpm/tis.c new file mode 100644 index 0000000..3e23fe7 --- /dev/null +++ b/src/drivers/amd/ftpm/tis.c @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <security/tpm/tis.h> +#include <acpi/acpigen.h> +#include <device/device.h> +#include <drivers/intel/ptt/ptt.h> +#include <drivers/tpm/tpm_ppi.h> +#include <security/tpm/tss.h> +#include <endian.h> +#include <smbios.h> +#include <string.h> + +#include "tpm.h" +#include "chip.h" + +#define ACPI_DSM_START_METHOD_UUID "6bbf6cab-5463-4714-b7cd-f0203c0368d4" + +static const char *tis_get_dev_name(struct crb_tpm_info *info) +{ + return "fTPM"; +} + +static tpm_result_t crb_tpm_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, uint8_t *recvbuf, + size_t *rbuf_len) +{ + int len = crb_tpm_process_command(sendbuf, sbuf_size, recvbuf, *rbuf_len); + + if (len == 0) + return TPM_CB_FAIL; + + *rbuf_len = len; + + return TPM_SUCCESS; +} + +tis_sendrecv_fn crb_tis_probe(enum tpm_family *family) +{ + struct crb_tpm_info info; + + /* Wake TPM up (if necessary) */ + if (crb_tpm_init()) + return NULL; + + /* CRB interface exists only in TPM2 */ + if (family != NULL) + *family = TPM_2; + + crb_tpm_get_info(&info); + + printk(BIOS_INFO, "Initialized TPM device %s revision %d\n", tis_get_dev_name(&info), + info.revision); + + return &crb_tpm_sendrecv; +} + +static void start_method_cb(void *arg) +{ + /* Do nothing. */ +} + +static void (*acpi_start_method_callbacks[])(void *) = { + NULL, /* Enumerate functions (auto-generated) */ + start_method_cb, +}; + +static void crb_tpm_fill_ssdt(const struct device *dev) +{ + /* Device */ + acpigen_write_scope("\\_SB"); + acpigen_write_device(acpi_device_name(dev)); + + acpigen_write_name_string("_HID", "MSFT0101"); + acpigen_write_name_string("_CID", "MSFT0101"); + + acpi_device_write_uid(dev); + + if (crb_tpm_is_active()) + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + else + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_OFF); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpigen_write_mem32fixed(1, dev->path.mmio.addr, 0x30); + acpigen_write_resourcetemplate_footer(); + + if (!CONFIG(CHROMEOS) && CONFIG(TPM_PPI)) + tpm_ppi_acpi_fill_ssdt(dev); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *crb_tpm_acpi_name(const struct device *dev) +{ + return "TPM2"; +} + +#if CONFIG(GENERATE_SMBIOS_TABLES) && CONFIG(TPM2) +static tpm_result_t tpm_get_cap(uint32_t property, uint32_t *value) +{ + TPMS_CAPABILITY_DATA cap_data; + int i; + tpm_result_t rc; + + if (!value) + return TPM_CB_INVALID_ARG; + + rc = tlcl2_get_capability(TPM_CAP_TPM_PROPERTIES, property, 1, &cap_data); + + if (rc) + return rc; + + for (i = 0 ; i < cap_data.data.tpmProperties.count; i++) { + if (cap_data.data.tpmProperties.tpmProperty[i].property == property) { + *value = cap_data.data.tpmProperties.tpmProperty[i].value; + return TPM_SUCCESS; + } + } + + return TPM_CB_FAIL; +} + +static int smbios_write_type43_tpm(struct device *dev, int *handle, unsigned long *current) +{ + struct crb_tpm_info info; + uint32_t tpm_manuf, tpm_family; + uint32_t fw_ver1, fw_ver2; + uint8_t major_spec_ver, minor_spec_ver; + + if (tlcl_get_family() == TPM_1) + return 0; + + crb_tpm_get_info(&info); + + /* If any of these have invalid values, assume TPM not present or disabled */ + if (info.vendor_id == 0 || info.vendor_id == 0xFFFF || + info.device_id == 0 || info.device_id == 0xFFFF) { + printk(BIOS_DEBUG, "%s: Invalid Vendor ID/Device ID\n", __func__); + return 0; + } + + /* Vendor ID is the value returned by TPM2_GetCapabiltiy TPM_PT_MANUFACTURER */ + if (tpm_get_cap(TPM_PT_MANUFACTURER, &tpm_manuf)) { + printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_MANUFACTURER failed\n"); + return 0; + } + + tpm_manuf = be32toh(tpm_manuf); + + if (tpm_get_cap(TPM_PT_FIRMWARE_VERSION_1, &fw_ver1)) { + printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_FIRMWARE_VERSION_1 failed\n"); + return 0; + } + + if (tpm_get_cap(TPM_PT_FIRMWARE_VERSION_2, &fw_ver2)) { + printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_FIRMWARE_VERSION_2 failed\n"); + return 0; + } + + if (tpm_get_cap(TPM_PT_FAMILY_INDICATOR, &tpm_family)) { + printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_FAMILY_INDICATOR failed\n"); + return 0; + } + + tpm_family = be32toh(tpm_family); + + if (!strncmp((char *)&tpm_family, "2.0", 4)) { + major_spec_ver = 2; + minor_spec_ver = 0; + } else { + printk(BIOS_ERR, "%s: Invalid TPM family\n", __func__); + return 0; + } + + return smbios_write_type43(current, handle, tpm_manuf, major_spec_ver, minor_spec_ver, + fw_ver1, fw_ver2, tis_get_dev_name(&info), + SMBIOS_TPM_DEVICE_CHARACTERISTICS_NOT_SUPPORTED, 0); +} +#endif + +static struct device_operations __maybe_unused amd_crb_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = crb_tpm_acpi_name, + .acpi_fill_ssdt = crb_tpm_fill_ssdt, +#endif +#if CONFIG(GENERATE_SMBIOS_TABLES) && CONFIG(TPM2) + .get_smbios_data = smbios_write_type43_tpm, +#endif +}; + +static void enable_dev(struct device *dev) +{ +#if !DEVTREE_EARLY + dev->ops = &amd_crb_ops; +#endif +} + +struct chip_operations drivers_amd_ftpm_ops = { + .name = "AMD CRB fTPM", + .enable_dev = enable_dev +}; diff --git a/src/drivers/amd/ftpm/tpm.c b/src/drivers/amd/ftpm/tpm.c new file mode 100644 index 0000000..68f78ff --- /dev/null +++ b/src/drivers/amd/ftpm/tpm.c @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * This is a driver for the AMD fTPM CRB Interface. + * + * The general flow looks like this: + * + * TPM starts in IDLE Mode + * + * IDLE -------------> Command Reception + * ^ | + * | v + -- Cmd Complete <-- Command Execution + */ + +#include <timer.h> +#include <console/console.h> +#include <device/mmio.h> +#include <string.h> +#include <soc/pci_devs.h> +#include <device/pci_ops.h> +#include <block/psp/psp_def.h> + +#include "tpm.h" + +static struct control_area { + uint32_t start; + uint32_t command_size; + void *command_bfr; + uint32_t response_size; + void *response_bfr; +} control_area; + +/* Read Control Area Structure back */ +static void crb_readControlArea(void) +{ + control_area.command_size = read32(CRB_REG(CRB_REG_CMD_SIZE)); + control_area.command_bfr = + (void *)(uintptr_t)read64(CRB_REG(CRB_REG_CMD_ADDR)); + control_area.response_size = read32(CRB_REG(CRB_REG_RESP_SIZE)); + control_area.response_bfr = + (void *)(uintptr_t)read64(CRB_REG(CRB_REG_RESP_ADDR)); +} + +/* Wait for Reg to be expected Value */ +static tpm_result_t crb_wait_for_reg32(const void *addr, uint32_t timeoutMs, uint32_t mask, + uint32_t expectedValue) +{ + uint32_t regValue; + struct stopwatch sw; + + // Set up a timer which breaks the loop after timeout + stopwatch_init_msecs_expire(&sw, timeoutMs); + + while (1) { + // Now check if the TPM is in IDLE mode + regValue = read32(addr); + + if ((regValue & mask) == expectedValue) + return TPM_SUCCESS; + + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, + "CRB_WAIT: Error - Timed out with RegValue: %08x, Mask: %08x, Expected: %08x\n", + regValue, mask, expectedValue); + return TPM_CB_TIMEOUT; + } + } +} + +/* CRB PROBE + * + * Checks if the CRB Interface is ready + */ +static tpm_result_t crb_probe(void) +{ + if (!crb_tpm_is_active()) + return CB_ERR_NOT_IMPLEMENTED; + return CB_SUCCESS; +} + +/* + * crb_tpm_init + * + * Even though the TPM does not need an initialization we check + * if the TPM responds and is in IDLE mode, which should be the + * normal bring up mode. + * + */ +tpm_result_t crb_tpm_init(void) +{ + tpm_result_t rc = crb_probe(); + if (rc) { + printk(BIOS_ERR, "fTPM: Probe failed.\n"); + return rc; + } + + /* Read back control area structure */ + crb_readControlArea(); + + /* Good to go. */ + printk(BIOS_SPEW, "fTPM: CRB TPM initialized successfully\n"); + + return TPM_SUCCESS; +} + +/* + * crb_tpm_process_command + */ +size_t crb_tpm_process_command(const void *tpm2_command, size_t command_size, + void *tpm2_response, size_t max_response) +{ + tpm_result_t rc; + + if (command_size > control_area.command_size) { + printk(BIOS_ERR, "fTPM: Command size is too big.\n"); + return -1; + } + + if (control_area.response_size < max_response) { + printk(BIOS_ERR, "fTPM: Response size could be too big.\n"); + return -1; + } + + // Check if CMD bit is cleared. + rc = crb_wait_for_reg32(CRB_REG(CRB_REG_START), 250, CRB_REG_START_START, 0x0); + if (rc) { + printk(BIOS_ERR, "fTPM Error (%#x): Cmd Bit not cleared.\n", rc); + return -1; + } + + // Write to Command Buffer + memcpy(control_area.command_bfr, tpm2_command, command_size); + + // Clear Response buffer + memset(control_area.response_bfr, 0, max_response); + + // Register CRB_REG_RESP_SIZE will be updated by fTPM + write32(CRB_REG(CRB_REG_RESP_SIZE), control_area.response_size); + + // Write Start Bit + write8(CRB_REG(CRB_REG_START), 0x1); + + // Poll for Response + rc = crb_wait_for_reg32(CRB_REG(CRB_REG_START), 3500, CRB_REG_START_START, 0); + if (rc) { + printk(BIOS_DEBUG, "fTPM Error (%#x): Command Timed out.\n", rc); + return -1; + } + + // Check for errors + rc = crb_wait_for_reg32(CRB_REG(CRB_REG_STATUS), 200, CRB_REG_STATUS_ERROR, 0); + if (rc) { + printk(BIOS_DEBUG, "fTPM Error (%#x): Command errored.\n", rc); + return -1; + } + + // Get Response Length + uint32_t length = read32(CRB_REG(CRB_REG_RESP_SIZE)); + + /* Response has to have at least 6 bytes */ + if (length < 6 || length > max_response) + return 1; + + // Copy Response + memcpy(tpm2_response, control_area.response_bfr, length); + + return length; +} + +/* + * tp2_get_info + * + * Returns information about the TPM + * + */ +void crb_tpm_get_info(struct crb_tpm_info *crb_tpm_info) +{ + /* Register CRB_REG_INTF_ID isn't supported. Use AMD HSP device ID. */ + crb_tpm_info->vendor_id = 0x1022; + crb_tpm_info->device_id = 0x163E; + crb_tpm_info->revision = 0; +} + +/* + * crb_tpm_is_active + * + * Checks that CRB interface is available and active. + * + */ +bool crb_tpm_is_active(void) +{ + // Register CRB_REG_INTF_ID is not supported + uint32_t caps = 0; + + // PSP must report fTPM support + if (psp_get_ftpm_capabilties(&caps) != CB_SUCCESS) + return false; + + if (!(caps & MBOX_FTPM_CAP_TPM_SUPPORTED)) + return false; + + // DRTM is always in locality 0 + const uint8_t loc_state = read8(CRB_REG(CRB_REG_LOC_STATE)); + const uint8_t locality = (loc_state >> 2) & 0x07; + const uint8_t locality_enabled = (loc_state >> 1) & 1; + + if (locality != 0 || !locality_enabled) + return false; + + return true; +} diff --git a/src/drivers/amd/ftpm/tpm.h b/src/drivers/amd/ftpm/tpm.h new file mode 100644 index 0000000..81d2fdc --- /dev/null +++ b/src/drivers/amd/ftpm/tpm.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This is a driver for a Command Response Buffer Interface */ + +#include <security/tpm/tis.h> +#include <security/tpm/tss_errors.h> + +/* CRB driver */ +/* address of locality 0 (CRB) */ +#define TPM_CRB_BASE_ADDRESS CONFIG_CRB_TPM_BASE_ADDRESS + +#define CRB_REG(REG) \ + (void *)(uintptr_t)(CONFIG_CRB_TPM_BASE_ADDRESS + REG) + +/* hardware registers */ + +#define CRB_REG_LOC_STATE 0x00 /* Readonly */ +//#define CRB_REG_LOC_CTRL 0x08 +//#define CRB_REG_LOC_STS 0x0C + +/* LOC_CTRL BIT MASKS */ +//#define LOC_CTRL_REQ_ACCESS 0x01 + +/* LOC STATE BIT MASKS */ +//#define LOC_STATE_LOC_ASSIGN 0x02 +//#define LOC_STATE_REG_VALID_STS 0x80 + +/* LOC STS BIT MASKS */ +//#define LOC_STS_GRANTED 0x01 + +//#define CRB_REG_INTF_ID 0x30 + +//#define CRB_REG_REQUEST 0x40 +#define CRB_REG_STATUS 0x44 +//#define CRB_REG_CANCEL 0x48 +#define CRB_REG_START 0x4C +//#define CRB_REG_INT_CTRL 0x50 +#define CRB_REG_CMD_SIZE 0x58 +#define CRB_REG_CMD_ADDR 0x5C +#define CRB_REG_RESP_SIZE 0x64 +#define CRB_REG_RESP_ADDR 0x68 +//#define CRB_REG_DATA_BUFF 0x80 + +/* CRB INTF BIT MASK */ +//#define CRB_INTF_REG_CAP_CRB (1<<14) +//#define CRB_INTF_REG_INTF_SEL (1<<17) +//#define CRB_INTF_REG_INTF_LOCK (1<<19) + +/*REQUEST Register related */ +//#define CRB_REG_REQUEST_CMD_RDY 0x01 +//#define CRB_REG_REQUEST_GO_IDLE 0x02 + +/* STATUS Register related */ +#define CRB_REG_STATUS_ERROR 0x01 +//#define CRB_REG_STATUS_IDLE 0x02 + +/* START Register related */ +#define CRB_REG_START_START 0x01 + +/* CRB TPM Info Struct */ +struct crb_tpm_info { + uint16_t vendor_id; + uint16_t device_id; + uint16_t revision; +}; + +tpm_result_t crb_tpm_init(void); +void crb_tpm_get_info(struct crb_tpm_info *crb_tpm_info); +size_t crb_tpm_process_command(const void *tpm2_command, size_t command_size, + void *tpm2_response, size_t max_response); +bool crb_tpm_is_active(void); + +tis_sendrecv_fn crb_tis_probe(enum tpm_family *family); diff --git a/src/security/tpm/tss/tss.c b/src/security/tpm/tss/tss.c index 8e52de7..f4deb2d 100644 --- a/src/security/tpm/tss/tss.c +++ b/src/security/tpm/tss/tss.c @@ -29,7 +29,7 @@ init_done = true; tlcl_tis_sendrecv = NULL; - if (CONFIG(CRB_TPM)) + if (CONFIG(CRB_TPM) || CONFIG(AMD_CRB_FTPM)) tlcl_tis_sendrecv = crb_tis_probe(&tlcl_tpm_family); if (CONFIG(MEMORY_MAPPED_TPM) && tlcl_tis_sendrecv == NULL) tlcl_tis_sendrecv = pc80_tis_probe(&tlcl_tpm_family); -- To view, visit https://review.coreboot.org/c/coreboot/+/88247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I780bdab621228e12b37f3a89868e16bc62a05e7b Gerrit-Change-Number: 88247 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[M] Change in coreboot[main]: util/qualcomm: Add MBN v7 format support
by Sasirekaa Madhesu (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Subrata Banik, Varadarajan Narayanan, snlakshm snlakshm. Sasirekaa Madhesu has posted comments on this change by Sasirekaa Madhesu. ( https://review.coreboot.org/c/coreboot/+/88240?usp=email ) Change subject: util/qualcomm: Add MBN v7 format support ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: > Can you help me understand how various tooling is used in current Qualcomm SoCs? […] Yes, the image format of Bootblock ELF for Qualcomm 7c and 8x are different. On Qualcomm 7c, the QC_SEC and bootblock binaries are packed as segments of an ELF image (using createxbl.py) which is then converted to MBN v6 format ( using mbn_tools.py). For Qualcomm 8x, since we need the image in multi ELF format, we make use of create_multielf.py to concatenate the ELF images to melf image. As you said, createxbl.py would be invoked separately to generate the bootblock MBN image and then the create_multielf.py would be used to append the 4 images ( TME SEQ + TME FW + QC_SEC + BOOTBLOCK) Commit Message: https://review.coreboot.org/c/coreboot/+/88240/comment/69a5ec60_423d6e82?us… : PS1, Line 12: > It would be super helpful if you could also share the link or a document where I can find more infor […] Document update with MBN v7 format details is yet to be done. The document update is tracked as part of Bug ID: 404985109 -- To view, visit https://review.coreboot.org/c/coreboot/+/88240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I484df537ac7d1e51ec86dcae74a74dc211710616 Gerrit-Change-Number: 88240 Gerrit-PatchSet: 1 Gerrit-Owner: Sasirekaa Madhesu <smadhesu(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Varadarajan Narayanan <vnarayan(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: snlakshm snlakshm <snlakshm(a)qualcomm.corp-partner.google.com> Gerrit-CC: Pavan Garimella <garimell(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Varadarajan Narayanan <vnarayan(a)qualcomm.corp-partner.google.com> Gerrit-Attention: snlakshm snlakshm <snlakshm(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 10:32:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/qc/x1p42100: Support to generate Bootblock as multi ELF
by Sasirekaa Madhesu (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Kapil Porwal, Subrata Banik. Sasirekaa Madhesu has posted comments on this change by Sasirekaa Madhesu. ( https://review.coreboot.org/c/coreboot/+/88241?usp=email ) Change subject: soc/qc/x1p42100: Support to generate Bootblock as multi ELF ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/88241/comment/ac92d75a_ab5a1658?us… : PS1, Line 16: Test=Generate image.serial.bin and verify bootup on X1P42100 > TEST Done File src/soc/qualcomm/x1p42100/Makefile.mk: https://review.coreboot.org/c/coreboot/+/88241/comment/3c50ec23_cc67c6cc?us… : PS1, Line 81: -d 64 > This looks redundant now. yes,"-d" option is not required for x1p42100. Removed it https://review.coreboot.org/c/coreboot/+/88241/comment/9ae14915_89b89fe8?us… : PS1, Line 83: mbn > Can call it melf for clarity? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/88241?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc499221d8806b549f6c873a14382a28c3efb74f Gerrit-Change-Number: 88241 Gerrit-PatchSet: 2 Gerrit-Owner: Sasirekaa Madhesu <smadhesu(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 09:26:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[S] Change in coreboot[main]: soc/qc/x1p42100: Support to generate Bootblock as multi ELF
by Sasirekaa Madhesu (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Sasirekaa Madhesu, Subrata Banik. Hello Kapil Porwal, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/88241?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: soc/qc/x1p42100: Support to generate Bootblock as multi ELF ...................................................................... soc/qc/x1p42100: Support to generate Bootblock as multi ELF This commit performs below to create Bootblock binary. 1. createxbl.py: Converts "bootblock.raw.elf" to MBN (v7 format). 2. create_multielf.py: Concatenates TME SEQ, TME FW, QC_SEC and bootblock into multi ELF binary. BUG=b:415949107 TEST=Generate image.serial.bin and verify bootup on X1P42100 Change-Id: Icc499221d8806b549f6c873a14382a28c3efb74f Signed-off-by: smadhesu <smadhesu(a)qualcomm.corp-partner.google.com> Signed-off-by: Sasirekaa Madhesu <smadhesu(a)qualcomm.corp-partner.google.com> --- M src/soc/qualcomm/x1p42100/Makefile.mk M util/qualcomm/create_multielf.py 2 files changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/88241/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/88241?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc499221d8806b549f6c873a14382a28c3efb74f Gerrit-Change-Number: 88241 Gerrit-PatchSet: 2 Gerrit-Owner: Sasirekaa Madhesu <smadhesu(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sasirekaa Madhesu <smadhesu(a)qualcomm.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/ocelot: Update EC host command range for variants
by Usha P (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Appukuttan Vk, Avi Uday, Nick Vaccaro, Nick Vaccaro, Paul Menzel, Pranava Y N. Usha P has posted comments on this change by Usha P. ( https://review.coreboot.org/c/coreboot/+/88179?usp=email ) Change subject: mb/google/ocelot: Update EC host command range for variants ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/88179/comment/d2cde594_9857dc6e?us… : PS4, Line 14: BOARD_GOOGLE_OCELOTMCHP > We also have BOARD_GOOGLE_OCELOTMCHP4ES. Acknowledged https://review.coreboot.org/c/coreboot/+/88179/comment/a7fd7d2c_b6341787?us… : PS4, Line 15: BOARD_GOOGLE_OCELOT and BOARD_GOOGLE_OCELOTITE > I don't see this change in this CL. […] Acknowledged File src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb: https://review.coreboot.org/c/coreboot/+/88179/comment/a6288b88_de7d4ed3?us… : PS4, Line 11: BOARD_GOOGLE_OCELOTMCHP > CONFIG(BOARD_GOOGLE_OCELOTMCHP) || CONFIG(BOARD_GOOGLE_OCELOTMCHP4ES) […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/88179?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If08f2362a7b3bafca69375ce3b346f75435a83df Gerrit-Change-Number: 88179 Gerrit-PatchSet: 6 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Appukuttan Vk <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Appukuttan Vk <appukuttan.vk(a)intel.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 09:00:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com>

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[XS] Change in coreboot[main]: mb/google/ocelot: Update EC host command range for variants
by Usha P (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Appukuttan Vk, Avi Uday, Nick Vaccaro, Paul Menzel, Pranava Y N, Usha P. Hello Appukuttan Vk, Avi Uday, Nick Vaccaro, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/88179?usp=email to look at the new patch set (#6). Change subject: mb/google/ocelot: Update EC host command range for variants ...................................................................... mb/google/ocelot: Update EC host command range for variants This patch updates the EC host command range configuration for Ocelot board variants, ensuring that each variant uses the correct range based on its specific EC. BOARD_GOOGLE_OCELOTMCHP and BOARD_GOOGLE_OCELOTMCHP4ES uses Microchip EC. BOARD_GOOGLE_OCELOT and BOARD_GOOGLE_OCELOT4ES uses Nuvoton EC. BOARD_GOOGLE_OCELOTITE and BOARD_GOOGLE_OCELOTITE4ES uses ITE EC. Key changes: - Microchip EC: Configured to use host command ranges 0x800-0x807 and 0x200-0x20f. The register is set to 0x00040801 to accommodate these constraints. BUG=b:394208231 TEST=Build Ocelot and verify it compiles without any error. Change-Id: If08f2362a7b3bafca69375ce3b346f75435a83df Signed-off-by: P, Usha <usha.p(a)intel.com> --- M src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/88179/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/88179?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If08f2362a7b3bafca69375ce3b346f75435a83df Gerrit-Change-Number: 88179 Gerrit-PatchSet: 6 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Appukuttan Vk <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Appukuttan Vk <appukuttan.vk(a)intel.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in blobs[main]: mb/emulation/qemu-riscv: Add OpenSBI image with cbtable support
by Ziang Wang (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: weidongwd. Ziang Wang has posted comments on this change by Ziang Wang. ( https://review.coreboot.org/c/blobs/+/88214?usp=email ) Change subject: mb/emulation/qemu-riscv: Add OpenSBI image with cbtable support ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hi Felix, sorry to loop you in this thread. We are trying to upload some customized OpenSBI images, which will be used in riscv emulation upstream project. Yet we are not sure who to invite to take care of our "Verified" status, or is it possible to apply for that +1 Verified right. Could you provide any guideline by any chance? Thanks! -- To view, visit https://review.coreboot.org/c/blobs/+/88214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I445a2d3654f3091d539492f608dc72ccfb572559 Gerrit-Change-Number: 88214 Gerrit-PatchSet: 2 Gerrit-Owner: Ziang Wang <wangziang.ok(a)bytedance.com> Gerrit-Reviewer: weidongwd <weidong.wd(a)bytedance.com> Gerrit-CC: Nill Ge <geshijian(a)bytedance.com> Gerrit-CC: niehaitao(a)bytedance.com Gerrit-Attention: weidongwd <weidong.wd(a)bytedance.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 08:51:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/ocelot: Update EC host command range for variants
by Usha P (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Appukuttan Vk, Avi Uday, Nick Vaccaro, Paul Menzel, Pranava Y N, Usha P. Hello Appukuttan Vk, Avi Uday, Nick Vaccaro, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/88179?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+1 by Appukuttan Vk, Verified+1 by build bot (Jenkins) Change subject: mb/google/ocelot: Update EC host command range for variants ...................................................................... mb/google/ocelot: Update EC host command range for variants This patch updates the EC host command range configuration for Ocelot board variants, ensuring that each variant uses the correct range based on its specific EC. BOARD_GOOGLE_OCELOTMCHP and BOARD_GOOGLE_OCELOTMCHP4ES uses Microchip EC. BOARD_GOOGLE_OCELOT and BOARD_GOOGLE_OCELOT4ES uses Nuvoton EC. BOARD_GOOGLE_OCELOTITE and BOARD_GOOGLE_OCELOTITE4ES uses ITE EC. Key changes: - Microchip EC: Configured to use host command ranges 0x800-0x807 and 0x200-0x20f. The register is set to 0x00040801 to accommodate these constraints. - ITE/Nuvoton EC: Configured to use host command ranges 0x800-0x8ff and 0x200-0x20f. The register is set to 0x00fc0801 to match these requirements. BUG=b:394208231 TEST=Build Ocelot and verify it compiles without any error. Change-Id: If08f2362a7b3bafca69375ce3b346f75435a83df Signed-off-by: P, Usha <usha.p(a)intel.com> --- M src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/88179/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/88179?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If08f2362a7b3bafca69375ce3b346f75435a83df Gerrit-Change-Number: 88179 Gerrit-PatchSet: 5 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Appukuttan Vk <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Appukuttan Vk <appukuttan.vk(a)intel.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/protectli/vault_kbl/devicetree: Lower the throttling temp to 75C
by Michał Żygowski (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Andrei Purdea, Paul Menzel. Michał Żygowski has posted comments on this change by Andrei Purdea. ( https://review.coreboot.org/c/coreboot/+/88224?usp=email ) Change subject: mb/protectli/vault_kbl/devicetree: Lower the throttling temp to 75C ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/88224/comment/bd3fe598_4f11eff0?us… : PS4, Line 8: > I can say the following: […] 95 °C is wowrking too. The throttling temperature was a customer request. -- To view, visit https://review.coreboot.org/c/coreboot/+/88224?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied84c2494e33ee3f800d0633404f5f879899bc51 Gerrit-Change-Number: 88224 Gerrit-PatchSet: 5 Gerrit-Owner: Andrei Purdea <purdea.andrei(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrei Purdea <purdea.andrei(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 08:16:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Andrei Purdea <purdea.andrei(a)gmail.com>

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[M] Change in coreboot[main]: mb/protectli/vault_kbl: Adding Yanling YL -KBR6L board as FW6D/FW6E v...
by Michał Żygowski (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Andrei Purdea. Michał Żygowski has posted comments on this change by Andrei Purdea. ( https://review.coreboot.org/c/coreboot/+/88223?usp=email ) Change subject: mb/protectli/vault_kbl: Adding Yanling YL -KBR6L board as FW6D/FW6E variant ...................................................................... Patch Set 5: (2 comments) Patchset: PS4: > Thank you for your time to upstream these changes. […] Thank you too Purdea Anderi. File src/mainboard/protectli/vault_kbl/Kconfig: https://review.coreboot.org/c/coreboot/+/88223/comment/1110b63d_d6192534?us… : PS4, Line 15: select SUPERIO_ITE_IT8613E > Why is this necessary/correct? The first board revisions shipped with IT8772F, but later the chip was replaced with IT8613E. THe Latter one is used consistently across all FW6 varianta (A/B/C/D/E). -- To view, visit https://review.coreboot.org/c/coreboot/+/88223?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07026f501d7150b2ebfb26abd1f1a094cc304f01 Gerrit-Change-Number: 88223 Gerrit-PatchSet: 5 Gerrit-Owner: Andrei Purdea <purdea.andrei(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrei Purdea <purdea.andrei(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 08:15:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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