June 2025 - coreboot-gerrit - mail.coreboot.org

[S] Change in coreboot[main]: self_test/intel_cpu: Add test to verify the status of sample part
by Kanika Punia (Code Review) June 30, 2025

June 30, 2025

Kanika Punia has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/88250?usp=email ) Change subject: self_test/intel_cpu: Add test to verify the status of sample part ...................................................................... self_test/intel_cpu: Add test to verify the status of sample part Add a test to verify the sample part status, ensuring the system is not using a CPU pre-production (sample) part. This test confirms that Bit 27 (SAMPLE_PART) in MSR 0xCE (IA32_PLATFORM_INFO) is 0. BUG=b:424030800 TEST=Able to build and execute the test. output log: Starting st_intel_sample_part [DEBUG] Test: Is Sample part verified? [DEBUG] SAMPLE_PART: Bit 27 is 0 in MSR (0xce). [INFO ] Selftest: Intel_sample_part (0x2), Result: PASSED Change-Id: Ifab486642365afc7fa5c3a0d7a87c71b9df11830 Signed-off-by: kanikapunia <kanikapunia(a)google.com> --- M src/commonlib/include/commonlib/self_test_id.h M src/drivers/self_test/modules/intel_cpu/Kconfig M src/drivers/self_test/modules/intel_cpu/Makefile.mk M src/drivers/self_test/modules/intel_cpu/st_intel_cpu.c M src/drivers/self_test/modules/intel_cpu/st_intel_cpu.h A src/drivers/self_test/modules/intel_cpu/st_intel_cpu_sample_part.c 6 files changed, 42 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/88250/1 diff --git a/src/commonlib/include/commonlib/self_test_id.h b/src/commonlib/include/commonlib/self_test_id.h index d243e86..e9626f6 100644 --- a/src/commonlib/include/commonlib/self_test_id.h +++ b/src/commonlib/include/commonlib/self_test_id.h @@ -5,11 +5,13 @@ enum st_id { ST_INVALID_ID, - ST_CPU_INTEL_MICROCODE + ST_CPU_INTEL_MICROCODE, + ST_CPU_INTEL_SAMPLE_PART }; #define ST_ID_TO_NAME_TABLE \ {ST_INVALID_ID, "Invalid Test"},\ - {ST_CPU_INTEL_MICROCODE, "Intel_microcode_patch_loaded"} + {ST_CPU_INTEL_MICROCODE, "Intel_microcode_patch_loaded"},\ + {ST_CPU_INTEL_SAMPLE_PART, "Intel_sample_part"} #endif /* _SELF_TEST_ID_H_ */ diff --git a/src/drivers/self_test/modules/intel_cpu/Kconfig b/src/drivers/self_test/modules/intel_cpu/Kconfig index c6fb71f..175f4b7 100644 --- a/src/drivers/self_test/modules/intel_cpu/Kconfig +++ b/src/drivers/self_test/modules/intel_cpu/Kconfig @@ -13,3 +13,10 @@ depends on SELF_TEST_INTEL_CPU && SOC_INTEL_COMMON_BLOCK_CPU_MPINIT help Self test to validate uCode patch status on Intel CPU. + +config SELF_TEST_INTEL_SAMPLE_PART + bool + default y + depends on SELF_TEST_INTEL_CPU && SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + help + Self test to validate sample part status on Intel CPU. diff --git a/src/drivers/self_test/modules/intel_cpu/Makefile.mk b/src/drivers/self_test/modules/intel_cpu/Makefile.mk index 7a4a2ed..3b23ef7 100644 --- a/src/drivers/self_test/modules/intel_cpu/Makefile.mk +++ b/src/drivers/self_test/modules/intel_cpu/Makefile.mk @@ -2,3 +2,4 @@ ramstage-$(CONFIG_SELF_TEST_INTEL_CPU) += st_intel_cpu.c ramstage-$(CONFIG_SELF_TEST_INTEL_CPU) += st_intel_cpu_common.c ramstage-$(CONFIG_SELF_TEST_INTEL_CPU_UCODE) += st_intel_cpu_ucode.c +ramstage-$(CONFIG_SELF_TEST_INTEL_SAMPLE_PART) += st_intel_cpu_sample_part.c diff --git a/src/drivers/self_test/modules/intel_cpu/st_intel_cpu.c b/src/drivers/self_test/modules/intel_cpu/st_intel_cpu.c index 58a49b3..137c74a 100644 --- a/src/drivers/self_test/modules/intel_cpu/st_intel_cpu.c +++ b/src/drivers/self_test/modules/intel_cpu/st_intel_cpu.c @@ -10,6 +10,9 @@ #if CONFIG(SELF_TEST_INTEL_CPU_UCODE) {.id = ST_CPU_INTEL_MICROCODE, .exec = st_intel_microcode, .state = BS_PAYLOAD_LOAD, .when = BS_ON_EXIT}, #endif +#if CONFIG(SELF_TEST_INTEL_SAMPLE_PART) + {.id = ST_CPU_INTEL_SAMPLE_PART, .exec = st_intel_sample_part, .state = BS_POST_DEVICE, .when = BS_ON_ENTRY}, +#endif {.id = ST_INVALID_ID, } /* Terminator */ }; diff --git a/src/drivers/self_test/modules/intel_cpu/st_intel_cpu.h b/src/drivers/self_test/modules/intel_cpu/st_intel_cpu.h index 31a6cf3..6f014c8 100644 --- a/src/drivers/self_test/modules/intel_cpu/st_intel_cpu.h +++ b/src/drivers/self_test/modules/intel_cpu/st_intel_cpu.h @@ -4,5 +4,6 @@ #define _ST_INTEL_CPU_H_ st_status st_intel_microcode(void); +st_status st_intel_sample_part(void); #endif /* _ST_INTEL_CPU_H_ */ diff --git a/src/drivers/self_test/modules/intel_cpu/st_intel_cpu_sample_part.c b/src/drivers/self_test/modules/intel_cpu/st_intel_cpu_sample_part.c new file mode 100644 index 0000000..d71c1b9 --- /dev/null +++ b/src/drivers/self_test/modules/intel_cpu/st_intel_cpu_sample_part.c @@ -0,0 +1,26 @@ +#include <bootstate.h> +#include <console/console.h> +#include <self_test.h> + +#include "st_intel_cpu.h" +#include "st_intel_cpu_common.h" + +static msr_t msr; + +#define IA32_PLATFORM_INFO 0xCE +#define SAMPLE_PART_BIT 27 + +st_status st_intel_sample_part(void){ + st_debug("Starting %s\n", __func__); + st_debug("Test: Is Sample part verified?\n"); + + msr = rdmsr(IA32_PLATFORM_INFO); + + // Check Lock Bit (Bit 0) + if ((msr.lo & SAMPLE_PART_BIT) == 0) { + st_debug("SAMPLE_PART: Bit 27 is 0 in MSR (0x%x).\n", IA32_PLATFORM_INFO); + return ST_PASSED; + } + return ST_FAILED; + +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/88250?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab486642365afc7fa5c3a0d7a87c71b9df11830 Gerrit-Change-Number: 88250 Gerrit-PatchSet: 1 Gerrit-Owner: Kanika Punia <kanikapunia(a)google.com>

1 0

[M] Change in coreboot[main]: tree: Replace scan-build by clang-tidy
by Elyes Haouas (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Elyes Haouas, Martin L Roth. Hello Julius Werner, Martin L Roth, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87908?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Code-Review+2 by Martin L Roth, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: tree: Replace scan-build by clang-tidy ...................................................................... tree: Replace scan-build by clang-tidy Change-Id: I0e59a1667759723bbf8d76232e7e5375837d2e9a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.mk M payloads/libpayload/Makefile M src/arch/riscv/Makefile.mk M toolchain.mk M util/abuild/abuild M util/cbfstool/lz4/Makefile M util/crossgcc/buildgcc M util/testing/Makefile.mk 8 files changed, 71 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/87908/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/87908?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e59a1667759723bbf8d76232e7e5375837d2e9a Gerrit-Change-Number: 87908 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[L] Change in coreboot[main]: [WIP]drivers/amd/ftpm: Add fTPM driver for PSP emulated CRB TPMs
by Patrick Rudolph (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Christian Walter, Cliff Huang, Lance Zhao, Patrick Rudolph, Tim Wawrzynczak. Hello Christian Walter, Cliff Huang, Lance Zhao, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/88247?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: [WIP]drivers/amd/ftpm: Add fTPM driver for PSP emulated CRB TPMs ...................................................................... [WIP]drivers/amd/ftpm: Add fTPM driver for PSP emulated CRB TPMs The AMD fTPM uses the CRB interface, but doesn't implement all registers defined in the TCG specification. Add a new driver that deals with the reduced register set. The driver is intended to work with AMD family 1Ah SoCs only. The TPM interface also assumes that the DRTM is always using locality 0. TODO: Test on real hardware. Change-Id: I780bdab621228e12b37f3a89868e16bc62a05e7b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/acpi/acpi.c A src/drivers/amd/ftpm/Kconfig A src/drivers/amd/ftpm/Makefile.mk A src/drivers/amd/ftpm/chip.h A src/drivers/amd/ftpm/tis.c A src/drivers/amd/ftpm/tpm.c A src/drivers/amd/ftpm/tpm.h M src/security/tpm/tss/tss.c 8 files changed, 497 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/88247/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/88247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I780bdab621228e12b37f3a89868e16bc62a05e7b Gerrit-Change-Number: 88247 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com>

1 0

[L] Change in coreboot[main]: mb/google/ocelot/var/ocelot: Add FW_CONFIG for devices
by Avi Uday (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Appukuttan Vk, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Pranava Y N, Sowmya Aralguppe, Subrata Banik, Usha P, Varun Upadhyay. Avi Uday has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/88173?usp=email ) Change subject: mb/google/ocelot/var/ocelot: Add FW_CONFIG for devices ...................................................................... Patch Set 8: (3 comments) File src/mainboard/google/ocelot/variants/ocelot/fw_config.c: https://review.coreboot.org/c/coreboot/+/88173/comment/124aeaf4_88b77816?us… : PS8, Line 103: 1 Why is this not a low signal for disable, similar to PTL? https://review.coreboot.org/c/coreboot/+/88173/comment/1c704aec_bebf37df?us… : PS8, Line 118: 1 Is the high signal intentional, to have it different from PTL? https://review.coreboot.org/c/coreboot/+/88173/comment/f51f3ffe_12fb1ea1?us… : PS8, Line 337: static const struct pad_config ish_disable_pads[] = { : /* GPP_B05: C_EC_ISH_ALRT */ : PAD_NC(GPP_B05, NONE), : /* GPP_B07: SLATEMODE_HALLOUT_SNSR_R */ : PAD_NC(GPP_B07, NONE), : /* GPP_B22: ISH_GP_5_SNSR_HDR */ : PAD_NC(GPP_B22, NONE), : /* GPP_B23: ISH_GP_6_SNSR_HDR */ : PAD_NC(GPP_B23, NONE), : /* GPP_D05: ISH_UART0_ECAIC_RXD */ : PAD_NC(GPP_D05, NONE), : /* GPP_D06: ISH_UART0_ECAIC_TXD */ : PAD_NC(GPP_D06, NONE), : }; Shouldn't GPP_F23 be set to NC here too? -- To view, visit https://review.coreboot.org/c/coreboot/+/88173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ideea34defdb6f4da63374ae09e2088c3de745657 Gerrit-Change-Number: 88173 Gerrit-PatchSet: 8 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Appukuttan Vk <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Attention: Appukuttan Vk <appukuttan.vk(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 13:54:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: drivers/crb/tpm: Add new method to retrieve base address
by Patrick Rudolph (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Cliff Huang, Lance Zhao, Tim Wawrzynczak. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/88249?usp=email ) Change subject: drivers/crb/tpm: Add new method to retrieve base address ...................................................................... drivers/crb/tpm: Add new method to retrieve base address In order to support runtime evaluation of the TPM base address introduce and use a new method for CRB TPMs. Change-Id: I29c81d82947eb2603472a515f9ada598e4f8e6ea Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/acpi/acpi.c M src/drivers/crb/tpm.c M src/drivers/crb/tpm.h 3 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/88249/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 84e314c..07e84f6d 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -281,7 +281,7 @@ tpm2->platform_class = 0; if (CONFIG(CRB_TPM)) { /* Must be set to 7 for CRB Support */ - tpm2->control_area = CONFIG_CRB_TPM_BASE_ADDRESS + 0x40; + tpm2->control_area = crb_tpm_base_address() + 0x40; tpm2->start_method = 7; } else { /* Must be set to 0 for FIFO interface support */ diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c index ea5e701..c33d634 100644 --- a/src/drivers/crb/tpm.c +++ b/src/drivers/crb/tpm.c @@ -346,3 +346,13 @@ return true; } + +/* + * crb_tpm_base_address + * + * Returns the CRB TPM base address. + */ +uintptr_t crb_tpm_base_address(void) +{ + return CONFIG_CRB_TPM_BASE_ADDRESS; +} diff --git a/src/drivers/crb/tpm.h b/src/drivers/crb/tpm.h index aaf63a4..dd44a2e 100644 --- a/src/drivers/crb/tpm.h +++ b/src/drivers/crb/tpm.h @@ -68,3 +68,5 @@ bool crb_tpm_is_active(void); tis_sendrecv_fn crb_tis_probe(enum tpm_family *family); + +uintptr_t crb_tpm_base_address(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/88249?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29c81d82947eb2603472a515f9ada598e4f8e6ea Gerrit-Change-Number: 88249 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>

1 0

[L] Change in coreboot[main]: [WIP]drivers/amd/ftpm: Add fTPM driver for PSP emulated CRB TPMs
by Patrick Rudolph (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Christian Walter, Cliff Huang, Lance Zhao, Tim Wawrzynczak. Hello Christian Walter, Cliff Huang, Lance Zhao, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/88247?usp=email to look at the new patch set (#2). Change subject: [WIP]drivers/amd/ftpm: Add fTPM driver for PSP emulated CRB TPMs ...................................................................... [WIP]drivers/amd/ftpm: Add fTPM driver for PSP emulated CRB TPMs The AMD fTPM uses the CRB interface, but doesn't implement all registers defined in the TCG specification. Add a new driver that deals with the reduced register set. The driver is intended to work with AMD family 1Ah SoCs only. The TPM interface also assumes that the DRTM is always using locality 0. TODO: Test on real hardware. Change-Id: I780bdab621228e12b37f3a89868e16bc62a05e7b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/acpi/acpi.c A src/drivers/amd/ftpm/Kconfig A src/drivers/amd/ftpm/Makefile.mk A src/drivers/amd/ftpm/chip.h A src/drivers/amd/ftpm/tis.c A src/drivers/amd/ftpm/tpm.c A src/drivers/amd/ftpm/tpm.h M src/security/tpm/tss/tss.c 8 files changed, 497 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/88247/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/88247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I780bdab621228e12b37f3a89868e16bc62a05e7b Gerrit-Change-Number: 88247 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com>

1 0

[M] Change in coreboot[main]: util/qualcomm: Add MBN v7 format support
by Subrata Banik (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Sasirekaa Madhesu, Varadarajan Narayanan, snlakshm snlakshm. Subrata Banik has posted comments on this change by Sasirekaa Madhesu. ( https://review.coreboot.org/c/coreboot/+/88240?usp=email ) Change subject: util/qualcomm: Add MBN v7 format support ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: > Yes, the image format of Bootblock ELF for Qualcomm 7c and 8x are different. > > On Qualcomm 7c, the QC_SEC and bootblock binaries are packed as segments of an ELF image (using createxbl.py) which is then converted to MBN v6 format ( using mbn_tools.py). > > For Qualcomm 8x, since we need the image in multi ELF format, we make use of create_multielf.py to concatenate the ELF images to melf image. > > As you said, createxbl.py would be invoked separately to generate the bootblock MBN image and then the create_multielf.py would be used to append the 4 images ( TME SEQ + TME FW + QC_SEC + BOOTBLOCK) can you please highlight the steps in the commit msg for easier understanding ? then feel free to mark this comment resolved Commit Message: https://review.coreboot.org/c/coreboot/+/88240/comment/8d85d5fc_f439474d?us… : PS1, Line 12: > Document update with MBN v7 format details is yet to be done. The document update is tracked as part of Bug ID: 404985109 BUG=b:420542130, b:404985109 TEST=Create image.serial.bin with bootblock in MBN v7 format and ensure it boots on X1P42100. Please refer to the steps mentioned below to create final AP FW image for QC SoC X1P42100. Step 1: Create MBN header using createxbl.py script where newly added MBN v7 script will be used. Step 2: Call into create_multielf.py would be used to append the 4 images ( TME SEQ + TME FW + QC_SEC + BOOTBLOCK from step 1) Step 3: Call nqgpt.py to create final GPT image. -- To view, visit https://review.coreboot.org/c/coreboot/+/88240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I484df537ac7d1e51ec86dcae74a74dc211710616 Gerrit-Change-Number: 88240 Gerrit-PatchSet: 1 Gerrit-Owner: Sasirekaa Madhesu <smadhesu(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Varadarajan Narayanan <vnarayan(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: snlakshm snlakshm <snlakshm(a)qualcomm.corp-partner.google.com> Gerrit-CC: Pavan Garimella <garimell(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Varadarajan Narayanan <vnarayan(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Sasirekaa Madhesu <smadhesu(a)qualcomm.corp-partner.google.com> Gerrit-Attention: snlakshm snlakshm <snlakshm(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 11:49:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sasirekaa Madhesu <smadhesu(a)qualcomm.corp-partner.google.com>

1 0

[S] Change in coreboot[main]: soc/qc/x1p42100: Support to generate Bootblock as multi ELF
by Subrata Banik (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Kapil Porwal, Sasirekaa Madhesu. Subrata Banik has posted comments on this change by Sasirekaa Madhesu. ( https://review.coreboot.org/c/coreboot/+/88241?usp=email ) Change subject: soc/qc/x1p42100: Support to generate Bootblock as multi ELF ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/88241?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc499221d8806b549f6c873a14382a28c3efb74f Gerrit-Change-Number: 88241 Gerrit-PatchSet: 2 Gerrit-Owner: Sasirekaa Madhesu <smadhesu(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sasirekaa Madhesu <smadhesu(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 11:45:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[L] Change in coreboot[main]: [WIP]drivers/amd/ftpm: Add fTPM driver for PSP emulated CRB TPMs
by Patrick Rudolph (Code Review) June 30, 2025

June 30, 2025

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/88247?usp=email ) Change subject: [WIP]drivers/amd/ftpm: Add fTPM driver for PSP emulated CRB TPMs ...................................................................... [WIP]drivers/amd/ftpm: Add fTPM driver for PSP emulated CRB TPMs The AMD fTPM uses the CRB interface, but doesn't implement all registers defined in the TCG specification. Add a new driver that deals with the reduced register set. The driver is intended to work with AMD family 1Ah SoCs only. The TPM interface also assumes that the DRTM is always using locality 0. TODO: Test on real hardware. Change-Id: I780bdab621228e12b37f3a89868e16bc62a05e7b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/acpi/acpi.c A src/drivers/amd/ftpm/Kconfig A src/drivers/amd/ftpm/Makefile.mk A src/drivers/amd/ftpm/chip.h A src/drivers/amd/ftpm/tis.c A src/drivers/amd/ftpm/tpm.c A src/drivers/amd/ftpm/tpm.h M src/security/tpm/tss/tss.c 8 files changed, 515 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/88247/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 84e314c..fd9f461 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -258,7 +258,7 @@ if (tlcl_get_family() != TPM_2) return; - if (CONFIG(CRB_TPM) && !(CONFIG(SPI_TPM) || CONFIG(I2C_TPM) || CONFIG(MEMORY_MAPPED_TPM))) + if ((CONFIG(CRB_TPM) || CONFIG(AMD_CRB_FTPM)) && !(CONFIG(SPI_TPM) || CONFIG(I2C_TPM) || CONFIG(MEMORY_MAPPED_TPM))) if (!crb_tpm_is_active()) return; @@ -279,7 +279,7 @@ /* Hard to detect for coreboot. Just set it to 0 */ tpm2->platform_class = 0; - if (CONFIG(CRB_TPM)) { + if (CONFIG(CRB_TPM) || CONFIG(AMD_CRB_FTPM)) { /* Must be set to 7 for CRB Support */ tpm2->control_area = CONFIG_CRB_TPM_BASE_ADDRESS + 0x40; tpm2->start_method = 7; diff --git a/src/drivers/amd/ftpm/Kconfig b/src/drivers/amd/ftpm/Kconfig new file mode 100644 index 0000000..20d7927 --- /dev/null +++ b/src/drivers/amd/ftpm/Kconfig @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config AMD_CRB_FTPM + bool + default n + depends on !CRB_TPM + depends on SOC_AMD_COMMON_BLOCK_PSP + help + Mainboard has fTPM with Command Response Buffer support diff --git a/src/drivers/amd/ftpm/Makefile.mk b/src/drivers/amd/ftpm/Makefile.mk new file mode 100644 index 0000000..4b7eaf7 --- /dev/null +++ b/src/drivers/amd/ftpm/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_AMD_CRB_FTPM),y) +all-y += tis.c tpm.c +endif diff --git a/src/drivers/amd/ftpm/chip.h b/src/drivers/amd/ftpm/chip.h new file mode 100644 index 0000000..7e69509 --- /dev/null +++ b/src/drivers/amd/ftpm/chip.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DRIVERS_AMD_FTPM_CHIP_H +#define DRIVERS_AMD_FTPM_CHIP_H + +struct drivers_amd_ftpm_config { +}; + +#endif /* DRIVERS_AMD_FTPM_CHIP_H */ diff --git a/src/drivers/amd/ftpm/tis.c b/src/drivers/amd/ftpm/tis.c new file mode 100644 index 0000000..3e23fe7 --- /dev/null +++ b/src/drivers/amd/ftpm/tis.c @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <security/tpm/tis.h> +#include <acpi/acpigen.h> +#include <device/device.h> +#include <drivers/intel/ptt/ptt.h> +#include <drivers/tpm/tpm_ppi.h> +#include <security/tpm/tss.h> +#include <endian.h> +#include <smbios.h> +#include <string.h> + +#include "tpm.h" +#include "chip.h" + +#define ACPI_DSM_START_METHOD_UUID "6bbf6cab-5463-4714-b7cd-f0203c0368d4" + +static const char *tis_get_dev_name(struct crb_tpm_info *info) +{ + return "fTPM"; +} + +static tpm_result_t crb_tpm_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, uint8_t *recvbuf, + size_t *rbuf_len) +{ + int len = crb_tpm_process_command(sendbuf, sbuf_size, recvbuf, *rbuf_len); + + if (len == 0) + return TPM_CB_FAIL; + + *rbuf_len = len; + + return TPM_SUCCESS; +} + +tis_sendrecv_fn crb_tis_probe(enum tpm_family *family) +{ + struct crb_tpm_info info; + + /* Wake TPM up (if necessary) */ + if (crb_tpm_init()) + return NULL; + + /* CRB interface exists only in TPM2 */ + if (family != NULL) + *family = TPM_2; + + crb_tpm_get_info(&info); + + printk(BIOS_INFO, "Initialized TPM device %s revision %d\n", tis_get_dev_name(&info), + info.revision); + + return &crb_tpm_sendrecv; +} + +static void start_method_cb(void *arg) +{ + /* Do nothing. */ +} + +static void (*acpi_start_method_callbacks[])(void *) = { + NULL, /* Enumerate functions (auto-generated) */ + start_method_cb, +}; + +static void crb_tpm_fill_ssdt(const struct device *dev) +{ + /* Device */ + acpigen_write_scope("\\_SB"); + acpigen_write_device(acpi_device_name(dev)); + + acpigen_write_name_string("_HID", "MSFT0101"); + acpigen_write_name_string("_CID", "MSFT0101"); + + acpi_device_write_uid(dev); + + if (crb_tpm_is_active()) + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + else + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_OFF); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpigen_write_mem32fixed(1, dev->path.mmio.addr, 0x30); + acpigen_write_resourcetemplate_footer(); + + if (!CONFIG(CHROMEOS) && CONFIG(TPM_PPI)) + tpm_ppi_acpi_fill_ssdt(dev); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *crb_tpm_acpi_name(const struct device *dev) +{ + return "TPM2"; +} + +#if CONFIG(GENERATE_SMBIOS_TABLES) && CONFIG(TPM2) +static tpm_result_t tpm_get_cap(uint32_t property, uint32_t *value) +{ + TPMS_CAPABILITY_DATA cap_data; + int i; + tpm_result_t rc; + + if (!value) + return TPM_CB_INVALID_ARG; + + rc = tlcl2_get_capability(TPM_CAP_TPM_PROPERTIES, property, 1, &cap_data); + + if (rc) + return rc; + + for (i = 0 ; i < cap_data.data.tpmProperties.count; i++) { + if (cap_data.data.tpmProperties.tpmProperty[i].property == property) { + *value = cap_data.data.tpmProperties.tpmProperty[i].value; + return TPM_SUCCESS; + } + } + + return TPM_CB_FAIL; +} + +static int smbios_write_type43_tpm(struct device *dev, int *handle, unsigned long *current) +{ + struct crb_tpm_info info; + uint32_t tpm_manuf, tpm_family; + uint32_t fw_ver1, fw_ver2; + uint8_t major_spec_ver, minor_spec_ver; + + if (tlcl_get_family() == TPM_1) + return 0; + + crb_tpm_get_info(&info); + + /* If any of these have invalid values, assume TPM not present or disabled */ + if (info.vendor_id == 0 || info.vendor_id == 0xFFFF || + info.device_id == 0 || info.device_id == 0xFFFF) { + printk(BIOS_DEBUG, "%s: Invalid Vendor ID/Device ID\n", __func__); + return 0; + } + + /* Vendor ID is the value returned by TPM2_GetCapabiltiy TPM_PT_MANUFACTURER */ + if (tpm_get_cap(TPM_PT_MANUFACTURER, &tpm_manuf)) { + printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_MANUFACTURER failed\n"); + return 0; + } + + tpm_manuf = be32toh(tpm_manuf); + + if (tpm_get_cap(TPM_PT_FIRMWARE_VERSION_1, &fw_ver1)) { + printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_FIRMWARE_VERSION_1 failed\n"); + return 0; + } + + if (tpm_get_cap(TPM_PT_FIRMWARE_VERSION_2, &fw_ver2)) { + printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_FIRMWARE_VERSION_2 failed\n"); + return 0; + } + + if (tpm_get_cap(TPM_PT_FAMILY_INDICATOR, &tpm_family)) { + printk(BIOS_DEBUG, "TPM2_GetCap TPM_PT_FAMILY_INDICATOR failed\n"); + return 0; + } + + tpm_family = be32toh(tpm_family); + + if (!strncmp((char *)&tpm_family, "2.0", 4)) { + major_spec_ver = 2; + minor_spec_ver = 0; + } else { + printk(BIOS_ERR, "%s: Invalid TPM family\n", __func__); + return 0; + } + + return smbios_write_type43(current, handle, tpm_manuf, major_spec_ver, minor_spec_ver, + fw_ver1, fw_ver2, tis_get_dev_name(&info), + SMBIOS_TPM_DEVICE_CHARACTERISTICS_NOT_SUPPORTED, 0); +} +#endif + +static struct device_operations __maybe_unused amd_crb_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = crb_tpm_acpi_name, + .acpi_fill_ssdt = crb_tpm_fill_ssdt, +#endif +#if CONFIG(GENERATE_SMBIOS_TABLES) && CONFIG(TPM2) + .get_smbios_data = smbios_write_type43_tpm, +#endif +}; + +static void enable_dev(struct device *dev) +{ +#if !DEVTREE_EARLY + dev->ops = &amd_crb_ops; +#endif +} + +struct chip_operations drivers_amd_ftpm_ops = { + .name = "AMD CRB fTPM", + .enable_dev = enable_dev +}; diff --git a/src/drivers/amd/ftpm/tpm.c b/src/drivers/amd/ftpm/tpm.c new file mode 100644 index 0000000..68f78ff --- /dev/null +++ b/src/drivers/amd/ftpm/tpm.c @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * This is a driver for the AMD fTPM CRB Interface. + * + * The general flow looks like this: + * + * TPM starts in IDLE Mode + * + * IDLE -------------> Command Reception + * ^ | + * | v + -- Cmd Complete <-- Command Execution + */ + +#include <timer.h> +#include <console/console.h> +#include <device/mmio.h> +#include <string.h> +#include <soc/pci_devs.h> +#include <device/pci_ops.h> +#include <block/psp/psp_def.h> + +#include "tpm.h" + +static struct control_area { + uint32_t start; + uint32_t command_size; + void *command_bfr; + uint32_t response_size; + void *response_bfr; +} control_area; + +/* Read Control Area Structure back */ +static void crb_readControlArea(void) +{ + control_area.command_size = read32(CRB_REG(CRB_REG_CMD_SIZE)); + control_area.command_bfr = + (void *)(uintptr_t)read64(CRB_REG(CRB_REG_CMD_ADDR)); + control_area.response_size = read32(CRB_REG(CRB_REG_RESP_SIZE)); + control_area.response_bfr = + (void *)(uintptr_t)read64(CRB_REG(CRB_REG_RESP_ADDR)); +} + +/* Wait for Reg to be expected Value */ +static tpm_result_t crb_wait_for_reg32(const void *addr, uint32_t timeoutMs, uint32_t mask, + uint32_t expectedValue) +{ + uint32_t regValue; + struct stopwatch sw; + + // Set up a timer which breaks the loop after timeout + stopwatch_init_msecs_expire(&sw, timeoutMs); + + while (1) { + // Now check if the TPM is in IDLE mode + regValue = read32(addr); + + if ((regValue & mask) == expectedValue) + return TPM_SUCCESS; + + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, + "CRB_WAIT: Error - Timed out with RegValue: %08x, Mask: %08x, Expected: %08x\n", + regValue, mask, expectedValue); + return TPM_CB_TIMEOUT; + } + } +} + +/* CRB PROBE + * + * Checks if the CRB Interface is ready + */ +static tpm_result_t crb_probe(void) +{ + if (!crb_tpm_is_active()) + return CB_ERR_NOT_IMPLEMENTED; + return CB_SUCCESS; +} + +/* + * crb_tpm_init + * + * Even though the TPM does not need an initialization we check + * if the TPM responds and is in IDLE mode, which should be the + * normal bring up mode. + * + */ +tpm_result_t crb_tpm_init(void) +{ + tpm_result_t rc = crb_probe(); + if (rc) { + printk(BIOS_ERR, "fTPM: Probe failed.\n"); + return rc; + } + + /* Read back control area structure */ + crb_readControlArea(); + + /* Good to go. */ + printk(BIOS_SPEW, "fTPM: CRB TPM initialized successfully\n"); + + return TPM_SUCCESS; +} + +/* + * crb_tpm_process_command + */ +size_t crb_tpm_process_command(const void *tpm2_command, size_t command_size, + void *tpm2_response, size_t max_response) +{ + tpm_result_t rc; + + if (command_size > control_area.command_size) { + printk(BIOS_ERR, "fTPM: Command size is too big.\n"); + return -1; + } + + if (control_area.response_size < max_response) { + printk(BIOS_ERR, "fTPM: Response size could be too big.\n"); + return -1; + } + + // Check if CMD bit is cleared. + rc = crb_wait_for_reg32(CRB_REG(CRB_REG_START), 250, CRB_REG_START_START, 0x0); + if (rc) { + printk(BIOS_ERR, "fTPM Error (%#x): Cmd Bit not cleared.\n", rc); + return -1; + } + + // Write to Command Buffer + memcpy(control_area.command_bfr, tpm2_command, command_size); + + // Clear Response buffer + memset(control_area.response_bfr, 0, max_response); + + // Register CRB_REG_RESP_SIZE will be updated by fTPM + write32(CRB_REG(CRB_REG_RESP_SIZE), control_area.response_size); + + // Write Start Bit + write8(CRB_REG(CRB_REG_START), 0x1); + + // Poll for Response + rc = crb_wait_for_reg32(CRB_REG(CRB_REG_START), 3500, CRB_REG_START_START, 0); + if (rc) { + printk(BIOS_DEBUG, "fTPM Error (%#x): Command Timed out.\n", rc); + return -1; + } + + // Check for errors + rc = crb_wait_for_reg32(CRB_REG(CRB_REG_STATUS), 200, CRB_REG_STATUS_ERROR, 0); + if (rc) { + printk(BIOS_DEBUG, "fTPM Error (%#x): Command errored.\n", rc); + return -1; + } + + // Get Response Length + uint32_t length = read32(CRB_REG(CRB_REG_RESP_SIZE)); + + /* Response has to have at least 6 bytes */ + if (length < 6 || length > max_response) + return 1; + + // Copy Response + memcpy(tpm2_response, control_area.response_bfr, length); + + return length; +} + +/* + * tp2_get_info + * + * Returns information about the TPM + * + */ +void crb_tpm_get_info(struct crb_tpm_info *crb_tpm_info) +{ + /* Register CRB_REG_INTF_ID isn't supported. Use AMD HSP device ID. */ + crb_tpm_info->vendor_id = 0x1022; + crb_tpm_info->device_id = 0x163E; + crb_tpm_info->revision = 0; +} + +/* + * crb_tpm_is_active + * + * Checks that CRB interface is available and active. + * + */ +bool crb_tpm_is_active(void) +{ + // Register CRB_REG_INTF_ID is not supported + uint32_t caps = 0; + + // PSP must report fTPM support + if (psp_get_ftpm_capabilties(&caps) != CB_SUCCESS) + return false; + + if (!(caps & MBOX_FTPM_CAP_TPM_SUPPORTED)) + return false; + + // DRTM is always in locality 0 + const uint8_t loc_state = read8(CRB_REG(CRB_REG_LOC_STATE)); + const uint8_t locality = (loc_state >> 2) & 0x07; + const uint8_t locality_enabled = (loc_state >> 1) & 1; + + if (locality != 0 || !locality_enabled) + return false; + + return true; +} diff --git a/src/drivers/amd/ftpm/tpm.h b/src/drivers/amd/ftpm/tpm.h new file mode 100644 index 0000000..81d2fdc --- /dev/null +++ b/src/drivers/amd/ftpm/tpm.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* This is a driver for a Command Response Buffer Interface */ + +#include <security/tpm/tis.h> +#include <security/tpm/tss_errors.h> + +/* CRB driver */ +/* address of locality 0 (CRB) */ +#define TPM_CRB_BASE_ADDRESS CONFIG_CRB_TPM_BASE_ADDRESS + +#define CRB_REG(REG) \ + (void *)(uintptr_t)(CONFIG_CRB_TPM_BASE_ADDRESS + REG) + +/* hardware registers */ + +#define CRB_REG_LOC_STATE 0x00 /* Readonly */ +//#define CRB_REG_LOC_CTRL 0x08 +//#define CRB_REG_LOC_STS 0x0C + +/* LOC_CTRL BIT MASKS */ +//#define LOC_CTRL_REQ_ACCESS 0x01 + +/* LOC STATE BIT MASKS */ +//#define LOC_STATE_LOC_ASSIGN 0x02 +//#define LOC_STATE_REG_VALID_STS 0x80 + +/* LOC STS BIT MASKS */ +//#define LOC_STS_GRANTED 0x01 + +//#define CRB_REG_INTF_ID 0x30 + +//#define CRB_REG_REQUEST 0x40 +#define CRB_REG_STATUS 0x44 +//#define CRB_REG_CANCEL 0x48 +#define CRB_REG_START 0x4C +//#define CRB_REG_INT_CTRL 0x50 +#define CRB_REG_CMD_SIZE 0x58 +#define CRB_REG_CMD_ADDR 0x5C +#define CRB_REG_RESP_SIZE 0x64 +#define CRB_REG_RESP_ADDR 0x68 +//#define CRB_REG_DATA_BUFF 0x80 + +/* CRB INTF BIT MASK */ +//#define CRB_INTF_REG_CAP_CRB (1<<14) +//#define CRB_INTF_REG_INTF_SEL (1<<17) +//#define CRB_INTF_REG_INTF_LOCK (1<<19) + +/*REQUEST Register related */ +//#define CRB_REG_REQUEST_CMD_RDY 0x01 +//#define CRB_REG_REQUEST_GO_IDLE 0x02 + +/* STATUS Register related */ +#define CRB_REG_STATUS_ERROR 0x01 +//#define CRB_REG_STATUS_IDLE 0x02 + +/* START Register related */ +#define CRB_REG_START_START 0x01 + +/* CRB TPM Info Struct */ +struct crb_tpm_info { + uint16_t vendor_id; + uint16_t device_id; + uint16_t revision; +}; + +tpm_result_t crb_tpm_init(void); +void crb_tpm_get_info(struct crb_tpm_info *crb_tpm_info); +size_t crb_tpm_process_command(const void *tpm2_command, size_t command_size, + void *tpm2_response, size_t max_response); +bool crb_tpm_is_active(void); + +tis_sendrecv_fn crb_tis_probe(enum tpm_family *family); diff --git a/src/security/tpm/tss/tss.c b/src/security/tpm/tss/tss.c index 8e52de7..f4deb2d 100644 --- a/src/security/tpm/tss/tss.c +++ b/src/security/tpm/tss/tss.c @@ -29,7 +29,7 @@ init_done = true; tlcl_tis_sendrecv = NULL; - if (CONFIG(CRB_TPM)) + if (CONFIG(CRB_TPM) || CONFIG(AMD_CRB_FTPM)) tlcl_tis_sendrecv = crb_tis_probe(&tlcl_tpm_family); if (CONFIG(MEMORY_MAPPED_TPM) && tlcl_tis_sendrecv == NULL) tlcl_tis_sendrecv = pc80_tis_probe(&tlcl_tpm_family); -- To view, visit https://review.coreboot.org/c/coreboot/+/88247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I780bdab621228e12b37f3a89868e16bc62a05e7b Gerrit-Change-Number: 88247 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

[M] Change in coreboot[main]: util/qualcomm: Add MBN v7 format support
by Sasirekaa Madhesu (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Subrata Banik, Varadarajan Narayanan, snlakshm snlakshm. Sasirekaa Madhesu has posted comments on this change by Sasirekaa Madhesu. ( https://review.coreboot.org/c/coreboot/+/88240?usp=email ) Change subject: util/qualcomm: Add MBN v7 format support ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: > Can you help me understand how various tooling is used in current Qualcomm SoCs? […] Yes, the image format of Bootblock ELF for Qualcomm 7c and 8x are different. On Qualcomm 7c, the QC_SEC and bootblock binaries are packed as segments of an ELF image (using createxbl.py) which is then converted to MBN v6 format ( using mbn_tools.py). For Qualcomm 8x, since we need the image in multi ELF format, we make use of create_multielf.py to concatenate the ELF images to melf image. As you said, createxbl.py would be invoked separately to generate the bootblock MBN image and then the create_multielf.py would be used to append the 4 images ( TME SEQ + TME FW + QC_SEC + BOOTBLOCK) Commit Message: https://review.coreboot.org/c/coreboot/+/88240/comment/69a5ec60_423d6e82?us… : PS1, Line 12: > It would be super helpful if you could also share the link or a document where I can find more infor […] Document update with MBN v7 format details is yet to be done. The document update is tracked as part of Bug ID: 404985109 -- To view, visit https://review.coreboot.org/c/coreboot/+/88240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I484df537ac7d1e51ec86dcae74a74dc211710616 Gerrit-Change-Number: 88240 Gerrit-PatchSet: 1 Gerrit-Owner: Sasirekaa Madhesu <smadhesu(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Varadarajan Narayanan <vnarayan(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: snlakshm snlakshm <snlakshm(a)qualcomm.corp-partner.google.com> Gerrit-CC: Pavan Garimella <garimell(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Varadarajan Narayanan <vnarayan(a)qualcomm.corp-partner.google.com> Gerrit-Attention: snlakshm snlakshm <snlakshm(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 10:32:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0