June 2025 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: sb/intel/lynxpoint: Use Broadwell SerialIO implementation
by Angel Pons (Code Review) Feb. 27, 2026

Feb. 27, 2026

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46969 ) Change subject: sb/intel/lynxpoint: Use Broadwell SerialIO implementation ...................................................................... sb/intel/lynxpoint: Use Broadwell SerialIO implementation Add power state control methods for more devices using helper methods. Change-Id: I96a3b896346f6f1e5aa4a1dc45638cbcff01b7dd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/serialio.asl 1 file changed, 96 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46969/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 845949c..0e246f7 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -16,6 +16,28 @@ External (\S6EN) External (\S7EN) +// Put SerialIO device in D0 state +// Arg0 - Ref to offset 0x84 of device's PCI config space +Method (LPD0, 1, Serialized) +{ + DeRefOf (Arg0) &= 0xFFFFFFFC + Local0 = DeRefOf (Arg0) // Read back after writing + + // Use Local0 to avoid iasl warning: Method Local is set but never used + Local0 &= Ones +} + +// Put SerialIO device in D3 state +// Arg0 - Ref to offset 0x84 of device's PCI config space +Method (LPD3, 1, Serialized) +{ + DeRefOf (Arg0) |= 0x3 + Local0 = DeRefOf (Arg0) // Read back after writing + + // Use Local0 to avoid iasl warning: Method Local is set but never used + Local0 &= Ones +} + // Serial IO Resource Consumption for BAR1 Device (SIOR) { @@ -193,32 +215,20 @@ } } - // Access to PCI Config in ACPI mode - OperationRegion (KEYS, SystemMemory, \S1B1, 0x100) - Field (KEYS, DWordAcc, NoLock, Preserve) + OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) { - Offset (0x84), - PSAT, 32, + SPCS, 32 } - // Put controller in D0 state Method (_PS0, 0, Serialized) { - ^PSAT &= 0xfffffffc - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD0 (RefOf (SPCS)) } - // Put controller in D3Hot state Method (_PS3, 0, Serialized) { - ^PSAT |= 0x00000003 - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD3 (RefOf (SPCS)) } } @@ -273,32 +283,20 @@ } } - // Access to PCI Config in ACPI mode - OperationRegion (KEYS, SystemMemory, \S2B1, 0x100) - Field (KEYS, DWordAcc, NoLock, Preserve) + OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) { - Offset (0x84), - PSAT, 32, + SPCS, 32 } - // Put controller in D0 state Method (_PS0, 0, Serialized) { - ^PSAT &= 0xfffffffc - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD0 (RefOf (SPCS)) } - // Put controller in D3Hot state Method (_PS3, 0, Serialized) { - ^PSAT |= 0x00000003 - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD3 (RefOf (SPCS)) } } @@ -337,6 +335,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (SPI1) @@ -386,6 +400,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (UAR0) @@ -435,6 +465,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (UAR1) @@ -472,6 +518,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (SDIO) -- To view, visit https://review.coreboot.org/c/coreboot/+/46969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96a3b896346f6f1e5aa4a1dc45638cbcff01b7dd Gerrit-Change-Number: 46969 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods
by Angel Pons (Code Review) Feb. 27, 2026

Feb. 27, 2026

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46967 ) Change subject: soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods ...................................................................... soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods Creating named objects within a method is highly inefficient. So, pass a reference to the OperationRegion field that needs to be updated instead. Change-Id: I88272fc5cbe35427ccb5fc50789d47b66ace88fe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 54 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46967/1 diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index b03bcdd..35b15b4 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -6,34 +6,22 @@ #define SIO_BAR_LEN 0x1000 // Put SerialIO device in D0 state -// Arg0 - BAR1 of device +// Arg0 - Ref to offset 0x84 of device's PCI config space Method (LPD0, 1, Serialized) { - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) - Field (SPRT, DWordAcc, NoLock, Preserve) - { - SPCS, 32 - } - - SPCS &= 0xFFFFFFFC - Local0 = SPCS // Read back after writing + DeRefOf (Arg0) &= 0xFFFFFFFC + Local0 = DeRefOf (Arg0) // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used Local0 &= Ones } // Put SerialIO device in D3 state -// Arg0 - BAR1 of device +// Arg0 - Ref to offset 0x84 of device's PCI config space Method (LPD3, 1, Serialized) { - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) - Field (SPRT, DWordAcc, NoLock, Preserve) - { - SPCS, 32 - } - - SPCS |= 0x3 - Local0 = SPCS // Read back after writing + DeRefOf (Arg0) |= 0x3 + Local0 = DeRefOf (Arg0) // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used Local0 &= Ones @@ -226,14 +214,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S1B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S1B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -297,14 +291,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S2B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S2B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -353,14 +353,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S3B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S3B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -421,14 +427,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S4B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S4B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -489,14 +501,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S5B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S5B1) + ^^LPD3 (RefOf (SPCS)) } } @@ -545,14 +563,20 @@ } } + OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S6B1) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S6B1) + ^^LPD3 (RefOf (SPCS)) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88272fc5cbe35427ccb5fc50789d47b66ace88fe Gerrit-Change-Number: 46967 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/variants/dood: Disable XHCI LFPS power management
by Kenneth Chan (Code Review) Nov. 27, 2025

Nov. 27, 2025

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41143 ) Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ...................................................................... mb/google/octopus/variants/dood: Disable XHCI LFPS power management LTE module is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c --- M src/mainboard/google/octopus/variants/dood/overridetree.cb M src/mainboard/google/octopus/variants/dood/variant.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41143/1 diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index 6df9f53..e1f12cf 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -149,4 +149,5 @@ # Disable compliance mode register "DisableComplianceMode" = "1" + register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index e728fe3..ab049a8 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -8,6 +8,7 @@ #include <delay.h> #include <gpio.h> #include <ec/google/chromeec/ec.h> +#include <soc/intel/apollolake/chip.h> enum { SKU_1_LTE = 1, /* Wifi + LTE */ @@ -61,3 +62,21 @@ return; } } + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + + if (cfg != NULL && cfg->disable_xhci_lfps_pm) { + switch (google_chromeec_get_board_sku()) { + case SKU_1_LTE: + case SKU_3_LTE_2CAM: + cfg->disable_xhci_lfps_pm = 1; + return; + default: + return; + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c Gerrit-Change-Number: 41143 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/magolor: Configure I2C high and low time
by Ren Kuo (Code Review) Sept. 16, 2025

Sept. 16, 2025

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46613 ) Change subject: mb/google/dedede/var/magolor: Configure I2C high and low time ...................................................................... mb/google/dedede/var/magolor: Configure I2C high and low time Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:168783630 TEST=Measured the I2C bus frequency reduce to 387 KHz. Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1 --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/46613/1 diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index f41e9fa..625546e 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -25,18 +25,42 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[3] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/46613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1 Gerrit-Change-Number: 46613 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: soc/qualcomm/x1p42100: Add Clock support for x1p42100
by Swathi Tamilselvan (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Julius Werner, Kapil Porwal. Swathi Tamilselvan has posted comments on this change by Swathi Tamilselvan. ( https://review.coreboot.org/c/coreboot/+/88175?usp=email ) Change subject: soc/qualcomm/x1p42100: Add Clock support for x1p42100 ...................................................................... Patch Set 6: (2 comments) File src/soc/qualcomm/x1p42100/clock.c: https://review.coreboot.org/c/coreboot/+/88175/comment/40ad5de2_9ec9c4c8?us… : PS5, Line 11: KHz > MHz? Done File src/soc/qualcomm/x1p42100/include/soc/clock.h: https://review.coreboot.org/c/coreboot/+/88175/comment/9746046d_88c29133?us… : PS5, Line 10: #define SRC_XO_HZ (19200 * KHz) > Is the source oscillator on this platform actually 19. […] Yes the XO from PMIC is 38.4MHz, while there are some Internal drivers and final software use 19.2MHz. -- To view, visit https://review.coreboot.org/c/coreboot/+/88175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6252bc1fda3c53a683c65d2ab4a3b9f27ea64618 Gerrit-Change-Number: 88175 Gerrit-PatchSet: 6 Gerrit-Owner: Swathi Tamilselvan <tswathi(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 30 Jun 2025 23:22:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: mb/starlabs/starlite_adl: Add support for MXC6655 accelerometer
by Sean Rhodes (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/88253?usp=email ) Change subject: mb/starlabs/starlite_adl: Add support for MXC6655 accelerometer ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/88253?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I59d424903cceda9871855372e1d666eaa12443b0 Gerrit-Change-Number: 88253 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 20:23:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/starlabs/starlite_adl: Add support for MXC6655 accelerometer
by Matt DeVillier (Code Review) June 30, 2025

June 30, 2025

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/88253?usp=email ) Change subject: mb/starlabs/starlite_adl: Add support for MXC6655 accelerometer ...................................................................... mb/starlabs/starlite_adl: Add support for MXC6655 accelerometer Add support for the Memsic MXC6655 accelerometer on I2C0, as an alternative to the existing Kionix KCXJ9. Use the "detect" function of the I2C generic driver to determine which is present at runtime. TEST=build/boot starlite_adl with MXC6655, verify screen roation works properly when detached from keyboard under Linux and Windows. Change-Id: I59d424903cceda9871855372e1d666eaa12443b0 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/88253/1 diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index 862f31f..598e272 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -157,8 +157,18 @@ register "has_rotation_matrix" = "1" register "rotation_matrix" = "{1, 0, 0, 0, -1, 0, 0, 0, 1}" register "cdm_index" = "6" + register "detect" = "1" device i2c 0f on end end + chip drivers/i2c/generic + register "hid" = ""MXC6655"" + register "cid" = ""MXC6655"" + register "desc" = ""Accelerometer"" + register "has_rotation_matrix" = "1" + register "rotation_matrix" = "{1, 0, 0, 0, -1, 0, 0, 0, 1}" + register "detect" = "1" + device i2c 15 on end + end end device ref i2c2 on # Touchscreen chip drivers/i2c/hid -- To view, visit https://review.coreboot.org/c/coreboot/+/88253?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I59d424903cceda9871855372e1d666eaa12443b0 Gerrit-Change-Number: 88253 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/brox: Update cpu power limits
by Karthik Ramasubramanian (Code Review) June 30, 2025

June 30, 2025

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/88213?usp=email ) Change subject: mb/google/brox: Update cpu power limits ...................................................................... mb/google/brox: Update cpu power limits brox_rtk_ec share the same power design with brox, so follow brox set as 9W. BUG=b:414474440 TEST=system can boot when AC only. Change-Id: Ia05b331f229127b898f4549d5ba1ac2771ac8b7b Signed-off-by: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88213 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Keith Short <keithshort(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified Keith Short: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index a94995a..9a22731 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -124,6 +124,7 @@ config PL4_LIMIT_FOR_CRITICAL_BAT_BOOT int default 9 if BOARD_GOOGLE_BROX + default 9 if BOARD_GOOGLE_BROX_RTK_EC default 14 if BOARD_GOOGLE_JUBILANT default 40 if BOARD_GOOGLE_LOTSO help -- To view, visit https://review.coreboot.org/c/coreboot/+/88213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia05b331f229127b898f4549d5ba1ac2771ac8b7b Gerrit-Change-Number: 88213 Gerrit-PatchSet: 5 Gerrit-Owner: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Gerrit-Reviewer: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/brox: Update cpu power limits
by Karthik Ramasubramanian (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Elmo Lan, Paul Menzel. Karthik Ramasubramanian has posted comments on this change by Elmo Lan. ( https://review.coreboot.org/c/coreboot/+/88213?usp=email ) Change subject: mb/google/brox: Update cpu power limits ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/88213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia05b331f229127b898f4549d5ba1ac2771ac8b7b Gerrit-Change-Number: 88213 Gerrit-PatchSet: 4 Gerrit-Owner: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Gerrit-Reviewer: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 30 Jun 2025 19:16:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brox: Update cpu power limits
by Keith Short (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Elmo Lan, Paul Menzel. Keith Short has posted comments on this change by Elmo Lan. ( https://review.coreboot.org/c/coreboot/+/88213?usp=email ) Change subject: mb/google/brox: Update cpu power limits ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/88213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia05b331f229127b898f4549d5ba1ac2771ac8b7b Gerrit-Change-Number: 88213 Gerrit-PatchSet: 4 Gerrit-Owner: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Gerrit-Reviewer: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 30 Jun 2025 17:52:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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