June 2025 - coreboot-gerrit - mail.coreboot.org

[L] Change in coreboot[main]: soc/qualcomm/x1p42100: Add Clock support for x1p42100
by Swathi Tamilselvan (Code Review) July 1, 2025

July 1, 2025

Attention is currently required from: Julius Werner, Kapil Porwal. Swathi Tamilselvan has posted comments on this change by Swathi Tamilselvan. ( https://review.coreboot.org/c/coreboot/+/88175?usp=email ) Change subject: soc/qualcomm/x1p42100: Add Clock support for x1p42100 ...................................................................... Patch Set 6: (2 comments) File src/soc/qualcomm/x1p42100/clock.c: https://review.coreboot.org/c/coreboot/+/88175/comment/40ad5de2_9ec9c4c8?us… : PS5, Line 11: KHz > MHz? Done File src/soc/qualcomm/x1p42100/include/soc/clock.h: https://review.coreboot.org/c/coreboot/+/88175/comment/9746046d_88c29133?us… : PS5, Line 10: #define SRC_XO_HZ (19200 * KHz) > Is the source oscillator on this platform actually 19. […] Yes the XO from PMIC is 38.4MHz, while there are some Internal drivers and final software use 19.2MHz. -- To view, visit https://review.coreboot.org/c/coreboot/+/88175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6252bc1fda3c53a683c65d2ab4a3b9f27ea64618 Gerrit-Change-Number: 88175 Gerrit-PatchSet: 6 Gerrit-Owner: Swathi Tamilselvan <tswathi(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 30 Jun 2025 23:22:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: mb/starlabs/starlite_adl: Add support for MXC6655 accelerometer
by Sean Rhodes (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/88253?usp=email ) Change subject: mb/starlabs/starlite_adl: Add support for MXC6655 accelerometer ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/88253?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I59d424903cceda9871855372e1d666eaa12443b0 Gerrit-Change-Number: 88253 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 20:23:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/starlabs/starlite_adl: Add support for MXC6655 accelerometer
by Matt DeVillier (Code Review) June 30, 2025

June 30, 2025

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/88253?usp=email ) Change subject: mb/starlabs/starlite_adl: Add support for MXC6655 accelerometer ...................................................................... mb/starlabs/starlite_adl: Add support for MXC6655 accelerometer Add support for the Memsic MXC6655 accelerometer on I2C0, as an alternative to the existing Kionix KCXJ9. Use the "detect" function of the I2C generic driver to determine which is present at runtime. TEST=build/boot starlite_adl with MXC6655, verify screen roation works properly when detached from keyboard under Linux and Windows. Change-Id: I59d424903cceda9871855372e1d666eaa12443b0 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/88253/1 diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index 862f31f..598e272 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -157,8 +157,18 @@ register "has_rotation_matrix" = "1" register "rotation_matrix" = "{1, 0, 0, 0, -1, 0, 0, 0, 1}" register "cdm_index" = "6" + register "detect" = "1" device i2c 0f on end end + chip drivers/i2c/generic + register "hid" = ""MXC6655"" + register "cid" = ""MXC6655"" + register "desc" = ""Accelerometer"" + register "has_rotation_matrix" = "1" + register "rotation_matrix" = "{1, 0, 0, 0, -1, 0, 0, 0, 1}" + register "detect" = "1" + device i2c 15 on end + end end device ref i2c2 on # Touchscreen chip drivers/i2c/hid -- To view, visit https://review.coreboot.org/c/coreboot/+/88253?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I59d424903cceda9871855372e1d666eaa12443b0 Gerrit-Change-Number: 88253 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/brox: Update cpu power limits
by Karthik Ramasubramanian (Code Review) June 30, 2025

June 30, 2025

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/88213?usp=email ) Change subject: mb/google/brox: Update cpu power limits ...................................................................... mb/google/brox: Update cpu power limits brox_rtk_ec share the same power design with brox, so follow brox set as 9W. BUG=b:414474440 TEST=system can boot when AC only. Change-Id: Ia05b331f229127b898f4549d5ba1ac2771ac8b7b Signed-off-by: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88213 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Keith Short <keithshort(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified Keith Short: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index a94995a..9a22731 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -124,6 +124,7 @@ config PL4_LIMIT_FOR_CRITICAL_BAT_BOOT int default 9 if BOARD_GOOGLE_BROX + default 9 if BOARD_GOOGLE_BROX_RTK_EC default 14 if BOARD_GOOGLE_JUBILANT default 40 if BOARD_GOOGLE_LOTSO help -- To view, visit https://review.coreboot.org/c/coreboot/+/88213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia05b331f229127b898f4549d5ba1ac2771ac8b7b Gerrit-Change-Number: 88213 Gerrit-PatchSet: 5 Gerrit-Owner: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Gerrit-Reviewer: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/brox: Update cpu power limits
by Karthik Ramasubramanian (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Elmo Lan, Paul Menzel. Karthik Ramasubramanian has posted comments on this change by Elmo Lan. ( https://review.coreboot.org/c/coreboot/+/88213?usp=email ) Change subject: mb/google/brox: Update cpu power limits ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/88213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia05b331f229127b898f4549d5ba1ac2771ac8b7b Gerrit-Change-Number: 88213 Gerrit-PatchSet: 4 Gerrit-Owner: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Gerrit-Reviewer: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 30 Jun 2025 19:16:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brox: Update cpu power limits
by Keith Short (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Elmo Lan, Paul Menzel. Keith Short has posted comments on this change by Elmo Lan. ( https://review.coreboot.org/c/coreboot/+/88213?usp=email ) Change subject: mb/google/brox: Update cpu power limits ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/88213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia05b331f229127b898f4549d5ba1ac2771ac8b7b Gerrit-Change-Number: 88213 Gerrit-PatchSet: 4 Gerrit-Owner: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Gerrit-Reviewer: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elmo Lan <elmo_lan(a)realtek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 30 Jun 2025 17:52:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/qualcomm/x1p42100: Add external BL31 file path
by Subrata Banik (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Kapil Porwal. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/88252?usp=email ) Change subject: soc/qualcomm/x1p42100: Add external BL31 file path ...................................................................... soc/qualcomm/x1p42100: Add external BL31 file path This commit overviews Kconfig option, `ARM64_BL31_EXTERNAL_FILE`, to specify the path for the BL31 binary for the Qualcomm X1P42100 SoC. Previously, the BL31 binary was expected to be located in a fixed internal path. This change allows for greater flexibility by enabling users to provide an external path, which is particularly useful for integrating pre-built or proprietary BL31 binaries. The default path is set to "3rdparty/qc_blobs/x1p42100/bl31.elf". BUG=b:428684788 TEST=Able to build google/bluey with QC private TF-A blobs. Qualcomm plan to add `x1p42100` SoC support in TF-A upstream post 09/01. Change-Id: I30ad7e95472c7fd925f9baf61d049631d9237630 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/qualcomm/x1p42100/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/88252/1 diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig index cb32c2f..2e823b2 100644 --- a/src/soc/qualcomm/x1p42100/Kconfig +++ b/src/soc/qualcomm/x1p42100/Kconfig @@ -28,6 +28,10 @@ if SOC_QUALCOMM_X1P42100 +config ARM64_BL31_EXTERNAL_FILE + string + default "3rdparty/qc_blobs/x1p42100/bl31.elf" + config QC_BLOBS_UPSTREAM bool "QC blobs are available in upstream repository" select USE_QC_BLOBS -- To view, visit https://review.coreboot.org/c/coreboot/+/88252?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30ad7e95472c7fd925f9baf61d049631d9237630 Gerrit-Change-Number: 88252 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>

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[XS] Change in coreboot[main]: soc/qualcomm/x1p42100: Select ARM64_USE_ARM_TRUSTED_FIRMWARE
by Subrata Banik (Code Review) June 30, 2025

June 30, 2025

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/88251?usp=email ) Change subject: soc/qualcomm/x1p42100: Select ARM64_USE_ARM_TRUSTED_FIRMWARE ...................................................................... soc/qualcomm/x1p42100: Select ARM64_USE_ARM_TRUSTED_FIRMWARE This commit enables `ARM64_USE_ARM_TRUSTED_FIRMWARE` for the Qualcomm X1P42100 SoC. Selecting this option ensures that coreboot is configured to integrate with ARM Trusted Firmware (TF-A), which is essential for proper boot and power management functionality on this platform. BUG=b:424149462 TEST=Able to build google/bluey. Change-Id: I30bc3eb9eedcaaef67cccf8c2f29c6ed76c71e9a Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/qualcomm/x1p42100/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/88251/1 diff --git a/src/soc/qualcomm/x1p42100/Kconfig b/src/soc/qualcomm/x1p42100/Kconfig index 7aa6481..cb32c2f 100644 --- a/src/soc/qualcomm/x1p42100/Kconfig +++ b/src/soc/qualcomm/x1p42100/Kconfig @@ -8,6 +8,7 @@ select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 select ARM64_USE_ARCH_TIMER + select ARM64_USE_ARM_TRUSTED_FIRMWARE select CACHE_MRC_SETTINGS select COMMONLIB_STORAGE select COMMONLIB_STORAGE_SD -- To view, visit https://review.coreboot.org/c/coreboot/+/88251?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30bc3eb9eedcaaef67cccf8c2f29c6ed76c71e9a Gerrit-Change-Number: 88251 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/qualcomm/common: Update QUP register structure for QUP v3.2
by Subrata Banik (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Julius Werner, Swathi Tamilselvan. Subrata Banik has posted comments on this change by Swathi Tamilselvan. ( https://review.coreboot.org/c/coreboot/+/88190?usp=email ) Change subject: soc/qualcomm/common: Update QUP register structure for QUP v3.2 ...................................................................... Patch Set 4: (1 comment) File src/soc/qualcomm/common/clock.c: https://review.coreboot.org/c/coreboot/+/88190/comment/0ae08218_ca88d8d4?us… : PS4, Line 138: else > This will be true for WRAP2 as well. I missed this part during the review. for platform w/ QC_COMMON_QUPV3_2 Kconfig, we wish to program all three QUP wraps isn't it. -- To view, visit https://review.coreboot.org/c/coreboot/+/88190?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I304012d72a1af33510dcd620953367f0a9e98ac1 Gerrit-Change-Number: 88190 Gerrit-PatchSet: 4 Gerrit-Owner: Swathi Tamilselvan <tswathi(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Swathi Tamilselvan <tswathi(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 16:35:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[S] Change in coreboot[main]: soc/qualcomm/common: Update QUP register structure for QUP v3.2
by Subrata Banik (Code Review) June 30, 2025

June 30, 2025

Attention is currently required from: Julius Werner, Swathi Tamilselvan. Subrata Banik has posted comments on this change by Swathi Tamilselvan. ( https://review.coreboot.org/c/coreboot/+/88190?usp=email ) Change subject: soc/qualcomm/common: Update QUP register structure for QUP v3.2 ...................................................................... Patch Set 4: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/88190?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I304012d72a1af33510dcd620953367f0a9e98ac1 Gerrit-Change-Number: 88190 Gerrit-PatchSet: 4 Gerrit-Owner: Swathi Tamilselvan <tswathi(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Swathi Tamilselvan <tswathi(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 30 Jun 2025 16:33:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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