November 2025 - coreboot-gerrit

[XS] Change in coreboot[main]: mb/google/ocelot/var/matsu: Fix GPP_V3 internal pull-up configuration
by Ivy Jian (Code Review) Nov. 30, 2025

Nov. 30, 2025

Attention is currently required from: Avi Uday, Ivy Jian, Nick Vaccaro, Paul Menzel, Pranava Y N. Hello Avi Uday, Bob Moragues, Nick Vaccaro, Paul Menzel, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/90218?usp=email to look at the new patch set (#3). Change subject: mb/google/ocelot/var/matsu: Fix GPP_V3 internal pull-up configuration ...................................................................... mb/google/ocelot/var/matsu: Fix GPP_V3 internal pull-up configuration According to doc#836031, GPP_V3 defaults to Native F1 with the integrated pull-up enabled. However, coreboot was configuring this pin with the internal pull-up set to NONE, which disabled the pull-up and caused GPP_V3/PWRBTN# to read low, leading to unexpected shutdowns. Update the pad configuration to use the internal pull-up. BUG=b:463193164 TEST=boots normally and no unexpected shutdown occurs. Change-Id: Ia650aa9b60d7ce634827330954b1a9c9ac3d7567 Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/mainboard/google/ocelot/variants/matsu/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/90218/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/90218?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia650aa9b60d7ce634827330954b1a9c9ac3d7567 Gerrit-Change-Number: 90218 Gerrit-PatchSet: 3 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chiasheng Lee <chiasheng.lee(a)intel.corp-partner.google.com> Gerrit-CC: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Ryan Lin <ryan.lin(a)intel.corp-partner.google.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: mb/google/dedede/var/galtic: Add fw_config option for touchpad type
by Matt DeVillier (Code Review) Nov. 30, 2025

Nov. 30, 2025

Matt DeVillier has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/83606?usp=email ) Change subject: mb/google/dedede/var/galtic: Add fw_config option for touchpad type ...................................................................... Abandoned abandoning in favor of selection via CFR, since it's less intrusive -- To view, visit https://review.coreboot.org/c/coreboot/+/83606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36797eb5c8f262782380f95ff3c2e38443cf00c0 Gerrit-Change-Number: 83606 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

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[S] Change in coreboot[main]: drivers/tpm/ppi: Fix generated ACPI
by Matt DeVillier (Code Review) Nov. 30, 2025

Nov. 30, 2025

Attention is currently required from: Nicholas Sudsgaard, Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84606?usp=email ) Change subject: drivers/tpm/ppi: Fix generated ACPI ...................................................................... Patch Set 12: (1 comment) File src/drivers/tpm/ppi.c: https://review.coreboot.org/c/coreboot/+/84606/comment/9f3c5afd_a8f32644?us… : PS12, Line 634: acpigen_write_method_serialized("FUNC", 1); can you provide the generated ASL in a comment above as is done elsewhere for acpigen functions? -- To view, visit https://review.coreboot.org/c/coreboot/+/84606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If80bb5bf69562f8b904c1b315e95a0b5627efbc4 Gerrit-Change-Number: 84606 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Comment-Date: Sun, 30 Nov 2025 21:35:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brya: Enable ACPI S3 sleep state support
by Matt DeVillier (Code Review) Nov. 30, 2025

Nov. 30, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/90252?usp=email ) Change subject: mb/google/brya: Enable ACPI S3 sleep state support ...................................................................... mb/google/brya: Enable ACPI S3 sleep state support Add missing HAVE_ACPI_RESUME Kconfig selection to enable S3 (suspend-to-RAM) sleep state support on Brya-based boards. Without this option, the ACPI sleepstates.asl initializes SSFG to 0x09 (supporting only S0 and S4) instead of 0x0D (supporting S0, S3, and S4). This prevents the _S3 ACPI object from being created in the DSDT, causing the operating system to not recognize S3 as an available sleep state. With this change: - SSFG is initialized to 0x0D - _S3 ACPI object is created in DSDT - Linux recognizes S3 as supported (dmesg shows "ACPI: PM: (supports S0 S3 S4 S5)") - Both s2idle and deep sleep options become available Tested on Yaviks (Nissa/PCH-N variant). Change-Id: I07cfe9327b73d28ba7f7abc7755f3b870be5be00 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90252 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Sean Rhodes: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 437632b..e5f5dc9 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -29,6 +29,7 @@ select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select I2C_TPM select INTEL_LPSS_UART_FOR_CONSOLE -- To view, visit https://review.coreboot.org/c/coreboot/+/90252?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07cfe9327b73d28ba7f7abc7755f3b870be5be00 Gerrit-Change-Number: 90252 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/samsung/lumpy: Fix HDA pin configuration issues
by Matt DeVillier (Code Review) Nov. 30, 2025

Nov. 30, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/90216?usp=email ) Change subject: mb/samsung/lumpy: Fix HDA pin configuration issues ...................................................................... mb/samsung/lumpy: Fix HDA pin configuration issues Fix several HDA pin configuration issues: - NID 0x06 (Internal Speaker): Disable jack presence detection. - NID 0x08 (Unused): Standardize to AZALIA_PIN_CFG_NC(0) which generates the canonical NC value 0x411111f0 instead of the non-standard 0x77a70037. - NID 0x09 (Internal Digital Mic): Disable jack presence detection. This resolves an issue under Linux where the speakers would keep outputting audio when the headphones were plugged in. Change-Id: If9f5781200e2d2dc6c90713caf999868f7b993a0 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90216 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/samsung/lumpy/hda_verb.c 1 file changed, 3 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Sean Rhodes: Looks good to me, approved diff --git a/src/mainboard/samsung/lumpy/hda_verb.c b/src/mainboard/samsung/lumpy/hda_verb.c index 8c538d6..aedd7b6 100644 --- a/src/mainboard/samsung/lumpy/hda_verb.c +++ b/src/mainboard/samsung/lumpy/hda_verb.c @@ -38,7 +38,7 @@ AZALIA_SPEAKER, AZALIA_OTHER_ANALOG, AZALIA_COLOR_UNKNOWN, - AZALIA_JACK_PRESENCE_DETECT, + AZALIA_NO_JACK_PRESENCE_DETECT, 15, 0 )), @@ -56,16 +56,7 @@ )), /* Pin Complex (NID 0x08) - Unused (NC) */ - AZALIA_PIN_CFG(0, 0x08, AZALIA_PIN_DESC( - AZALIA_NC, - AZALIA_MOBILE_LID_INSIDE, - AZALIA_MIC_IN, - AZALIA_OTHER_ANALOG, - AZALIA_COLOR_UNKNOWN, - AZALIA_JACK_PRESENCE_DETECT, - 3, - 7 - )), + AZALIA_PIN_CFG_NC(0), /* Pin Complex (NID 0x09) - Internal Digital Mic */ AZALIA_PIN_CFG(0, 0x09, AZALIA_PIN_DESC( @@ -74,7 +65,7 @@ AZALIA_MIC_IN, AZALIA_OTHER_DIGITAL, AZALIA_COLOR_UNKNOWN, - AZALIA_JACK_PRESENCE_DETECT, + AZALIA_NO_JACK_PRESENCE_DETECT, 3, 14 )), -- To view, visit https://review.coreboot.org/c/coreboot/+/90216?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9f5781200e2d2dc6c90713caf999868f7b993a0 Gerrit-Change-Number: 90216 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/samsung/lumpy: Convert HDA verbs to use AZALIA_PIN_DESC macros
by Matt DeVillier (Code Review) Nov. 30, 2025

Nov. 30, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/90215?usp=email ) Change subject: mb/samsung/lumpy: Convert HDA verbs to use AZALIA_PIN_DESC macros ...................................................................... mb/samsung/lumpy: Convert HDA verbs to use AZALIA_PIN_DESC macros Convert raw hexadecimal pin configuration values to use the AZALIA_PIN_DESC macro for improved readability and maintainability. All pin configurations have been verified to generate identical binary output to the original raw verbs: - NID 0x05: Headphone Jack (0x022110f0) - NID 0x06: Internal Speaker (0x901700f0) - NID 0x07: Microphone Jack (0x02a110f0) - NID 0x08: Unused/NC (0x77a70037) - NID 0x09: Unused/NC (0xb7a6003e) - NID 0x0a: SPDIF Out/NC (0x434510f0) No functional changes. Change-Id: Ib2f531575dd0e3cccf41b74e861394f21ce237af Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90215 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/samsung/lumpy/hda_verb.c 1 file changed, 70 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Sean Rhodes: Looks good to me, approved diff --git a/src/mainboard/samsung/lumpy/hda_verb.c b/src/mainboard/samsung/lumpy/hda_verb.c index b3350a1..8c538d6 100644 --- a/src/mainboard/samsung/lumpy/hda_verb.c +++ b/src/mainboard/samsung/lumpy/hda_verb.c @@ -11,30 +11,85 @@ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x152D0924 */ AZALIA_SUBVENDOR(0, 0x152D0924), + /* Padding - Power up sequence */ 0x00170500, - 0x00170500, /* Padding */ - 0x00170500, /* Padding */ - 0x00170500, /* Padding */ + 0x00170500, + 0x00170500, + 0x00170500, /* Pin Widget Verb Table */ - /* Pin Complex (NID 0x05) */ - AZALIA_PIN_CFG(0, 0x05, 0x022110f0), + /* Pin Complex (NID 0x05) - Headphone Jack */ + AZALIA_PIN_CFG(0, 0x05, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 15, + 0 + )), - /* Pin Complex (NID 0x06) */ - AZALIA_PIN_CFG(0, 0x06, 0x901700f0), + /* Pin Complex (NID 0x06) - Internal Speaker */ + AZALIA_PIN_CFG(0, 0x06, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL, + AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 15, + 0 + )), - /* Pin Complex (NID 0x07) */ - AZALIA_PIN_CFG(0, 0x07, 0x02a110f0), + /* Pin Complex (NID 0x07) - Microphone Jack */ + AZALIA_PIN_CFG(0, 0x07, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 15, + 0 + )), - /* Pin Complex (NID 0x08) */ - AZALIA_PIN_CFG(0, 0x08, 0x77a70037), + /* Pin Complex (NID 0x08) - Unused (NC) */ + AZALIA_PIN_CFG(0, 0x08, AZALIA_PIN_DESC( + AZALIA_NC, + AZALIA_MOBILE_LID_INSIDE, + AZALIA_MIC_IN, + AZALIA_OTHER_ANALOG, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 3, + 7 + )), - /* Pin Complex (NID 0x09) */ - AZALIA_PIN_CFG(0, 0x09, 0xb7a6003e), + /* Pin Complex (NID 0x09) - Internal Digital Mic */ + AZALIA_PIN_CFG(0, 0x09, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_MOBILE_LID_INSIDE, + AZALIA_MIC_IN, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 3, + 14 + )), - /* Pin Complex (NID 0x0a) */ - AZALIA_PIN_CFG(0, 0x0a, 0x434510f0), + /* Pin Complex (NID 0x0a) - SPDIF Out (NC) */ + AZALIA_PIN_CFG(0, 0x0a, AZALIA_PIN_DESC( + AZALIA_NC, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT, + AZALIA_SPDIF_OUT, + AZALIA_OPTICAL, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 15, + 0 + )), }; const u32 pc_beep_verbs[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/90215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2f531575dd0e3cccf41b74e861394f21ce237af Gerrit-Change-Number: 90215 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: drivers/efi: Exclude verstage from EFI variable store files
by Matt DeVillier (Code Review) Nov. 30, 2025

Nov. 30, 2025

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/90296?usp=email ) Change subject: drivers/efi: Exclude verstage from EFI variable store files ...................................................................... drivers/efi: Exclude verstage from EFI variable store files The EFI variable store driver (efivars.c) and option backend (option.c) require EDK2 headers which are x86-specific and not available in ARM verstage. Use 'all_x86-' instead of 'all-' to exclude verstage while keeping other x86 stages and SMM. TEST=build google/dewatt with CFR enabled Change-Id: I6d0955423cb55658725dfa3025b2118736f5e63b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/drivers/efi/Makefile.mk 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/90296/1 diff --git a/src/drivers/efi/Makefile.mk b/src/drivers/efi/Makefile.mk index 2c3cf9c..060c013 100644 --- a/src/drivers/efi/Makefile.mk +++ b/src/drivers/efi/Makefile.mk @@ -1,11 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-only -all-$(CONFIG_DRIVERS_EFI_VARIABLE_STORE) += efivars.c +all_x86-$(CONFIG_DRIVERS_EFI_VARIABLE_STORE) += efivars.c smm-$(CONFIG_DRIVERS_EFI_VARIABLE_STORE) += efivars.c ramstage-$(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES) += capsules.c -all-$(CONFIG_USE_UEFI_VARIABLE_STORE) += option.c +all_x86-$(CONFIG_USE_UEFI_VARIABLE_STORE) += option.c smm-$(CONFIG_USE_UEFI_VARIABLE_STORE) += option.c ramstage-$(CONFIG_DRIVERS_EFI_FW_INFO) += info.c -- To view, visit https://review.coreboot.org/c/coreboot/+/90296?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d0955423cb55658725dfa3025b2118736f5e63b Gerrit-Change-Number: 90296 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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[S] Change in coreboot[main]: include/option: Add verstage stub for UEFI variable store backend
by Matt DeVillier (Code Review) Nov. 30, 2025

Nov. 30, 2025

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/90295?usp=email ) Change subject: include/option: Add verstage stub for UEFI variable store backend ...................................................................... include/option: Add verstage stub for UEFI variable store backend Verstage cannot use the UEFI variable store because it runs before the SMMSTORE is initialized/available, and because the required EDK2 headers are x86-specific. Provide inline stub that returns fallback values to satisfy console_init() dependency. TEST=build google/dewatt with CFR enabled Change-Id: Icaa493692006cf3e0bb194ee3fdd9caf2f51cda1 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/include/option.h 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/90295/1 diff --git a/src/include/option.h b/src/include/option.h index bee761a..083af95 100644 --- a/src/include/option.h +++ b/src/include/option.h @@ -8,8 +8,14 @@ void sanitize_cmos(void); /* The CBFS file option backend cannot be used in SMM due to vboot - * dependencies, which are not added to SMM */ -#if CONFIG(OPTION_BACKEND_NONE) || (CONFIG(USE_CBFS_FILE_OPTION_BACKEND) && ENV_SMM) + * dependencies, which are not added to SMM. + * The UEFI variable store option backend cannot be used in verstage because: + * - Verstage runs before SMM is available (needed for SMMSTORE access) + * - EDK2 headers required for UEFI variables are x86-specific and not available + * in ARM verstage (PSP verstage). */ +#if CONFIG(OPTION_BACKEND_NONE) || \ + (CONFIG(USE_CBFS_FILE_OPTION_BACKEND) && ENV_SMM) || \ + (CONFIG(USE_UEFI_VARIABLE_STORE) && ENV_SEPARATE_VERSTAGE) static inline unsigned int get_uint_option(const char *name, const unsigned int fallback) { -- To view, visit https://review.coreboot.org/c/coreboot/+/90295?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icaa493692006cf3e0bb194ee3fdd9caf2f51cda1 Gerrit-Change-Number: 90295 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/zork: Increase size of SMMSTORE to 512KB
by Matt DeVillier (Code Review) Nov. 30, 2025

Nov. 30, 2025

Attention is currently required from: Jason Nien, Martin L Roth. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/90294?usp=email ) Change subject: mb/google/zork: Increase size of SMMSTORE to 512KB ...................................................................... mb/google/zork: Increase size of SMMSTORE to 512KB Increase size of SMMSTORE FMAP region to 512KB to ensure a large enough area is allocated to UEFI variable storage which allows for variables (such as the UEFI revocation database) to be updated via fwupd. Previously, such updates would fail with an error such as: "efivar: No space left on device". Change-Id: I71dcab53b8d570c1a3f37c11ce0b0fb3d86a5d45 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/zork/chromeos.fmd 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/90294/1 diff --git a/src/mainboard/google/zork/chromeos.fmd b/src/mainboard/google/zork/chromeos.fmd index c874c56..b90ce89 100644 --- a/src/mainboard/google/zork/chromeos.fmd +++ b/src/mainboard/google/zork/chromeos.fmd @@ -19,7 +19,7 @@ RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 20K PAD_TO_ALIGN_STORE 16K - SMMSTORE(PRESERVE) 256K + SMMSTORE(PRESERVE) 0x80000 RW_LEGACY(CBFS) WP_RO@8M 8M { RO_VPD(PRESERVE) 16K -- To view, visit https://review.coreboot.org/c/coreboot/+/90294?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I71dcab53b8d570c1a3f37c11ce0b0fb3d86a5d45 Gerrit-Change-Number: 90294 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/skyrim: Increase size of SMMSTORE to 512KB
by Matt DeVillier (Code Review) Nov. 30, 2025

Nov. 30, 2025

Attention is currently required from: Jason Nien, Martin L Roth. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/90293?usp=email ) Change subject: mb/google/skyrim: Increase size of SMMSTORE to 512KB ...................................................................... mb/google/skyrim: Increase size of SMMSTORE to 512KB Increase size of SMMSTORE FMAP region to 512KB to ensure a large enough area is allocated to UEFI variable storage which allows for variables (such as the UEFI revocation database) to be updated via fwupd. Previously, such updates would fail with an error such as: "efivar: No space left on device". Change-Id: I26b8bc194d9f28c2274b87f429821028120a4fcb Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/skyrim/chromeos.fmd 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/90293/1 diff --git a/src/mainboard/google/skyrim/chromeos.fmd b/src/mainboard/google/skyrim/chromeos.fmd index 12ad05f..3750aee 100644 --- a/src/mainboard/google/skyrim/chromeos.fmd +++ b/src/mainboard/google/skyrim/chromeos.fmd @@ -20,7 +20,7 @@ } RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 20K - SMMSTORE(PRESERVE)@0x630000 256K + SMMSTORE(PRESERVE)@0x630000 0x80000 RW_VBIOS_CACHE 64K RECOVERY_MRC_CACHE(PRESERVE) 120K RW_LEGACY(CBFS) -- To view, visit https://review.coreboot.org/c/coreboot/+/90293?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I26b8bc194d9f28c2274b87f429821028120a4fcb Gerrit-Change-Number: 90293 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com>

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