October 2025 - coreboot-gerrit

Change in coreboot[master]: mb/google/octopus/variants/dood: Disable XHCI LFPS power management
by Kenneth Chan (Code Review) Nov. 28, 2025

Nov. 28, 2025

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41143 ) Change subject: mb/google/octopus/variants/dood: Disable XHCI LFPS power management ...................................................................... mb/google/octopus/variants/dood: Disable XHCI LFPS power management LTE module is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c --- M src/mainboard/google/octopus/variants/dood/overridetree.cb M src/mainboard/google/octopus/variants/dood/variant.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41143/1 diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index 6df9f53..e1f12cf 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -149,4 +149,5 @@ # Disable compliance mode register "DisableComplianceMode" = "1" + register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index e728fe3..ab049a8 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -8,6 +8,7 @@ #include <delay.h> #include <gpio.h> #include <ec/google/chromeec/ec.h> +#include <soc/intel/apollolake/chip.h> enum { SKU_1_LTE = 1, /* Wifi + LTE */ @@ -61,3 +62,21 @@ return; } } + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + + if (cfg != NULL && cfg->disable_xhci_lfps_pm) { + switch (google_chromeec_get_board_sku()) { + case SKU_1_LTE: + case SKU_3_LTE_2CAM: + cfg->disable_xhci_lfps_pm = 1; + return; + default: + return; + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c Gerrit-Change-Number: 41143 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: ec/google/chromeec: Add fan presence helper function
by Matt DeVillier (Code Review) Oct. 31, 2025

Oct. 31, 2025

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Subrata Banik. Matt DeVillier has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/89829?usp=email ) Change subject: ec/google/chromeec: Add fan presence helper function ...................................................................... Patch Set 4: (1 comment) File src/ec/google/chromeec/ec.c: https://review.coreboot.org/c/coreboot/+/89829/comment/314b915a_f94b8dd7?us… : PS2, Line 174: resp.percent > 0 > i would think that if `EC_CMD_PWM_GET_FAN_DUTY` succeeds, […] I just checked the EC code for pre-FF boards, and EC_CMD_PWM_GET_FAN_TARGET_RPM will return invalid command if the EC fw isn't compiled with CONFIG_FANS selected, so it should be safe to use as a test for older boards. -- To view, visit https://review.coreboot.org/c/coreboot/+/89829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2a920709f0e6780c779a87568d6a8d18f817c76d Gerrit-Change-Number: 89829 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Fri, 31 Oct 2025 21:38:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add fan presence helper function
by Matt DeVillier (Code Review) Oct. 31, 2025

Oct. 31, 2025

Attention is currently required from: Boris Mittelberg, Matt DeVillier, Subrata Banik. Hello Boris Mittelberg, Caveh Jalali, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/89829?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: ec/google/chromeec: Add fan presence helper function ...................................................................... ec/google/chromeec: Add fan presence helper function Add google_chromeec_has_fan() to determine if a board has a fan or not. The function first tries the EC feature flag (EC_FEATURE_PWM_FAN), falling back to a RPM read test if the flag is unavailable. TEST=tested hooked up to a CFR option to enable auto fan control at boot, with option visibility controlled by fan presence, on a range of Chromebooks with and without PWM-controlled fans. Change-Id: I2a920709f0e6780c779a87568d6a8d18f817c76d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/89829/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/89829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2a920709f0e6780c779a87568d6a8d18f817c76d Gerrit-Change-Number: 89829 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add function to determine keyboard backlight pres...
by Matt DeVillier (Code Review) Oct. 31, 2025

Oct. 31, 2025

Attention is currently required from: Boris Mittelberg, Caveh Jalali. Matt DeVillier has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/89827?usp=email ) Change subject: ec/google/chromeec: Add function to determine keyboard backlight presence ...................................................................... Patch Set 2: (1 comment) File src/ec/google/chromeec/ec.c: https://review.coreboot.org/c/coreboot/+/89827/comment/285e97ea_b2c126af?us… : PS1, Line 120: google_chromeec_has_kbbacklight > Done if you don't mind, CB:89602 could use your input as well - TIA -- To view, visit https://review.coreboot.org/c/coreboot/+/89827?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I74daf7a63f06239d2ba3915221555af494a9340f Gerrit-Change-Number: 89827 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Fri, 31 Oct 2025 21:21:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/common/block/pcie: Move speed helper to pcie_helpers.c
by Matt DeVillier (Code Review) Oct. 31, 2025

Oct. 31, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/89763?usp=email ) Change subject: soc/intel/common/block/pcie: Move speed helper to pcie_helpers.c ...................................................................... soc/intel/common/block/pcie: Move speed helper to pcie_helpers.c The pcie_speed_control_to_upd() helper function was only available in aspm.c for PCH root port configuration. However, CPU root ports in romstage also need to convert PCIE_SPEED_control enum values to FSP UPD indices. Move pcie_speed_control_to_upd() from aspm.c to pcie_helpers.c to make it available in both romstage and ramstage. This allows both PCH and CPU root port code to use the same conversion logic without code duplication. The helper handles the mapping between devicetree enum values and FSP UPD values using the UPD_INDEX() macro (which subtracts 1): - SPEED_DEFAULT (0) -> SPEED_AUTO (1) -> UPD_INDEX = 0 - SPEED_AUTO (1) -> UPD_INDEX = 0 - SPEED_GEN1 (2) -> UPD_INDEX = 1 - SPEED_GEN2 (3) -> UPD_INDEX = 2 - SPEED_GEN3 (4) -> UPD_INDEX = 3 - SPEED_GEN4 (5) -> UPD_INDEX = 4 This accounts for the fact that FSP expects 0-based indexing where 0 = Auto, 1 = Gen1, 2 = Gen2, etc. TEST=Configured PCIE_SPEED_GEN2 for root port on mc_rpl1, booted and verified with lspci -vv that device is limited to Gen2 speed Change-Id: I0f70ad4da6f9f9e73b1c05648f0b206d5d61e07d Signed-off-by: Kilian Krause <kilian.krause(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89763 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/aspm/aspm.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h M src/soc/intel/common/block/pcie/pcie_helpers.c 3 files changed, 22 insertions(+), 9 deletions(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/aspm/aspm.c b/src/soc/intel/common/block/aspm/aspm.c index 595de84..56da3cb 100644 --- a/src/soc/intel/common/block/aspm/aspm.c +++ b/src/soc/intel/common/block/aspm/aspm.c @@ -74,15 +74,6 @@ return UPD_INDEX(l1_substates_control); } -static unsigned int pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control) -{ - /* Use auto unless overwritten */ - if (!pcie_speed_control) - return UPD_INDEX(SPEED_AUTO); - - return UPD_INDEX(pcie_speed_control); -} - void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, const struct pcie_rp_config *rp_cfg, unsigned int index) diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index 6ff07cf..6813749 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -149,6 +149,19 @@ */ uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups); +/* + * Convert PCIe speed control setting to UPD index format. + * + * Takes a PCIE_SPEED_control enum value and converts it to the corresponding + * UPD (Unit Parameter Data) index required by the firmware interface. + * + * If pcie_speed_control is 0 (uninitialized/default), the function returns + * the UPD index for SPEED_AUTO, enabling automatic speed negotiation. + * Otherwise, it returns the UPD index corresponding to the specified speed + * control value. + */ +unsigned int pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control); + /* Get PCH root port groups */ const struct pcie_rp_group *soc_get_pch_rp_groups(void); diff --git a/src/soc/intel/common/block/pcie/pcie_helpers.c b/src/soc/intel/common/block/pcie/pcie_helpers.c index 00bef42..697d1c7 100644 --- a/src/soc/intel/common/block/pcie/pcie_helpers.c +++ b/src/soc/intel/common/block/pcie/pcie_helpers.c @@ -39,3 +39,12 @@ return mask; } + +unsigned int pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control) +{ + /* Use auto unless overwritten */ + if (!pcie_speed_control) + return UPD_INDEX(SPEED_AUTO); + + return UPD_INDEX(pcie_speed_control); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/89763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f70ad4da6f9f9e73b1c05648f0b206d5d61e07d Gerrit-Change-Number: 89763 Gerrit-PatchSet: 12 Gerrit-Owner: Kilian Krause <kilian.krause(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: ec/starlabs/merlin: Move version offsets to ECDEFs
by Matt DeVillier (Code Review) Oct. 31, 2025

Oct. 31, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/89695?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: ec/starlabs/merlin: Move version offsets to ECDEFs ...................................................................... ec/starlabs/merlin: Move version offsets to ECDEFs This is a more suitable place for these definitions as it contains all other ECRAM offsets. Change-Id: I12f52b7b27b24c49b6dfc3d4b8fa0718605d2d5f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89695 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/starlabs/merlin/ec.h M src/ec/starlabs/merlin/variants/glk/ecdefs.h M src/ec/starlabs/merlin/variants/glkr/ecdefs.h M src/ec/starlabs/merlin/variants/kbl/ecdefs.h M src/ec/starlabs/merlin/variants/merlin/ecdefs.h 5 files changed, 8 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/ec.h b/src/ec/starlabs/merlin/ec.h index b22b279..39c805cb 100644 --- a/src/ec/starlabs/merlin/ec.h +++ b/src/ec/starlabs/merlin/ec.h @@ -47,10 +47,6 @@ #define ITE_CHIPID2 0x21 /* Device ID register 2 */ #define NUVOTON_CHIPID 0x27 /* Device ID register */ -/* EC RAM common offsets */ -#define ECRAM_MAJOR_VERSION 0x00 -#define ECRAM_MINOR_VERSION 0x01 - /* * CMOS Settings */ diff --git a/src/ec/starlabs/merlin/variants/glk/ecdefs.h b/src/ec/starlabs/merlin/variants/glk/ecdefs.h index a9b3025..ecdff4a 100644 --- a/src/ec/starlabs/merlin/variants/glk/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/glk/ecdefs.h @@ -11,6 +11,8 @@ #define _EC_STARLABS_GLK_EC_DEFS_H /* EC RAM offsets. */ +#define ECRAM_MAJOR_VERSION 0x00 +#define ECRAM_MINOR_VERSION 0x01 #define ECRAM_TRACKPAD_STATE 0x14 #define ECRAM_KBL_STATE 0x19 #define ECRAM_KBL_BRIGHTNESS 0x18 diff --git a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h index 028dd5f..e6dbc2f 100644 --- a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h @@ -14,6 +14,8 @@ #define NUVOTON_CHIPID_VAL 0x0004 /* EC RAM offsets. */ +#define ECRAM_MAJOR_VERSION 0x00 +#define ECRAM_MINOR_VERSION 0x01 #define ECRAM_TRACKPAD_STATE 0x14 #define ECRAM_KBL_STATE 0x16 #define ECRAM_KBL_BRIGHTNESS 0x17 diff --git a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h index 75b83c9..d5dd307 100644 --- a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h @@ -11,6 +11,8 @@ #define _EC_STARLABS_KBL_EC_DEFS_H /* EC RAM offsets */ +#define ECRAM_MAJOR_VERSION 0x00 +#define ECRAM_MINOR_VERSION 0x01 #define ECRAM_TRACKPAD_STATE 0x14 #define ECRAM_KBL_STATE 0x18 #define ECRAM_KBL_BRIGHTNESS 0x19 diff --git a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h index b712baa..75c2c62 100644 --- a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h @@ -11,6 +11,8 @@ #define _EC_STARLABS_MERLIN_EC_DEFS_H /* EC RAM offsets */ +#define ECRAM_MAJOR_VERSION 0x00 +#define ECRAM_MINOR_VERSION 0x01 #define ECRAM_KBL_BRIGHTNESS 0x09 #define ECRAM_KBL_TIMEOUT 0x10 #define ECRAM_KBL_STATE 0x0a -- To view, visit https://review.coreboot.org/c/coreboot/+/89695?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I12f52b7b27b24c49b6dfc3d4b8fa0718605d2d5f Gerrit-Change-Number: 89695 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/google/ocelot/var/matsu: Add overridetree
by Matt DeVillier (Code Review) Oct. 31, 2025

Oct. 31, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/89816?usp=email ) Change subject: mb/google/ocelot/var/matsu: Add overridetree ...................................................................... mb/google/ocelot/var/matsu: Add overridetree Add override devicetree per schematic_20251028. BUG=b:443612246 TEST=emerge-ocelot coreboot Change-Id: I0b527846ed455f46b9de1cd4bb4987aae85e0456 Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89816 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/ocelot/variants/matsu/overridetree.cb 1 file changed, 377 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved diff --git a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb index bfd637a..ded15fb 100644 --- a/src/mainboard/google/ocelot/variants/matsu/overridetree.cb +++ b/src/mainboard/google/ocelot/variants/matsu/overridetree.cb @@ -1,5 +1,382 @@ chip soc/intel/pantherlake + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB Camera + register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen1 x1 Type-A Port + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB FPS + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen1 x1 Type-A Port + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen1 x1 Type-A Con - # 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen1 x1 Type-A Con - # 2 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN" + register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN" + + # Enable EDP in PortA & HDMI in Port B + register "ddi_port_A_config" = "1" + register "ddi_port_B_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI0A] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C1 | TPM(cr50) | + #| I2C4 | Touchpad | + #| I2C5 | TouchScreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + /* Render OEM footer logo 100px above from the edge */ + .logo_bottom_margin = 100, + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .early_init = 1, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "4" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) for port C1 + register "device[3].name" = ""DD03"" + register "device[3].use_pld" = "true" + register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device generic 0 on end + end + end + + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + + ## Active Policy + # FIXME: below values are initial reference values only + register "policies.active" = "{ + [0] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(70, 97), + TEMP_PCT(65, 90), + TEMP_PCT(60, 80), + TEMP_PCT(55, 75), + TEMP_PCT(50, 65), + TEMP_PCT(45, 45), + TEMP_PCT(43, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(70, 97), + TEMP_PCT(65, 90), + TEMP_PCT(60, 80), + TEMP_PCT(55, 75), + TEMP_PCT(50, 65), + TEMP_PCT(45, 45), + TEMP_PCT(43, 30), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 50), + } + } + }" + + ## Passive Policy + # TODO: below values are initial reference values only + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + }" + + ## Critical Policy + # TODO: below values are initial reference values only + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 12000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "true" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + + device ref iaa off end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + end + end + end + + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C01)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 FPMCU"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E05)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 2"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref usb3_port2 on end + end + end + end + end + #ToDo: Probe using fw_config after decision. + device ref ufs on end + #ToDo: Probe using fw_config after decision. + device ref pcie_rp1 on + register "pcie_rp[PCIE_RP(1)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end # Gen4 M.2 SSD + + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + use cnvi_bluetooth as bluetooth_companion + device generic 0 on end + end + end # CNVi + + device ref cnvi_bluetooth on end + + # NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled. + # TPM device is under i2c1. Therefore, i2c0 needs to be enabled anyways. + device ref i2c0 on end + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E14_IRQ)" + device i2c 50 on end + end + end + device ref i2c4 on + chip drivers/i2c/hid + register "generic.hid" = ""PIXA2305"" + register "generic.desc" = ""PIXA Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)" + # NOTE: pmc_gpe0_dw2 is GPP_E in baseboard devicetree.cb. + register "generic.wake" = "GPE0_DW2_18" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 68 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)" + register "generic.wake" = "GPE0_DW2_18" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end # I2C4 + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F16_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F18)" + register "generic.reset_delay_ms" = "150" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)" + register "generic.enable_delay_ms" = "6" + register "generic.enable_off_delay_ms" = "1" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)" + register "generic.stop_off_delay_ms" = "2" + register "generic.has_power_resource" = "1" + register "generic.use_gpio_for_status" = "true" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end + end + end # I2C5 + #ToDo: Probe using fw_config after decision. + device ref hda on + chip drivers/intel/soundwire + device generic 0 on + chip drivers/soundwire/alc711 + register "desc" = ""Headset Codec"" + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2" + register "alc711_address.class" = "MIPI_CLASS_SDCA" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721" + register "disable_clkstop_sm_support" = "true" + # SoundWire Link 3 ID 1 + device generic 3.1 on end + end + end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/89816?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0b527846ed455f46b9de1cd4bb4987aae85e0456 Gerrit-Change-Number: 89816 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[L] Change in coreboot[main]: mb/google/ocelot/var/matsu: Update GPIO table
by Matt DeVillier (Code Review) Oct. 31, 2025

Oct. 31, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/89815?usp=email ) Change subject: mb/google/ocelot/var/matsu: Update GPIO table ...................................................................... mb/google/ocelot/var/matsu: Update GPIO table Configure GPIOs and related settings per schematic_20251028. BUG=b:443612246 TEST=emerge-ocelot coreboot Change-Id: I59227e435448eb6e362ab45d443fdea2f64a4233 Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89815 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/ocelot/variants/matsu/gpio.c 1 file changed, 216 insertions(+), 187 deletions(-) Approvals: build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved diff --git a/src/mainboard/google/ocelot/variants/matsu/gpio.c b/src/mainboard/google/ocelot/variants/matsu/gpio.c index 41c21a1..abbf708 100644 --- a/src/mainboard/google/ocelot/variants/matsu/gpio.c +++ b/src/mainboard/google/ocelot/variants/matsu/gpio.c @@ -31,34 +31,38 @@ /* GPP_A08: M2_GEN4_SSD_RESET_N */ PAD_CFG_GPO(GPP_A08, 1, PLTRST), - /* GPP_A09: M.2_WWAN_FCP_OFF_N */ - PAD_CFG_GPO(GPP_A09, 1, PLTRST), - /* GPP_A10: WWAN_DISABLE_N */ - PAD_CFG_GPO(GPP_A10, 1, PLTRST), - /* GPP_A11: WLAN_RST_N */ - PAD_CFG_GPO(GPP_A11, 1, PLTRST), - /* GPP_A12: WIFI_WAKE_N */ - PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL), - /* GPP_A13: PCIE_LNK_DOWN */ - PAD_CFG_NF_OWNERSHIP(GPP_A13, NONE, DEEP, NF2, ACPI), - /* GPP_A15: CODEC_GPIO_EN */ - PAD_CFG_GPO(GPP_A15, 1, DEEP), + /* GPP_A09: NC */ + PAD_NC(GPP_A09, NONE), + /* GPP_A10: NC */ + PAD_NC(GPP_A10, NONE), + /* GPP_A11: NC */ + PAD_NC(GPP_A11, NONE), + /* GPP_A12: NC */ + PAD_NC(GPP_A12, NONE), + /* GPP_A13: NC */ + PAD_NC(GPP_A13, NONE), + /* GPP_A15: NC */ + PAD_NC(GPP_A15, NONE), /* GPP_B */ /* GPP_B00: USBC_SML_CLK_PD */ PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), /* GPP_B01: USBC_SML_DATA_PD */ PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), - /* GPP_B02: ISH_I2C0_SDA_SNSR_HDR */ + /* GPP_B02: NC */ PAD_NC(GPP_B02, NONE), - /* GPP_B03: ISH_I2C0_SCL_SNSR_HDR */ + /* GPP_B03: NC */ PAD_NC(GPP_B03, NONE), - /* GPP_B04: ISH_GP_0_SNSR_HDR */ + /* GPP_B04: NC */ PAD_NC(GPP_B04, NONE), - /* GPP_B06: SOC_PDB_CTRL */ - PAD_CFG_GPO(GPP_B06, 0, DEEP), - /* GPP_B08: ISH_GP_4_SNSR_HDR */ - PAD_NC(GPP_B08, NONE), + /* GPP_B05: EC_ISH_INT_ODL */ + PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4), + /* GPP_B06: MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_B06, NONE, DEEP), + /* GPP_B07: NC */ + PAD_NC(GPP_B07, NONE), + /* GPP_B08: MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_B08, NONE, DEEP), /* GPP_B09: BT_RF_KILL_N */ PAD_CFG_GPO(GPP_B09, 1, DEEP), /* GPP_B10: NC */ @@ -69,30 +73,38 @@ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* GPP_B14: GPP_B14_DDSP_HPDB */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), - /* GPP_B16: COINLESS_MODE_SELECT */ - PAD_CFG_GPI(GPP_B16, NONE, DEEP), - /* GPP_B17: SPI_TPM_INT_N */ - PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG), - /* GPP_B20: WWAN_RST_N */ - PAD_CFG_GPO(GPP_B20, 1, PLTRST), - /* GPP_B21: TCP_RETIMER_FORCE_PWR */ - PAD_CFG_GPO(GPP_B21, 0, DEEP), - /* GPP_B24: ESPI_ALERT0_EC_R_N */ + /* GPP_B16: NC */ + PAD_NC(GPP_B16, NONE), + /* GPP_B17: NC */ + PAD_NC(GPP_B17, NONE), + /* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1), + /* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1), + /* GPP_B20: NC */ + PAD_NC(GPP_B20, NONE), + /* GPP_B21: NC */ + PAD_NC(GPP_B21, NONE), + /* GPP_B22: ISH_GP_5_SNSR_HDR */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4), + /* GPP_B23: NC */ + PAD_NC(GPP_B23, NONE), + /* GPP_B24: NC */ PAD_NC(GPP_B24, NONE), - /* GPP_B25: None */ + /* GPP_B25: NC */ PAD_NC(GPP_B25, NONE), /* GPP_C */ - /* GPP_C00: SPD_SMB_CLK */ - PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), - /* GPP_C01: SPD_SMB_DATA */ - PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), + /* GPP_C00: MIC_PWR_EN */ + PAD_CFG_GPO(GPP_C00, 1, DEEP), + /* GPP_C01: EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_C01, 1, DEEP), /* GPP_C02: NC */ PAD_NC(GPP_C02, NONE), - /* GPP_C03: TCP_LAN_SML0_SCL_R */ - PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), - /* GPP_C04: TCP_LAN_SML0_SDA_R */ - PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), + /* GPP_C03: NC */ + PAD_NC(GPP_C03, NONE), + /* GPP_C04: NC */ + PAD_NC(GPP_C04, NONE), /* GPP_C05: NC */ PAD_NC(GPP_C05, NONE), /* GPP_C06: NC */ @@ -101,102 +113,106 @@ PAD_NC(GPP_C07, NONE), /* GPP_C08: PM_SLP_S0_N_GPP_CNTRL */ PAD_CFG_GPO(GPP_C08, 1, PLTRST), - /* GPP_C09: CLKREQ0_X1_GEN4_M2_WLAN_N */ - PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), + /* GPP_C09: NC */ + PAD_NC(GPP_C09, NONE), /* GPP_C10: WIFI_RF_KILL_N */ PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* GPP_C11: CLKREQ2_X4_GEN4_DT_CEM_SLOT1_N */ - PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + /* GPP_C11: NC */ + PAD_NC(GPP_C11, NONE), /* GPP_C12: CLKREQ3_X4_GEN4_M2_SSD_N */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), - /* GPP_C13: CLKREQ4_X4_GEN4_DT_CEM_SLOT2_N */ - PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), - /* GPP_C14: CLKREQ5_X1_GEN1_GBE_LAN_N */ - PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), - /* GPP_C15: FPS_RST_N */ - PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG), - /* GPP_C16: MOD_TCSS1_LS_TX_DDC_SCL */ - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - /* GPP_C17: MOD_TCSS1_LS_RX_DDC_SDA */ - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* GPP_C18: MOD_TCSS2_LS_TX_DDC_SCL */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* GPP_C19: MOD_TCSS2_LS_RX_DDC_SDA */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* GPP_C13: NC */ + PAD_NC(GPP_C13, NONE), + /* GPP_C14: NC */ + PAD_NC(GPP_C14, NONE), + /* GPP_C15: NC */ + PAD_NC(GPP_C15, NONE), + /* GPP_C16: NC */ + PAD_NC(GPP_C16, NONE), + /* GPP_C17: NC */ + PAD_NC(GPP_C17, NONE), + /* GPP_C18: NC */ + PAD_NC(GPP_C18, NONE), + /* GPP_C19: NC */ + PAD_NC(GPP_C19, NONE), /* GPP_C22: DDPB_HDMI_CTRLCLK */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), /* GPP_C23: DDPB_HDMI_CTRLDATA */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), /* GPP_D */ - /* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */ - PAD_CFG_GPO(GPP_D01, 1, DEEP), + /* GPP_D01: NC */ + PAD_NC(GPP_D01, NONE), /* GPP_D02: SOC_WP_OD */ - PAD_CFG_GPO(GPP_D02, 0, DEEP), - /* GPP_D03: X4_SLOT_WAKE_N */ - PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL), - /* GPP_D07: ISH_UART0_RTS_N_SNSR_HDR */ + PAD_CFG_GPI(GPP_D02, NONE, DEEP), + /* GPP_D03: NC */ + PAD_NC(GPP_D03, NONE), + /* GPP_D05: ISH_UART0_ECAIC_RXD */ + PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2), + /* GPP_D06: ISH_UART0_ECAIC_TXD */ + PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2), + /* GPP_D07: NC */ PAD_NC(GPP_D07, NONE), - /* GPP_D08: ISH_UART0_CTS_N_SNSR_HDR */ + /* GPP_D08: NC */ PAD_NC(GPP_D08, NONE), - /* GPP_D09: I2S_MCLK_HDR */ - PAD_CFG_NF(GPP_D09, NONE, DEEP, NF1), - /* GPP_D10: HDA_BCLK (HDR) */ - PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), - /* GPP_D11: HDA_SYNC (HDR) */ - PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1), - /* GPP_D12: HDA_SDO (HDR) */ - PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), - /* GPP_D13: HDA_SDI0 (HDR) */ - PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), - /* GPP_D16: HDA_RST_N (HDR) */ - PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), - /* GPP_D17: HDA_SDI1 (HDR) */ - PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), - /* GPP_D19: NC */ - PAD_NC(GPP_D19, NONE), - /* GPP_D21: GPP_D21_UFS_REFCLK_R */ + /* GPP_D09: NC */ + PAD_NC(GPP_D09, NONE), + /* GPP_D10: NC */ + PAD_NC(GPP_D10, NONE), + /* GPP_D11: NC */ + PAD_NC(GPP_D11, NONE), + /* GPP_D12: NC */ + PAD_NC(GPP_D12, NONE), + /* GPP_D13: NC */ + PAD_NC(GPP_D13, NONE), + /* GPP_D16: DMIC_CLK_A1 */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3), + /* GPP_D17: DMIC_DATA_1 */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3), + /* GPP_D19: TCHSCR_RPT_EN */ + PAD_CFG_GPO(GPP_D19, 0, PLTRST), + /* GPP_D21: GPP_D21_UFS_REFCLK */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* GPP_E */ - /* GPP_E01: PM_SLP_DRAM_N */ - PAD_CFG_NF(GPP_E01, NONE, DEEP, NF2), + /* GPP_E01: NC */ + PAD_NC(GPP_E01, NONE), /* GPP_E02: NC */ PAD_NC(GPP_E02, NONE), - /* GPP_E03: X4_DT_PCIE_RST_N */ - PAD_CFG_GPO(GPP_E03, 1, PLTRST), + /* GPP_E03: NC */ + PAD_NC(GPP_E03, NONE), /* GPP_E05: GPP_E5_FPS_PWREN */ PAD_CFG_GPO(GPP_E05, 1, DEEP), - /* GPP_E06: GPP_E6_PEN_DETECT */ - PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, LEVEL, ACPI), - /* GPP_E07: LAN_GPIO_RST_N */ - PAD_CFG_GPO(GPP_E07, 1, PLTRST), + /* GPP_E06: NC */ + PAD_NC(GPP_E06, NONE), + /* GPP_E07: NC */ + PAD_NC(GPP_E07, NONE), /* GPP_E08: EC_SOC_INT_ODL */ - PAD_CFG_GPI(GPP_E08, NONE, DEEP), - /* GPP_E09: USB_FP_CONN_1_CONN_2_OC0_N */ + PAD_CFG_GPI_APIC_LOCK(GPP_E08, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E09: USB_A_OC_ODL */ PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1), - /* GPP_E10: M2_UFS_DET_SEL_N */ - PAD_CFG_GPI(GPP_E10, NONE, DEEP), - /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */ - PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3), - /* GPP_E12: THC_I2C0_SCL_TCH_PNL1 */ - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3), - /* GPP_E13: THC_I2C0_SDA_TCH_PNL1 */ - PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3), - /* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */ - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3), - /* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */ - PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3), - /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */ - PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1), - /* GPP_E17: GPP_E17_GSPI0A_CS0 */ - PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5), - /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), - /* GPP_E19: FPS_INT_N */ - PAD_CFG_GPI_IRQ_WAKE(GPP_E19, NONE, PWROK, LEVEL, INVERT), - /* GPP_E20: FPS_FW_UPDATE */ - PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG), + /* GPP_E10: NC */ + PAD_NC(GPP_E10, NONE), + /* GPP_E11: NC */ + PAD_NC(GPP_E11, NONE), + /* GPP_E12: I2C_TCHPAD_SCL */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8), + /* GPP_E13: I2C_TCHPAD_SDA */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8), + /* GPP_E14: GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E14, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E15: NC */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16: NC */ + PAD_NC(GPP_E16, NONE), + /* GPP_E17: NC */ + PAD_NC(GPP_E17, NONE), + /* GPP_E18: TCHPAD_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, INVERT), + /* GPP_E19: NC */ + PAD_NC(GPP_E19, NONE), + /* GPP_E20: NC */ + PAD_NC(GPP_E20, NONE), /* GPP_E21: I2C_PMC_PD_INT_N */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* GPP_E22: NC */ @@ -215,86 +231,105 @@ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1), /* GPP_F05: CRF_CLKREQ_R */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), - /* GPP_F06: DISC_WLAN_WWAN_COEX3 */ - PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), - /* GPP_F07: FUSA_DIAGTEST_EN_HDR */ - PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2), - /* GPP_F08: TCH_PNL1_PWR_EN */ + /* GPP_F06: NC */ + PAD_NC(GPP_F06, NONE), + /* GPP_F07: NC */ + PAD_NC(GPP_F07, NONE), + /* GPP_F08: TCHSCR_PNL1_PWR_EN */ PAD_CFG_GPO(GPP_F08, 1, PLTRST), /* GPP_F09: M2_UFS_RST_N */ PAD_CFG_GPO(GPP_F09, 1, DEEP), - /* GPP_F10: X4_PCIE_SLOT1_PWR_EN */ - PAD_CFG_GPO(GPP_F10, 1, PLTRST), - /* GPP_F11: THC1_SPI2_CLK_TCH_PNL2 */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF11), - /* GPP_F12: THC_I2C1_SCL_TCH_PAD */ + /* GPP_F10: ISH_ACCEL_MB_INT_L*/ + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF8), + /* GPP_F11: NC */ + PAD_NC(GPP_F11, NONE), + /* GPP_F12: TCHSCR_I2C5_SCL */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), - /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ + /* GPP_F13: TCHSCR_I2C5_SDA */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), - /* GPP_F14: GPP_F14_GPSI0A_MOSI */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8), - /* GPP_F15: GPP_F15_GSPI0A_MISO */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8), - /* GPP_F16: GPP_F16_GSPI0A_CLK */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8), - /* GPP_F17: CODEC_IRQ_HDR */ - PAD_CFG_GPI(GPP_F17, NONE, DEEP), - /* GPP_F18: TCH_PAD_INT_N */ - PAD_CFG_GPI_APIC_DRIVER(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* GPP_F14: NC */ + PAD_NC(GPP_F14, NONE), + /* GPP_F15: NC */ + PAD_NC(GPP_F15, NONE), + /* GPP_F16: SOC_TCHSCR_INT */ + PAD_CFG_GPI_APIC(GPP_F16, NONE, PLTRST, LEVEL, NONE), + /* GPP_F17: NC */ + PAD_NC(GPP_F17, NONE), + /* GPP_F18: TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_F18, 1, DEEP), /* GPP_F19: NC */ PAD_NC(GPP_F19, NONE), /* GPP_F20: CSE_EARLY_SW */ PAD_CFG_GPI(GPP_F20, NONE, DEEP), - /* GPP_F22: THC1_SPI2_DSYNC */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3), + /* GPP_F22: NC */ + PAD_NC(GPP_F22, NONE), + /* GPP_F23: NC */ + PAD_NC(GPP_F23, NONE), /* GPP_H */ /* GPP_H00: NC */ PAD_NC(GPP_H00, NONE), - /* GPP_H01: M2_UFS_SLP_N */ - PAD_CFG_GPO(GPP_H01, 1, DEEP), - /* GPP_H02: DEBUG_TRACE_PNP */ - PAD_CFG_GPO(GPP_H02, 1, PLTRST), - /* GPP_H03: MIC MUTE */ - PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1), - /* GPP_H04: CNV_MFUART2_RXD */ - PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1), - /* GPP_H05: CNV_MFUART2_TXD */ - PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1), - /* GPP_H06: I2C3_SCL_AUDIO_HDR */ - PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), - /* GPP_H07: I2C3_SDA_AUDIO_HDR */ - PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_H01: NC */ + PAD_NC(GPP_H01, NONE), + /* GPP_H02: NC */ + PAD_NC(GPP_H02, NONE), + /* GPP_H03: NC */ + PAD_NC(GPP_H03, NONE), + /* GPP_H04: NC */ + PAD_NC(GPP_H04, NONE), + /* GPP_H05: NC */ + PAD_NC(GPP_H05, NONE), + /* GPP_H06: NC */ + PAD_NC(GPP_H06, NONE), + /* GPP_H07: NC */ + PAD_NC(GPP_H07, NONE), /* GPP_H08: SOC_BIOS_LOG_TTK_UART_RX */ PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */ PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), - /* GPP_H10: UART0_BUF_RTS */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), - /* GPP_H11: UART0_BUF_CTS */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), - /* GPP_H13: CPU_C10_GATE_N_R */ - PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), - /* GPP_H14: ISH_I3C1_SDA_SNSR_HDR */ + /* GPP_H10: NC */ + PAD_NC(GPP_H10, NONE), + /* GPP_H11: NC */ + PAD_NC(GPP_H11, NONE), + /* GPP_H13: NC */ + PAD_NC(GPP_H13, NONE), + /* GPP_H14: NC */ PAD_NC(GPP_H14, NONE), - /* GPP_H15: ISH_I3C1_SCL_SNSR_HDR */ + /* GPP_H15: NC */ PAD_NC(GPP_H15, NONE), - /* GPP_H17: MIC MUTE LED */ - PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* GPP_H17: NC */ + PAD_NC(GPP_H17, NONE), /* GPP_H18: GEN4_SSD_PWREN */ PAD_CFG_GPO(GPP_H18, 1, DEEP), - /* GPP_H19: I3C0_SDA_HDR */ - PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2), - /* GPP_H20: I3C0_SCL_HDR */ - PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2), - /* GPP_H21: I2C1_SDA_TTK_CHROME */ + /* GPP_H19: NC */ + PAD_NC(GPP_H19, NONE), + /* GPP_H20: NC */ + PAD_NC(GPP_H20, NONE), + /* GPP_H21: SOC_I2C_GSC_SDA */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), - /* GPP_H22: I2C1_SCL_TTK_CHROME */ + /* GPP_H22: SOC_I2C_GSC_SCL */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), - /* GPP_H23: TP */ - PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), - /* GPP_H24: TP */ - PAD_CFG_NF(GPP_H24, NONE, DEEP, NF1), + /* GPP_H23: MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H23, NONE, DEEP), + /* GPP_H24: MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H24, NONE, DEEP), + + /* GPP_S00: SNDW3_CLK_CODEC */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), + /* GPP_S01: SNDW3_DATA0_CODEC */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), + /* GPP_S02: SNDW3_DATA1_CODEC */ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1), + /* GPP_S03: SNDW3_DATA2_CODEC */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1), + /* GPP_S04: DMIC_CLK_A0 */ + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5), + /* GPP_S05: DMIC_DATA_0 */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5), + /* GPP_S06: NC */ + PAD_NC(GPP_S06, NONE), + /* GPP_S07: NC */ + PAD_NC(GPP_S07, NONE), /* GPP_V */ /* GPP_V00: PM_BATLOW_N */ @@ -313,14 +348,14 @@ PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), /* GPP_V07: M.2_BTWIFI_SUS_CLK_LS */ PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1), - /* GPP_V08: SLP_WLAN_N */ + /* GPP_V08: RSVD */ PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), /* GPP_V09: PM_SLP_S5_N */ PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), - /* GPP_V10: LANPHYPC_R_N */ - PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), - /* GPP_V11: PM_SLP_LAN_N */ - PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), + /* GPP_V10: NC */ + PAD_NC(GPP_V10, NONE), + /* GPP_V11: NC */ + PAD_NC(GPP_V11, NONE), /* GPP_V12: WAKE_N */ PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), /* GPP_V13: GPP_V13_CATERR_N */ @@ -335,30 +370,24 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* GPP_B17: SPI_TPM_INT_N */ - PAD_CFG_GPI_APIC(GPP_B17, NONE, DEEP, LEVEL, INVERT), - /* GPP_H06: I2C3_SDA_PSS */ - PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), - /* GPP_H07: I2C3_SCL_PSS */ - PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_E14: GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E14, NONE, PLTRST, LEVEL, INVERT), /* GPP_H08: SOC_BIOS_LOG_TTK_UART_RX */ PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */ PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), - /* GPP_H21: I2C1_SDA_TTK_CHROME */ + /* GPP_H21: SOC_I2C_GSC_SDA */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), - /* GPP_H22: I2C1_SCL_TTK_CHROME */ + /* GPP_H22: SOC_I2C_GSC_SCL */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), }; /* Pad configuration in romstage */ static const struct pad_config romstage_gpio_table[] = { - /* GPP_C00: SPD_SMB_CLK */ - PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), - /* GPP_C01: SPD_SMB_DATA */ - PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), - /* GPP_C15: FPS_RST_N */ - PAD_CFG_GPO(GPP_C15, 0, PLTRST), + /* GPP_H18: GEN4_SSD_PWREN */ + PAD_CFG_GPO(GPP_H18, 1, PLTRST), + /* GPP_A08: M2_GEN4_SSD_RESET_N */ + PAD_CFG_GPO(GPP_A08, 1, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/89815?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I59227e435448eb6e362ab45d443fdea2f64a4233 Gerrit-Change-Number: 89815 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/fatcat/var/moonstone: Support new schematic changes
by Matt DeVillier (Code Review) Oct. 31, 2025

Oct. 31, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/89819?usp=email ) Change subject: mb/google/fatcat/var/moonstone: Support new schematic changes ...................................................................... mb/google/fatcat/var/moonstone: Support new schematic changes Based on the Moonstone Schematic Proto 2.0 design, disable Thunderbolt support for TCSS_PORT0 on the MB and TCSS_PORT1 on the DB. Schematic: Kinmen(ZDQ)_Proto2.0_Moonstone_1014.pdf BUG＝none TEST=emerge-fatcat coreboot Change-Id: Ie9acb9d68234b2d8bfc9392cf89d581de8c54a08 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89819 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/fatcat/variants/moonstone/overridetree.cb 1 file changed, 0 insertions(+), 11 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb index d2487ac..2e8e44e 100644 --- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb @@ -217,10 +217,6 @@ end device ref iaa off end - device ref tbt_pcie_rp0 on end - device ref tbt_pcie_rp1 on - probe IO_PORT USB3C - end device ref tbt_pcie_rp2 on probe IO_PORT USB2A2C_HDMI end @@ -262,13 +258,6 @@ end end - device ref tcss_dma0 on - chip drivers/intel/usb4/retimer - register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - use tcss_usb3_port0 as dfp[0].typec_port - device generic 0 on end - end - end device ref tcss_dma1 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" -- To view, visit https://review.coreboot.org/c/coreboot/+/89819?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9acb9d68234b2d8bfc9392cf89d581de8c54a08 Gerrit-Change-Number: 89819 Gerrit-PatchSet: 3 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in coreboot[main]: vc/intel/fsp: Update WCL FSP headers to 3344_03
by Matt DeVillier (Code Review) Oct. 31, 2025

Oct. 31, 2025

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/89311?usp=email ) Change subject: vc/intel/fsp: Update WCL FSP headers to 3344_03 ...................................................................... vc/intel/fsp: Update WCL FSP headers to 3344_03 Update header files for FSP for wildcatlake platform from FSP 3266_02 to FSP 3344_03 Details: -Update FspmUpd.h: Add below variable -Update definition of SerialIoUartDebugAutoFlow -Add WREQT, IsWckIdleExitEnabled, LogoPixelHeight , LogoPixelWidth, LogoXPosition, LogoYPosition ,VgaGraphicsMode12ImagePtr -Update FspsUpd.h: - Add PchHdaMicPrivacyMode BUG=b:447530895 TEST=Able to build google/ocelot with the partial header changes Change-Id: Id5b37434396d4d70f4269a1bf82aa3d6935a9d41 Signed-off-by: Alok Agarwal <alok.agarwal(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89311 Reviewed-by: Pranava Y N <pranavayn(a)google.com> Reviewed-by: Avi Uday <aviuday(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h 1 file changed, 109 insertions(+), 79 deletions(-) Approvals: build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved Avi Uday: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h index 449a254..dace758 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h @@ -57,8 +57,7 @@ /** Offset 0x0060 - Serial Io Uart Debug Mode Select SerialIo Uart Controller mode - 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, - 4:SerialIoUartSkipInit + 1:SerialIoUartPci, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartDebugMode; @@ -941,8 +940,8 @@ **/ UINT8 DIMMRONT; -/** Offset 0x0260 - Write Drive Strength/Equalization 2D - Enables/Disable Write Drive Strength/Equalization 2D +/** Offset 0x0260 - Write Drive Strength Training + Enables/Disable Write Drive Strength Training $EN_DIS **/ UINT8 WRDSEQT; @@ -1241,9 +1240,11 @@ **/ UINT8 ChHashInterleaveBit; -/** Offset 0x02BB - Reserved +/** Offset 0x02BB - Write Equalization Training + Enables/Disables Write Equalization Training + $EN_DIS **/ - UINT8 Reserved25; + UINT8 WREQT; /** Offset 0x02BC - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to @@ -1253,7 +1254,7 @@ /** Offset 0x02BE - Reserved **/ - UINT8 Reserved26; + UINT8 Reserved25; /** Offset 0x02BF - Throttler CKEMin Timer Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). @@ -1332,7 +1333,7 @@ /** Offset 0x02CB - Reserved **/ - UINT8 Reserved27[5]; + UINT8 Reserved26[5]; /** Offset 0x02D0 - DDR Phy Safe Mode Support DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]: @@ -1354,7 +1355,7 @@ /** Offset 0x02D6 - Reserved **/ - UINT8 Reserved28[8]; + UINT8 Reserved27[8]; /** Offset 0x02DE - RMTLoopCount Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO @@ -1390,7 +1391,7 @@ /** Offset 0x02E7 - Reserved **/ - UINT8 Reserved29; + UINT8 Reserved28; /** Offset 0x02E8 - Margin limit check L2 Margin limit check L2 threshold: 100=Default @@ -1405,7 +1406,7 @@ /** Offset 0x02EB - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved29; /** Offset 0x02EC - LP5 Command Pins Mapping BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller @@ -1427,7 +1428,7 @@ /** Offset 0x02EF - Reserved **/ - UINT8 Reserved31[43]; + UINT8 Reserved30[43]; /** Offset 0x031A - Read Vref Decap Training* Enable/Disable Read Timing Centering Training with SR stress* @@ -1447,9 +1448,15 @@ **/ UINT8 Use1p5ReadPostamble; -/** Offset 0x031D - Reserved +/** Offset 0x031D - IsWckIdleExitEnabled + Enables/Disables WCK Idle Exit + $EN_DIS **/ - UINT8 Reserved32[18]; + UINT8 IsWckIdleExitEnabled; + +/** Offset 0x031E - Reserved +**/ + UINT8 Reserved31[17]; /** Offset 0x032F - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile @@ -1473,7 +1480,7 @@ /** Offset 0x0341 - Reserved **/ - UINT8 Reserved33; + UINT8 Reserved32; /** Offset 0x0342 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -1601,7 +1608,7 @@ /** Offset 0x04D6 - Reserved **/ - UINT8 Reserved34[2]; + UINT8 Reserved33[2]; /** Offset 0x04D8 - DMIC<N> ClkA Pin Muxing (N - DMIC number) Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* @@ -1616,7 +1623,7 @@ /** Offset 0x04E1 - Reserved **/ - UINT8 Reserved35[3]; + UINT8 Reserved34[3]; /** Offset 0x04E4 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* @@ -1630,7 +1637,7 @@ /** Offset 0x04F3 - Reserved **/ - UINT8 Reserved36[117]; + UINT8 Reserved35[117]; /** Offset 0x0568 - Enable HD Audio SoundWire#N Link Enable/disable HD Audio SNDW#N link. Muxed with HDA. @@ -1651,7 +1658,7 @@ /** Offset 0x056F - Reserved **/ - UINT8 Reserved37[45]; + UINT8 Reserved36[45]; /** Offset 0x059C - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. @@ -1661,7 +1668,7 @@ /** Offset 0x059D - Reserved **/ - UINT8 Reserved38[5]; + UINT8 Reserved37[5]; /** Offset 0x05A2 - HDA Power/Clock Gating (PGD/CGD) Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: @@ -1672,7 +1679,7 @@ /** Offset 0x05A3 - Reserved **/ - UINT8 Reserved39; + UINT8 Reserved38; /** Offset 0x05A4 - Audio Sub System IDs Set default Audio Sub System IDs. If its set to 0 then value from Strap is used. @@ -1681,7 +1688,7 @@ /** Offset 0x05A8 - Reserved **/ - UINT8 Reserved40; + UINT8 Reserved39; /** Offset 0x05A9 - PCH LPC Enhance the port 8xh decoding Original LPC only decodes one byte of port 80h. @@ -1701,7 +1708,7 @@ /** Offset 0x05CE - Reserved **/ - UINT8 Reserved41[46]; + UINT8 Reserved40[46]; /** Offset 0x05FC - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -1717,7 +1724,7 @@ /** Offset 0x0601 - Reserved **/ - UINT8 Reserved42[3]; + UINT8 Reserved41[3]; /** Offset 0x0604 - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode @@ -1794,7 +1801,7 @@ /** Offset 0x061A - Reserved **/ - UINT8 Reserved43[2]; + UINT8 Reserved42[2]; /** Offset 0x061C - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI @@ -1847,7 +1854,7 @@ /** Offset 0x0624 - Reserved **/ - UINT8 Reserved44[2]; + UINT8 Reserved43[2]; /** Offset 0x0626 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. @@ -1868,7 +1875,7 @@ /** Offset 0x062A - Reserved **/ - UINT8 Reserved45[26]; + UINT8 Reserved44[26]; /** Offset 0x0644 - Enable SMBus Enable/disable SMBus controller. @@ -1889,7 +1896,7 @@ /** Offset 0x0647 - Reserved **/ - UINT8 Reserved46; + UINT8 Reserved45; /** Offset 0x0648 - SMBUS Base Address SMBUS Base Address (IO space). @@ -1904,7 +1911,7 @@ /** Offset 0x064B - Reserved **/ - UINT8 Reserved47[13]; + UINT8 Reserved46[13]; /** Offset 0x0658 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -1927,7 +1934,7 @@ /** Offset 0x065B - Reserved **/ - UINT8 Reserved48[18]; + UINT8 Reserved47[18]; /** Offset 0x066D - Over clocking support Over clocking support; 0: Disable; 1: Enable @@ -1937,7 +1944,7 @@ /** Offset 0x066E - Reserved **/ - UINT8 Reserved49; + UINT8 Reserved48; /** Offset 0x066F - Realtime Memory Timing 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform @@ -2000,7 +2007,7 @@ /** Offset 0x067B - Reserved **/ - UINT8 Reserved50[2]; + UINT8 Reserved49[2]; /** Offset 0x067D - TjMax Offset TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support @@ -2010,7 +2017,7 @@ /** Offset 0x067E - Reserved **/ - UINT8 Reserved51[48]; + UINT8 Reserved50[48]; /** Offset 0x06AE - Core VF Point Offset Array used to specifies the Core Voltage Offset applied to the each selected VF @@ -2032,7 +2039,7 @@ /** Offset 0x06EA - Reserved **/ - UINT8 Reserved52[26]; + UINT8 Reserved51[26]; /** Offset 0x0704 - Per Core Max Ratio override Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new @@ -2043,7 +2050,7 @@ /** Offset 0x0705 - Reserved **/ - UINT8 Reserved53[25]; + UINT8 Reserved52[25]; /** Offset 0x071E - Per Core Current Max Ratio Array for the Per Core Max Ratio @@ -2052,7 +2059,7 @@ /** Offset 0x0726 - Reserved **/ - UINT8 Reserved54[8]; + UINT8 Reserved53[8]; /** Offset 0x072E - Pvd Ratio Threshold for SOC/CPU die Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio @@ -2065,7 +2072,7 @@ /** Offset 0x072F - Reserved **/ - UINT8 Reserved55[65]; + UINT8 Reserved54[65]; /** Offset 0x0770 - CPU BCLK OC Frequency CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz 0 - Auto. Range is @@ -2075,7 +2082,7 @@ /** Offset 0x0774 - Reserved **/ - UINT8 Reserved56[13]; + UINT8 Reserved55[13]; /** Offset 0x0781 - Avx2 Voltage Guardband Scaling Factor AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in @@ -2090,7 +2097,7 @@ /** Offset 0x0783 - Reserved **/ - UINT8 Reserved57[5]; + UINT8 Reserved56[5]; /** Offset 0x0788 - Enable PCH ISH Controller 0: Disable, 1: Enable (Default) ISH Controller @@ -2100,7 +2107,7 @@ /** Offset 0x0789 - Reserved **/ - UINT8 Reserved58; + UINT8 Reserved57; /** Offset 0x078A - BiosSize The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != @@ -2135,7 +2142,7 @@ /** Offset 0x0790 - Reserved **/ - UINT8 Reserved59[3]; + UINT8 Reserved58[3]; /** Offset 0x0793 - MKTME Key-Id Bits Override Enable Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager @@ -2146,7 +2153,7 @@ /** Offset 0x0794 - Reserved **/ - UINT8 Reserved60[4]; + UINT8 Reserved59[4]; /** Offset 0x0798 - TME Exclude Base Address TME Exclude Base Address. @@ -2160,7 +2167,7 @@ /** Offset 0x07A8 - Reserved **/ - UINT8 Reserved61[14]; + UINT8 Reserved60[14]; /** Offset 0x07B6 - BIST on Reset Enable/Disable BIST (Built-In Self Test) on reset. 0: Disable; 1: Enable. @@ -2170,7 +2177,7 @@ /** Offset 0x07B7 - Reserved **/ - UINT8 Reserved62; + UINT8 Reserved61; /** Offset 0x07B8 - Enable or Disable VMX Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities @@ -2240,7 +2247,7 @@ /** Offset 0x07C2 - Reserved **/ - UINT8 Reserved63[6]; + UINT8 Reserved62[6]; /** Offset 0x07C8 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -2268,7 +2275,7 @@ /** Offset 0x07D2 - Reserved **/ - UINT8 Reserved64[98]; + UINT8 Reserved63[98]; /** Offset 0x0834 - SinitMemorySize Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable @@ -2335,7 +2342,7 @@ /** Offset 0x086E - Reserved **/ - UINT8 Reserved65[2]; + UINT8 Reserved64[2]; /** Offset 0x0870 - Platform Power Pmax PSYS PMax power, defined in 1/8 Watt increments. 0 - Auto Specified in 1/8 @@ -2387,7 +2394,7 @@ /** Offset 0x08BA - Reserved **/ - UINT8 Reserved66[26]; + UINT8 Reserved65[26]; /** Offset 0x08D4 - Icc Max limit Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous @@ -2399,7 +2406,7 @@ /** Offset 0x08E0 - Reserved **/ - UINT8 Reserved67[42]; + UINT8 Reserved66[42]; /** Offset 0x090A - Thermal Design Current enable/disable Thermal Design Current enable/disable; 0: Disable; 1: Enable. [0] for IA, @@ -2409,7 +2416,7 @@ /** Offset 0x0910 - Reserved **/ - UINT8 Reserved68[6]; + UINT8 Reserved67[6]; /** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains This option needs to be configured to reduce acoustic noise during deeper C states. @@ -2431,7 +2438,7 @@ /** Offset 0x0922 - Reserved **/ - UINT8 Reserved69[6]; + UINT8 Reserved68[6]; /** Offset 0x0928 - Thermal Design Current time window Auto = 0 is default. Range is from 1ms to 448s. 0: Auto. [0] for IA, [1] @@ -2447,7 +2454,7 @@ /** Offset 0x0946 - Reserved **/ - UINT8 Reserved70[2]; + UINT8 Reserved69[2]; /** Offset 0x0948 - DLVR RFI Enable Enable/Disable DLVR RFI frequency hopping. 0: Disable; 1: Enable. @@ -2467,7 +2474,7 @@ /** Offset 0x094B - Reserved **/ - UINT8 Reserved71[11]; + UINT8 Reserved70[11]; /** Offset 0x0956 - VR Fast Vmode ICC Limit support Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds @@ -2492,7 +2499,7 @@ /** Offset 0x096E - Reserved **/ - UINT8 Reserved72[28]; + UINT8 Reserved71[28]; /** Offset 0x098A - PCH Port80 Route Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. @@ -2509,7 +2516,7 @@ /** Offset 0x098C - Reserved **/ - UINT8 Reserved73[4]; + UINT8 Reserved72[4]; /** Offset 0x0990 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -2535,7 +2542,7 @@ /** Offset 0x0997 - Reserved **/ - UINT8 Reserved74; + UINT8 Reserved73; /** Offset 0x0998 - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine @@ -2544,7 +2551,7 @@ /** Offset 0x09BC - Reserved **/ - UINT8 Reserved75[20]; + UINT8 Reserved74[20]; /** Offset 0x09D0 - MMIO Size Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB @@ -2559,7 +2566,7 @@ /** Offset 0x09D4 - Reserved **/ - UINT8 Reserved76[36]; + UINT8 Reserved75[36]; /** Offset 0x09F8 - Enable above 4GB MMIO resource support Enable/disable above 4GB MMIO resource support @@ -2575,7 +2582,7 @@ /** Offset 0x09FA - Reserved **/ - UINT8 Reserved77[10]; + UINT8 Reserved76[10]; /** Offset 0x0A04 - Enable/Disable CrashLog Device Enable or Disable CrashLog/Telemetry Device 0- Disable, 1- Enable @@ -2585,7 +2592,7 @@ /** Offset 0x0A08 - Reserved **/ - UINT8 Reserved78[20]; + UINT8 Reserved77[20]; /** Offset 0x0A1C - Platform Debug Option Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n @@ -2602,7 +2609,7 @@ /** Offset 0x0A1D - Reserved **/ - UINT8 Reserved79[14]; + UINT8 Reserved78[14]; /** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI @@ -2612,7 +2619,7 @@ /** Offset 0x0A2C - Reserved **/ - UINT8 Reserved80[2]; + UINT8 Reserved79[2]; /** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device 0(Default)=Disabled,1=eDP, 2=MIPI DSI @@ -2706,7 +2713,7 @@ /** Offset 0x0A3D - Reserved **/ - UINT8 Reserved81[3]; + UINT8 Reserved80[3]; /** Offset 0x0A40 - Temporary MMIO address for GMADR The reference code will use this as Temporary MMIO address space to access GMADR @@ -2725,7 +2732,7 @@ /** Offset 0x0A50 - Reserved **/ - UINT8 Reserved82[2]; + UINT8 Reserved81[2]; /** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression 0=Disable, 1(Default)=Enable @@ -2755,7 +2762,7 @@ /** Offset 0x0A56 - Reserved **/ - UINT8 Reserved83[2]; + UINT8 Reserved82[2]; /** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size Size of Internal Graphics VBT Image @@ -2764,7 +2771,7 @@ /** Offset 0x0A5C - Reserved **/ - UINT8 Reserved84[4]; + UINT8 Reserved83[4]; /** Offset 0x0A60 - Graphics Configuration Ptr Points to VBT @@ -2785,14 +2792,37 @@ /** Offset 0x0A71 - Control SOL VGA Initialition sequence Initialise SOL Init, BIT0 - (0 : Disable VGA Support, 1 : Enable VGA Support),, BIT1 - (0 : VGA Text Mode 3, 1 : VGA Graphics Mode 12), BIT2 - (0 : VGA Exit Supported, - 1: NO VGA Exit) + 1: NO VGA Exit), BIT3 - (0 : VGA Init During Display Init, 1 - VGA Init During + MRC Cold Boot), BIT4 - (0 : Enable Progress Bar, 1 : Disable Progress Bar) 0:VGA Disable, 1:Mode 3 VGA, 2:Mode 12 VGA **/ UINT8 VgaInitControl; -/** Offset 0x0A72 - Reserved +/** Offset 0x0A72 - SOL VGA Graphics Mode 12 LogoPixelHeight + Heigh of VGA Graphics Mode 12 Logo **/ - UINT8 Reserved85[16]; + UINT16 LogoPixelHeight; + +/** Offset 0x0A74 - SOL VGA Graphics Mode 12 LogoPixelWidth + Width of VGA Graphics Mode 12 Logo +**/ + UINT16 LogoPixelWidth; + +/** Offset 0x0A76 - SOL VGA Graphics Mode 12 Image X Position + X position of Image on Display +**/ + UINT16 LogoXPosition; + +/** Offset 0x0A78 - SOL VGA Graphics Mode 12 Image Pointer + Points to SOL VGA Graphics Graphics 12 Image, VgaPlanarImage200x58[4][58][25] for + 58Hx200W as example, +**/ + UINT64 VgaGraphicsMode12ImagePtr; + +/** Offset 0x0A80 - SOL VGA Graphics Mode 12 Image Y Position + Y position of Image on Display +**/ + UINT16 LogoYPosition; /** Offset 0x0A82 - TCSS USB HOST (xHCI) Enable Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below @@ -2802,7 +2832,7 @@ /** Offset 0x0A83 - Reserved **/ - UINT8 Reserved86[4]; + UINT8 Reserved84[4]; /** Offset 0x0A87 - TCSS Type C Port 0 Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, @@ -2834,7 +2864,7 @@ /** Offset 0x0A8B - Reserved **/ - UINT8 Reserved87; + UINT8 Reserved85; /** Offset 0x0A8C - TypeC port GPIO setting GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined @@ -2902,7 +2932,7 @@ /** Offset 0x0AC9 - Reserved **/ - UINT8 Reserved88; + UINT8 Reserved86; /** Offset 0x0ACA - DLL Weak Lock Support Enables/Disable DLL Weak Lock Support @@ -2912,7 +2942,7 @@ /** Offset 0x0ACB - Reserved **/ - UINT8 Reserved89; + UINT8 Reserved87; /** Offset 0x0ACC - Rx DQS Delay Comp Support Enables/Disable Rx DQS Delay Comp Support @@ -2922,7 +2952,7 @@ /** Offset 0x0ACD - Reserved **/ - UINT8 Reserved90[2]; + UINT8 Reserved88[2]; /** Offset 0x0ACF - Mrc Failure On Unsupported Dimm Enables/Disable Mrc Failure On Unsupported Dimm @@ -2932,7 +2962,7 @@ /** Offset 0x0AD0 - Reserved **/ - UINT8 Reserved91[4]; + UINT8 Reserved89[4]; /** Offset 0x0AD4 - DynamicMemoryBoost Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is @@ -2950,7 +2980,7 @@ /** Offset 0x0ADC - Reserved **/ - UINT8 Reserved92[9]; + UINT8 Reserved90[9]; /** Offset 0x0AE5 - Vref Offset Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset @@ -2961,7 +2991,7 @@ /** Offset 0x0AE6 - Reserved **/ - UINT8 Reserved93[2]; + UINT8 Reserved91[2]; /** Offset 0x0AE8 - tRRSG Delta Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT @@ -3077,7 +3107,7 @@ /** Offset 0x0AF8 - Reserved **/ - UINT8 Reserved94[41]; + UINT8 Reserved92[41]; /** Offset 0x0B21 - Channel to CKD QCK Mapping Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1 @@ -3091,7 +3121,7 @@ /** Offset 0x0B31 - Reserved **/ - UINT8 Reserved95[55]; + UINT8 Reserved93[55]; } FSP_M_CONFIG; /** Fsp M UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/89311?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id5b37434396d4d70f4269a1bf82aa3d6935a9d41 Gerrit-Change-Number: 89311 Gerrit-PatchSet: 5 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varun Upadhyay <varun.upadhyay(a)intel.com>

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