September 2024 - coreboot-gerrit

[S] Change in coreboot[main]: soc/amd/glinda: Update pci int defs
by Felix Held (Code Review) Sept. 30, 2024

Sept. 30, 2024

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84375?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/glinda: Update pci int defs ...................................................................... soc/amd/glinda: Update pci int defs Update IRQs according to datasheet/PPR. source: PPR #57254 Rev 1.59 Table 137 Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84375 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/glinda/acpi/pci_int_defs.asl M src/soc/amd/glinda/fch.c M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h 3 files changed, 15 insertions(+), 16 deletions(-) Approvals: Marshall Dawson: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/soc/amd/glinda/acpi/pci_int_defs.asl b/src/soc/amd/glinda/acpi/pci_int_defs.asl index dfbf5c7..61ecd44 100644 --- a/src/soc/amd/glinda/acpi/pci_int_defs.asl +++ b/src/soc/amd/glinda/acpi/pci_int_defs.asl @@ -22,7 +22,9 @@ PIRG, 0x00000008, /* Index 6: INTG */ PIRH, 0x00000008, /* Index 7: INTH */ - Offset (0x62), + Offset (0x60), + PGSC, 0x00000008, /* Index 0x60: GEventSci */ + PGSM, 0x00000008, /* Index 0x61: GEventSmi */ PGPI, 0x00000008, /* Index 0x62: GPIO */ Offset (0x70), @@ -32,7 +34,8 @@ PI23, 0x00000008, /* Index 0x73: I2C3 */ PUA0, 0x00000008, /* Index 0x74: UART0 */ PUA1, 0x00000008, /* Index 0x75: UART1 */ - PI24, 0x00000008, /* Index 0x76: I2C4 */ + + Offset (0x77), PUA4, 0x00000008, /* Index 0x77: UART4 */ PUA2, 0x00000008, /* Index 0x78: UART2 */ PUA3, 0x00000008, /* Index 0x79: UART3 */ @@ -49,6 +52,8 @@ IORH, 0x00000008, /* Index 0x87: INTH */ Offset (0xE2), + IGSC, 0x00000008, /* Index 0xE0: GEventSci */ + IGSM, 0x00000008, /* Index 0xE1: GEventSmi */ IGPI, 0x00000008, /* Index 0xE2: GPIO */ Offset (0xF0), @@ -58,7 +63,8 @@ II23, 0x00000008, /* Index 0xF3: I2C3 */ IUA0, 0x00000008, /* Index 0xF4: UART0 */ IUA1, 0x00000008, /* Index 0xF5: UART1 */ - II24, 0x00000008, /* Index 0xF6: I2C4 */ + + Offset (0xF7), IUA4, 0x00000008, /* Index 0xF7: UART4 */ IUA2, 0x00000008, /* Index 0xF8: UART2 */ IUA3, 0x00000008, /* Index 0xF9: UART3 */ diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c index 8c58f5b..c119738 100644 --- a/src/soc/amd/glinda/fch.c +++ b/src/soc/amd/glinda/fch.c @@ -48,16 +48,13 @@ { PIRQ_SMBUS, "SMBUS" }, { PIRQ_ASF, "ASF" }, { PIRQ_PMON, "PerMon" }, - { PIRQ_SD, "SD" }, { PIRQ_SDIO, "SDIO" }, { PIRQ_CIR, "CIR" }, { PIRQ_GPIOA, "GPIOa" }, { PIRQ_GPIOB, "GPIOb" }, { PIRQ_GPIOC, "GPIOc" }, - { PIRQ_GPP0, "GPP0" }, - { PIRQ_GPP1, "GPP1" }, - { PIRQ_GPP2, "GPP2" }, - { PIRQ_GPP3, "GPP3" }, + { PIRQ_GSCI, "GEventSci" }, + { PIRQ_GSMI, "GeventSmi" }, { PIRQ_GPIO, "GPIO" }, { PIRQ_I2C0, "I2C0" }, { PIRQ_I2C1, "I2C1" }, diff --git a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h index ebe1d2c..3a9d9b5 100644 --- a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h @@ -32,20 +32,16 @@ #define PIRQ_ASF 0x12 /* ASF */ /* 0x13-0x15 reserved */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#define PIRQ_SD 0x17 /* SD */ -/* 0x18-0x19 reserved */ +/* 0x17-0x19 reserved */ #define PIRQ_SDIO 0x1a /* SDIO */ /* 0x1b-0x1f reserved */ #define PIRQ_CIR 0x20 /* CIR, no IRQ connected */ #define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */ #define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */ #define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */ -/* 0x24-0x4f reserved */ -#define PIRQ_GPP0 0x50 /* GPPInt0 */ -#define PIRQ_GPP1 0x51 /* GPPInt1 */ -#define PIRQ_GPP2 0x52 /* GPPInt2 */ -#define PIRQ_GPP3 0x53 /* GPPInt3 */ -/* 0x54-0x61 reserved */ +/* 0x24-0x5f reserved */ +#define PIRQ_GSCI 0x60 /* GEventSci Interrupt */ +#define PIRQ_GSMI 0x61 /* GEventSmi Interrupt */ #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ /* 0x63-0x6f reserved */ #define PIRQ_I2C0 0x70 /* I2C0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d Gerrit-Change-Number: 84375 Gerrit-PatchSet: 7 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/amd/glinda-phoenix: Update pci int defs
by Felix Held (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Maximilian Brune. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84574?usp=email ) Change subject: soc/amd/glinda-phoenix: Update pci int defs ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > misc1 and misc2 are hpet_l and hpet_h. […] see register descriptions at the beginning of the FCH registers chapter for those two IOx00C01_x0A [Intr_Misc1Map] (FCH::IO::IntrMisc1Map) IOx00C01_x0B [Intr_Misc2Map] (FCH::IO::IntrMisc2Map) i'd say that having them named with what they do makes things a bit clearer. to ge the best of both, maybe do this like in the smi.h file: #define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */ #define PIRQ_HPET_L PIRQ_MISC1 #define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */ #define PIRQ_HPET_H PIRQ_MISC2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34 Gerrit-Change-Number: 84574 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 16:21:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/amd/glinda-phoenix: Update pci int defs
by Felix Held (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Maximilian Brune. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84574?usp=email ) Change subject: soc/amd/glinda-phoenix: Update pci int defs ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84574/comment/0650c016_0f731284?us… : PS2, Line 13: Table 135 when referencing tables, better reference it by name as the numbering is usually different between the public/nda/internal version -- To view, visit https://review.coreboot.org/c/coreboot/+/84574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34 Gerrit-Change-Number: 84574 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 16:15:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/amd/glinda-phoenix: Update pci int defs
by Felix Held (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Maximilian Brune. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84574?usp=email ) Change subject: soc/amd/glinda-phoenix: Update pci int defs ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: misc1 and misc2 are hpet_l and hpet_h. iirc those were called differently in different locations -- To view, visit https://review.coreboot.org/c/coreboot/+/84574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34 Gerrit-Change-Number: 84574 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 16:13:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/amd/glinda: Update gpp bridge naming scheme
by Felix Held (Code Review) Sept. 30, 2024

Sept. 30, 2024

Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84378?usp=email ) Change subject: soc/amd/glinda: Update gpp bridge naming scheme ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > Sorry, that was just a verified -1. Didn't realize it'd stick after jenkins came back online. oh, right, that was verified -1 and not code review -1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84378?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d Gerrit-Change-Number: 84378 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 30 Sep 2024 16:11:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com>

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[M] Change in coreboot[main]: drivers/usb/acpi: Add AOLD Method for Intel Bluetooth
by Sean Rhodes (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Subrata Banik, Tarun. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84134?usp=email ) Change subject: drivers/usb/acpi: Add AOLD Method for Intel Bluetooth ...................................................................... Patch Set 16: (1 comment) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/84134/comment/d84a1bea_ae3d90a8?us… : PS16, Line 499: s_cfg > this and instance below should be `params->` not `s_cfg->` Copy/pasta -- To view, visit https://review.coreboot.org/c/coreboot/+/84134?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb804fb1cf0edef4a98479a6261ca68255dbf075 Gerrit-Change-Number: 84134 Gerrit-PatchSet: 16 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 15:53:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[M] Change in coreboot[main]: drivers/usb/acpi: Add AOLD Method for Intel Bluetooth
by Sean Rhodes (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Sean Rhodes, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84134?usp=email to look at the new patch set (#17). Change subject: drivers/usb/acpi: Add AOLD Method for Intel Bluetooth ...................................................................... drivers/usb/acpi: Add AOLD Method for Intel Bluetooth Add AOLD Method, which simply returns an integer based on whether Audio Offload is enabled. Leave the existing control of Audio Offload in `soc/soc_chip.h`, and add second control in the USB ACPI `chip.h` which takes precedence if used. Change-Id: Idb804fb1cf0edef4a98479a6261ca68255dbf075 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/tigerlake/fsp_params.c 5 files changed, 83 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/84134/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/84134?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb804fb1cf0edef4a98479a6261ca68255dbf075 Gerrit-Change-Number: 84134 Gerrit-PatchSet: 17 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[S] Change in coreboot[main]: soc/amd/glinda: Update gpp bridge naming scheme
by Martin L Roth (Code Review) Sept. 30, 2024

Sept. 30, 2024

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84378?usp=email ) Change subject: soc/amd/glinda: Update gpp bridge naming scheme ...................................................................... soc/amd/glinda: Update gpp bridge naming scheme This patch updates the naming scheme used for the GPP bridges. The naming scheme now matches what we also have on phoenix. Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84378 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/birman/devicetree_glinda.cb M src/mainboard/amd/birman_plus/devicetree_glinda.cb M src/soc/amd/glinda/chipset.cb 3 files changed, 15 insertions(+), 12 deletions(-) Approvals: Marshall Dawson: Looks good to me, approved build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/birman/devicetree_glinda.cb b/src/mainboard/amd/birman/devicetree_glinda.cb index f1a99f6..2e06f2b 100644 --- a/src/mainboard/amd/birman/devicetree_glinda.cb +++ b/src/mainboard/amd/birman/devicetree_glinda.cb @@ -158,9 +158,10 @@ device domain 0 on device ref iommu on end - device ref gpp_bridge_0 on end # GBE - device ref gpp_bridge_1 on end # WIFI - device ref gpp_bridge_2 on end # NVMe SSD + device ref gpp_bridge_2_1 on end # GBE + device ref gpp_bridge_2_2 on end # WIFI + device ref gpp_bridge_2_3 on end # NVMe SSD + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb index 1df02ed..e867f01 100644 --- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb +++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb @@ -158,9 +158,9 @@ device domain 0 on device ref iommu on end - device ref gpp_bridge_0 on end # GBE - device ref gpp_bridge_1 on end # WIFI - device ref gpp_bridge_2 on end # NVMe SSD + device ref gpp_bridge_2_1 on end # GBE + device ref gpp_bridge_2_2 on end # WIFI + device ref gpp_bridge_2_3 on end # NVMe SSD device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb index 6e23c2d..f328797 100644 --- a/src/soc/amd/glinda/chipset.cb +++ b/src/soc/amd/glinda/chipset.cb @@ -14,13 +14,15 @@ device pci 01.2 alias usb4_pcie_bridge_1 off end device pci 01.3 alias usb4_pcie_bridge_2 off end + # The PCIe GPP aliases in this SoC match the device and function numbers device pci 02.0 on end # Dummy device function, do not disable - device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end - device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end - device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end - device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end - device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end - device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end + device pci 02.1 alias gpp_bridge_2_1 off ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_2_2 off ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2_3 off ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_2_4 off ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end + device pci 03.0 on end # Dummy device function, do not disable device pci 03.1 alias gpp_bridge_3_1 off ops amd_external_pcie_gpp_ops end device pci 03.2 alias gpp_bridge_3_2 off ops amd_external_pcie_gpp_ops end -- To view, visit https://review.coreboot.org/c/coreboot/+/84378?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d Gerrit-Change-Number: 84378 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/amd/glinda: Update gpp bridge naming scheme
by Martin L Roth (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Fred Reitberger, Jason Glenesk, Maximilian Brune. Martin L Roth has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84378?usp=email ) Change subject: soc/amd/glinda: Update gpp bridge naming scheme ...................................................................... Patch Set 3: -Verified (1 comment) Patchset: PS3: Sorry, that was just a verified -1. Didn't realize it'd stick after jenkins came back online. -- To view, visit https://review.coreboot.org/c/coreboot/+/84378?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d Gerrit-Change-Number: 84378 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 15:50:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brox/jubilant: Modify FP IRQ pin on disable pads
by Karthik Ramasubramanian (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Ren Kuo. Karthik Ramasubramanian has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84545?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/brox/jubilant: Modify FP IRQ pin on disable pads ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84545/comment/5c54b23c_b950a6d6?us… : PS4, Line 8: : In previous cl:84124 Previously in CB:84124 https://review.coreboot.org/c/coreboot/+/84545/comment/a946eb29_ca964314?us… : PS4, Line 10: , and fp_disable_pads need to be updated. . Hence update fp_disable_pads configuration to include that GPIO. -- To view, visit https://review.coreboot.org/c/coreboot/+/84545?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee4c3d3f000f884ca8a77ae8c72ccbeebfeb865f Gerrit-Change-Number: 84545 Gerrit-PatchSet: 4 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 15:43:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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