September 2024 - coreboot-gerrit

[S] Change in coreboot[main]: util/lint: Use bigint for hexadecimal values in handle_range
by Subrata Banik (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Felix Held, Jérémy Compostella, Martin L Roth, Paul Menzel. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84575?usp=email ) Change subject: util/lint: Use bigint for hexadecimal values in handle_range ...................................................................... Patch Set 4: (1 comment) File util/lint/kconfig_lint: https://review.coreboot.org/c/coreboot/+/84575/comment/3e990bd1_d1da2be5?us… : PS4, Line 871: Use bigint for large hexadecimal values > nit: I believe this is redundant and maybe not even necessary to mention it actually. let me remove it. > > More importantly, shouldn't it make sense to also add support for default values ? 64-bit support for `default` value already existed hence, it's working over Rex64 w/o any problem. > It looks weird to me to only support large numbers for range only. this code changes only added to support https://review.coreboot.org/c/coreboot/+/84572/4..8/src/drivers/intel/fsp2_… where `range` is unable to handle > 32-bit value -- To view, visit https://review.coreboot.org/c/coreboot/+/84575?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I402bb9bec9ba5bfb79b4185f35228c41d4a7b674 Gerrit-Change-Number: 84575 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 30 Sep 2024 18:36:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: util/lint: Use bigint for hexadecimal values in handle_range
by Jérémy Compostella (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Felix Held, Martin L Roth, Paul Menzel, Subrata Banik. Jérémy Compostella has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84575?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: util/lint: Use bigint for hexadecimal values in handle_range ...................................................................... Patch Set 4: (1 comment) File util/lint/kconfig_lint: https://review.coreboot.org/c/coreboot/+/84575/comment/c47c4c63_eaeb0e8f?us… : PS4, Line 871: Use bigint for large hexadecimal values nit: I believe this is redundant and maybe not even necessary to mention it actually. More importantly, shouldn't it make sense to also add support for default values ? It looks weird to me to only support large numbers for range only. -- To view, visit https://review.coreboot.org/c/coreboot/+/84575?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I402bb9bec9ba5bfb79b4185f35228c41d4a7b674 Gerrit-Change-Number: 84575 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 30 Sep 2024 17:54:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: chromeec/ec_acpi: Define ACPI devices for USB-C ports using UCSI
by Felix Held (Code Review) Sept. 30, 2024

Sept. 30, 2024

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84404?usp=email ) Change subject: chromeec/ec_acpi: Define ACPI devices for USB-C ports using UCSI ...................................................................... chromeec/ec_acpi: Define ACPI devices for USB-C ports using UCSI Add support to define ACPI devices for USB-C ports using UCSI. When defining the typec configuration do not set mux/retimer information. cros_ec_ucsi does not support setting USB muxes. BUG=b:349822718 TEST=emerge-brox coreboot chromeos-bootimage. Boot to OS on brox, confirmed that there are ACPI devices for each USB-C port and cros_ec_ucsi correctly matched the ACPI devices ("ls -l /sys/class/typec" with an update to add an ACPI match table to the cros_ec_ucsi driver). Change-Id: Ie7c281fe2a7fab705d3c238dcc4be68c93afd652 Signed-off-by: Jameson Thies <jthies(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84404 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/chromeec/ec_acpi.c 1 file changed, 19 insertions(+), 8 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 1c97dcc..65a425b 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -18,6 +18,12 @@ #define GOOGLE_CHROMEEC_USBC_DEVICE_HID "GOOG0014" #define GOOGLE_CHROMEEC_USBC_DEVICE_NAME "USBC" +/* + * Boards using UCSI need the USB-C ports to match with cros_ec_ucsi, not + * cros-ec-typec. + */ +#define GOOGLE_CHROMEEC_USBC_UCSI_DEVICE_HID "GOOG0021" + const char *google_chromeec_acpi_name(const struct device *dev) { /* @@ -157,11 +163,6 @@ struct acpi_pld pld = {0}; uint32_t pcap_mask = 0; - /* UCSI implementations do not require an ACPI device with mux info since the - linux kernel doesn't set the muxes. */ - if (google_chromeec_get_ucsi_enabled()) - return; - rv = google_chromeec_get_num_pd_ports(&num_ports); if (rv || num_ports == 0) return; @@ -173,9 +174,19 @@ acpigen_write_scope(acpi_device_path(dev)); acpigen_write_device(GOOGLE_CHROMEEC_USBC_DEVICE_NAME); - acpigen_write_name_string("_HID", GOOGLE_CHROMEEC_USBC_DEVICE_HID); - acpigen_write_name_string("_DDN", "ChromeOS EC Embedded Controller " - "USB Type-C Control"); + + bool ucsi_platform = google_chromeec_get_ucsi_enabled(); + if (ucsi_platform) { + acpigen_write_name_string("_HID", + GOOGLE_CHROMEEC_USBC_UCSI_DEVICE_HID); + acpigen_write_name_string("_DDN", "ChromeOS EC UCSI USB Type-C " + "Control"); + } else { + acpigen_write_name_string("_HID", + GOOGLE_CHROMEEC_USBC_DEVICE_HID); + acpigen_write_name_string("_DDN", "ChromeOS EC Embedded " + "Controller USB Type-C Control"); + } for (i = 0; i < num_ports; ++i) { rv = google_chromeec_get_pd_port_caps(i, &port_caps); -- To view, visit https://review.coreboot.org/c/coreboot/+/84404?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7c281fe2a7fab705d3c238dcc4be68c93afd652 Gerrit-Change-Number: 84404 Gerrit-PatchSet: 7 Gerrit-Owner: Jameson Thies <jthies(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhishek Pandit-Subedi <abhishekpandit(a)google.com>

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[XS] Change in coreboot[main]: device_util: Add support for GICv3 path in device path handling
by Felix Held (Code Review) Sept. 30, 2024

Sept. 30, 2024

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79972?usp=email ) Change subject: device_util: Add support for GICv3 path in device path handling ...................................................................... device_util: Add support for GICv3 path in device path handling Change-Id: Ib4004c1f1b854a54dfdf9eaa7f25583dec947302 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79972 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/device_util.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/device/device_util.c b/src/device/device_util.c index 3514de7..f33c925 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -230,6 +230,9 @@ case DEVICE_PATH_MDIO: snprintf(buffer, sizeof(buffer), "MDIO: %02x", dev->path.mdio.addr); break; + case DEVICE_PATH_GICC_V3: + snprintf(buffer, sizeof(buffer), "GICV3: %02x", dev->path.gicc_v3.mpidr); + break; default: printk(BIOS_ERR, "Unknown device path type: %d\n", dev->path.type); -- To view, visit https://review.coreboot.org/c/coreboot/+/79972?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4004c1f1b854a54dfdf9eaa7f25583dec947302 Gerrit-Change-Number: 79972 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[S] Change in coreboot[main]: arch/x86: Configure EBDA through Kconfig
by Felix Held (Code Review) Sept. 30, 2024

Sept. 30, 2024

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84321?usp=email ) Change subject: arch/x86: Configure EBDA through Kconfig ...................................................................... arch/x86: Configure EBDA through Kconfig EBDA (Extended BIOS Data Area) is a memory area below 0xA0000 and one of the default areas where OS will scan ACPI RSDP pointer from. coreboot's default EBDA's starting address is 0xF6000, which is in PAM (Programmable Attribute Map) F-segment's scope. For some platforms without writeable PAM-F segment (e.g. some simics virtual platforms), corboot's default EBDA is not writable. Make DEFAULT_EBDA_LOWMEM, DEFAULT_EBDA_SEGMENT, DEFAULT_EBDA_SIZE as Kconfig items so that coreboot's EBDA could be relocated to a writable low memory place. Change-Id: Icd7ba0c902560f7d498934392685dc2af9c5ce09 Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Co-authored-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84321 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/arch/x86/Kconfig M src/arch/x86/ebda.c 2 files changed, 21 insertions(+), 9 deletions(-) Approvals: Jérémy Compostella: Looks good to me, approved build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 16d8a70..4737e3c 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -422,4 +422,21 @@ The default value is 1024 bytes (1 KiB) for ChromeOS and 0 for other platforms. +config DEFAULT_EBDA_LOWMEM + hex + default 0x100000 + help + The default value of EBDA low memory is (1024 << 10). + +config DEFAULT_EBDA_SEGMENT + hex + default 0xF600 + help + The default value of EBDA segment is 0xF600. + +config DEFAULT_EBDA_SIZE + hex + default 0x400 + help + The default value of EBDA size is 0x400. endif diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c index e835fce..f3e8fd2 100644 --- a/src/arch/x86/ebda.c +++ b/src/arch/x86/ebda.c @@ -10,14 +10,9 @@ #define X86_EBDA_SEGMENT ((void *)0x40e) #define X86_EBDA_LOWMEM ((void *)0x413) -#define DEFAULT_EBDA_LOWMEM (1024 << 10) -#define DEFAULT_EBDA_SEGMENT 0xF600 -#define DEFAULT_EBDA_SIZE 0x400 - - static void *get_ebda_start(void) { - return (void *)((uintptr_t)DEFAULT_EBDA_SEGMENT << 4); + return (void *)((uintptr_t)CONFIG_DEFAULT_EBDA_SEGMENT << 4); } /* @@ -55,9 +50,9 @@ if (acpi_is_wakeup_s3()) return; - setup_ebda(DEFAULT_EBDA_LOWMEM, - DEFAULT_EBDA_SEGMENT, - DEFAULT_EBDA_SIZE); + setup_ebda(CONFIG_DEFAULT_EBDA_LOWMEM, + CONFIG_DEFAULT_EBDA_SEGMENT, + CONFIG_DEFAULT_EBDA_SIZE); } /* Ensure EBDA is prepared before Option ROMs. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd7ba0c902560f7d498934392685dc2af9c5ce09 Gerrit-Change-Number: 84321 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com>

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[S] Change in coreboot[main]: soc/amd/glinda: Update pci int defs
by Felix Held (Code Review) Sept. 30, 2024

Sept. 30, 2024

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84375?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/glinda: Update pci int defs ...................................................................... soc/amd/glinda: Update pci int defs Update IRQs according to datasheet/PPR. source: PPR #57254 Rev 1.59 Table 137 Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84375 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/glinda/acpi/pci_int_defs.asl M src/soc/amd/glinda/fch.c M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h 3 files changed, 15 insertions(+), 16 deletions(-) Approvals: Marshall Dawson: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/soc/amd/glinda/acpi/pci_int_defs.asl b/src/soc/amd/glinda/acpi/pci_int_defs.asl index dfbf5c7..61ecd44 100644 --- a/src/soc/amd/glinda/acpi/pci_int_defs.asl +++ b/src/soc/amd/glinda/acpi/pci_int_defs.asl @@ -22,7 +22,9 @@ PIRG, 0x00000008, /* Index 6: INTG */ PIRH, 0x00000008, /* Index 7: INTH */ - Offset (0x62), + Offset (0x60), + PGSC, 0x00000008, /* Index 0x60: GEventSci */ + PGSM, 0x00000008, /* Index 0x61: GEventSmi */ PGPI, 0x00000008, /* Index 0x62: GPIO */ Offset (0x70), @@ -32,7 +34,8 @@ PI23, 0x00000008, /* Index 0x73: I2C3 */ PUA0, 0x00000008, /* Index 0x74: UART0 */ PUA1, 0x00000008, /* Index 0x75: UART1 */ - PI24, 0x00000008, /* Index 0x76: I2C4 */ + + Offset (0x77), PUA4, 0x00000008, /* Index 0x77: UART4 */ PUA2, 0x00000008, /* Index 0x78: UART2 */ PUA3, 0x00000008, /* Index 0x79: UART3 */ @@ -49,6 +52,8 @@ IORH, 0x00000008, /* Index 0x87: INTH */ Offset (0xE2), + IGSC, 0x00000008, /* Index 0xE0: GEventSci */ + IGSM, 0x00000008, /* Index 0xE1: GEventSmi */ IGPI, 0x00000008, /* Index 0xE2: GPIO */ Offset (0xF0), @@ -58,7 +63,8 @@ II23, 0x00000008, /* Index 0xF3: I2C3 */ IUA0, 0x00000008, /* Index 0xF4: UART0 */ IUA1, 0x00000008, /* Index 0xF5: UART1 */ - II24, 0x00000008, /* Index 0xF6: I2C4 */ + + Offset (0xF7), IUA4, 0x00000008, /* Index 0xF7: UART4 */ IUA2, 0x00000008, /* Index 0xF8: UART2 */ IUA3, 0x00000008, /* Index 0xF9: UART3 */ diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c index 8c58f5b..c119738 100644 --- a/src/soc/amd/glinda/fch.c +++ b/src/soc/amd/glinda/fch.c @@ -48,16 +48,13 @@ { PIRQ_SMBUS, "SMBUS" }, { PIRQ_ASF, "ASF" }, { PIRQ_PMON, "PerMon" }, - { PIRQ_SD, "SD" }, { PIRQ_SDIO, "SDIO" }, { PIRQ_CIR, "CIR" }, { PIRQ_GPIOA, "GPIOa" }, { PIRQ_GPIOB, "GPIOb" }, { PIRQ_GPIOC, "GPIOc" }, - { PIRQ_GPP0, "GPP0" }, - { PIRQ_GPP1, "GPP1" }, - { PIRQ_GPP2, "GPP2" }, - { PIRQ_GPP3, "GPP3" }, + { PIRQ_GSCI, "GEventSci" }, + { PIRQ_GSMI, "GeventSmi" }, { PIRQ_GPIO, "GPIO" }, { PIRQ_I2C0, "I2C0" }, { PIRQ_I2C1, "I2C1" }, diff --git a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h index ebe1d2c..3a9d9b5 100644 --- a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h @@ -32,20 +32,16 @@ #define PIRQ_ASF 0x12 /* ASF */ /* 0x13-0x15 reserved */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#define PIRQ_SD 0x17 /* SD */ -/* 0x18-0x19 reserved */ +/* 0x17-0x19 reserved */ #define PIRQ_SDIO 0x1a /* SDIO */ /* 0x1b-0x1f reserved */ #define PIRQ_CIR 0x20 /* CIR, no IRQ connected */ #define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */ #define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */ #define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */ -/* 0x24-0x4f reserved */ -#define PIRQ_GPP0 0x50 /* GPPInt0 */ -#define PIRQ_GPP1 0x51 /* GPPInt1 */ -#define PIRQ_GPP2 0x52 /* GPPInt2 */ -#define PIRQ_GPP3 0x53 /* GPPInt3 */ -/* 0x54-0x61 reserved */ +/* 0x24-0x5f reserved */ +#define PIRQ_GSCI 0x60 /* GEventSci Interrupt */ +#define PIRQ_GSMI 0x61 /* GEventSmi Interrupt */ #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ /* 0x63-0x6f reserved */ #define PIRQ_I2C0 0x70 /* I2C0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d Gerrit-Change-Number: 84375 Gerrit-PatchSet: 7 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/amd/glinda-phoenix: Update pci int defs
by Felix Held (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Maximilian Brune. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84574?usp=email ) Change subject: soc/amd/glinda-phoenix: Update pci int defs ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > misc1 and misc2 are hpet_l and hpet_h. […] see register descriptions at the beginning of the FCH registers chapter for those two IOx00C01_x0A [Intr_Misc1Map] (FCH::IO::IntrMisc1Map) IOx00C01_x0B [Intr_Misc2Map] (FCH::IO::IntrMisc2Map) i'd say that having them named with what they do makes things a bit clearer. to ge the best of both, maybe do this like in the smi.h file: #define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */ #define PIRQ_HPET_L PIRQ_MISC1 #define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */ #define PIRQ_HPET_H PIRQ_MISC2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34 Gerrit-Change-Number: 84574 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 16:21:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/amd/glinda-phoenix: Update pci int defs
by Felix Held (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Maximilian Brune. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84574?usp=email ) Change subject: soc/amd/glinda-phoenix: Update pci int defs ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84574/comment/0650c016_0f731284?us… : PS2, Line 13: Table 135 when referencing tables, better reference it by name as the numbering is usually different between the public/nda/internal version -- To view, visit https://review.coreboot.org/c/coreboot/+/84574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34 Gerrit-Change-Number: 84574 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 16:15:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/amd/glinda-phoenix: Update pci int defs
by Felix Held (Code Review) Sept. 30, 2024

Sept. 30, 2024

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Maximilian Brune. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84574?usp=email ) Change subject: soc/amd/glinda-phoenix: Update pci int defs ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: misc1 and misc2 are hpet_l and hpet_h. iirc those were called differently in different locations -- To view, visit https://review.coreboot.org/c/coreboot/+/84574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34 Gerrit-Change-Number: 84574 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Sep 2024 16:13:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/amd/glinda: Update gpp bridge naming scheme
by Felix Held (Code Review) Sept. 30, 2024

Sept. 30, 2024

Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84378?usp=email ) Change subject: soc/amd/glinda: Update gpp bridge naming scheme ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > Sorry, that was just a verified -1. Didn't realize it'd stick after jenkins came back online. oh, right, that was verified -1 and not code review -1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84378?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d Gerrit-Change-Number: 84378 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 30 Sep 2024 16:11:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com>

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