September 2024 - coreboot-gerrit

[S] Change in coreboot[main]: tree: Use boolean for lpss_s0ix_enable
by Paul Menzel (Code Review) Sept. 1, 2024

Sept. 1, 2024

Attention is currently required from: Elyes Haouas. Paul Menzel has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84160?usp=email ) Change subject: tree: Use boolean for lpss_s0ix_enable ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84160/comment/a85a0b1c_6e29ef9d?us… : PS1, Line 8: Why? -- To view, visit https://review.coreboot.org/c/coreboot/+/84160?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34bd568defe202daaad6136b9c184bc292a226b3 Gerrit-Change-Number: 84160 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 01 Sep 2024 05:19:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: drivers/efi/uefi_capsules.c: coalesce and store UEFI capsules
by Paul Menzel (Code Review) Sept. 1, 2024

Sept. 1, 2024

Paul Menzel has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/83422?usp=email ) Change subject: drivers/efi/uefi_capsules.c: coalesce and store UEFI capsules ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Nice work. Please paste the new log lines in here for the record. -- To view, visit https://review.coreboot.org/c/coreboot/+/83422?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I162d678ae5c504906084b59c1a8d8c26dadb9433 Gerrit-Change-Number: 83422 Gerrit-PatchSet: 6 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 01 Sep 2024 05:16:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: tree: Use boolean for s0ix_enable
by Elyes Haouas (Code Review) Sept. 1, 2024

Sept. 1, 2024

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84159?usp=email ) Change subject: tree: Use boolean for s0ix_enable ...................................................................... tree: Use boolean for s0ix_enable Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/aoostar/wtr_r1/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/cwwk/adl/devicetree.cb M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/orisa/overridetree.cb M src/mainboard/google/brya/variants/trulo/overridetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/prodrive/atlas/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/protectli/vault_ehl/devicetree.cb M src/mainboard/purism/librem_jsl/devicetree.cb M src/mainboard/purism/librem_l1um_v2/devicetree.cb M src/mainboard/system76/tgl-u/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/tigerlake/chip.h 43 files changed, 43 insertions(+), 43 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/aoostar/wtr_r1/devicetree.cb b/src/mainboard/aoostar/wtr_r1/devicetree.cb index 101bb99..a802cca 100644 --- a/src/mainboard/aoostar/wtr_r1/devicetree.cb +++ b/src/mainboard/aoostar/wtr_r1/devicetree.cb @@ -14,7 +14,7 @@ register "dptf_enable" = "1" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "common_soc_config" = "{ .i2c[0] = { diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 11a8749..2fa7a30 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -1,5 +1,5 @@ chip soc/intel/cannonlake - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "common_soc_config" = "{ /* Touchpad */ .i2c[0] = { diff --git a/src/mainboard/cwwk/adl/devicetree.cb b/src/mainboard/cwwk/adl/devicetree.cb index 15ec3b2..c4c5e8c 100644 --- a/src/mainboard/cwwk/adl/devicetree.cb +++ b/src/mainboard/cwwk/adl/devicetree.cb @@ -1,6 +1,6 @@ chip soc/intel/alderlake - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 2ded452..49db518 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -17,7 +17,7 @@ chip cpu/intel/haswell device cpu_cluster 0 on ops broadwell_cpu_bus_ops end - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" end device domain 0 on diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index be96e95..d1e217b 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -14,7 +14,7 @@ chip cpu/intel/haswell device cpu_cluster 0 on end - register "s0ix_enable" = "0" + register "s0ix_enable" = "false" end device domain 0 on diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 3de469ec..b0b8a60 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -16,7 +16,7 @@ device cpu_cluster 0 on end # Disable S0ix for now - register "s0ix_enable" = "0" + register "s0ix_enable" = "false" register "vr_config" = "{ .slow_ramp_rate_set = 3, diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index 22e15ac..b900af1 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -15,7 +15,7 @@ register "sagv" = "SaGv_Enabled" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Disable package C state demotion on Raptorlake as a W/A for S0ix issues # seen on J0 and Q0 SKUs diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 38535a4..2ba54bc 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -15,7 +15,7 @@ register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 0290181..e07cf2a 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -12,7 +12,7 @@ register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Disable package C state demotion on Raptorlake as a W/A for S0ix issues # seen on J0 and Q0 SKUs diff --git a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb index 4372888..f91b088 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb @@ -12,7 +12,7 @@ register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index aac4bca..3d28ed3 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -29,7 +29,7 @@ register "gen3_dec" = "0x00fc0901" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index ffc3a56..ad5b943 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -24,7 +24,7 @@ register "pmc_gpe0_dw2" = "GPP_F" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index a5b346c..868342b 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -24,7 +24,7 @@ register "pmc_gpe0_dw2" = "GPP_F" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 534db38..cc2b66d 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -145,7 +145,7 @@ register "SdCardPowerEnableActiveHigh" = "1" # Enable S0ix support - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Display related UPDs # Select eDP for port A diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 302a09e..7238a06 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -39,7 +39,7 @@ # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "dptf_enable" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 25, diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 49ff8dd..2fe3e46 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -53,7 +53,7 @@ }" # Enable S0i3 support - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Enable STT support register "stt_control" = "1" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 39cea80..8c33f02 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -28,7 +28,7 @@ # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Enable DPTF register "dptf_enable" = "1" register "power_limits_config" = "{ diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 9e8e96a..08880cb 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -28,7 +28,7 @@ # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Enable DPTF register "dptf_enable" = "1" register "power_limits_config" = "{ diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index 7cb10d2..f0eb655 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -31,7 +31,7 @@ register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3 # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb index 7358eeb..16506ac 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb @@ -31,7 +31,7 @@ register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3 # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 00acbec..13558a4 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -31,7 +31,7 @@ register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3 # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb index 625a36b..d7a5f80 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb @@ -31,7 +31,7 @@ register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3 # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "1" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index fcaa730..7eec7a8 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -27,7 +27,7 @@ # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "dptf_enable" = "1" register "satapwroptimize" = "1" register "power_limits_config" = "{ diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 589ea1c..d10fd1f 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -30,7 +30,7 @@ # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "dptf_enable" = "1" register "satapwroptimize" = "1" register "AcousticNoiseMitigation" = "1" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 5dfc69c..4ff518e 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -195,7 +195,7 @@ register "DdiPort4Ddc" = "0" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 68c0754..95b006e 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -132,7 +132,7 @@ # TCSS USB3 register "tcss_aux_ori" = "0" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "dptf_enable" = "1" register "serial_io_i2c_mode" = "{ diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index ec60894..0b3a3ef 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -95,7 +95,7 @@ # TCSS USB3 register "tcss_aux_ori" = "0" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index 6776284..c01613c 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -70,7 +70,7 @@ register "tcss_aux_ori" = "4" register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_E20, .pad_auxn_dc = GPP_E21}" - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index bee71aa..012afc4 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -40,7 +40,7 @@ register "PcieClkSrcClkReq[5]" = "5" # Disable S0ix - register "s0ix_enable" = "0" + register "s0ix_enable" = "false" device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index 0ba9e83..e49c102 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -38,7 +38,7 @@ register "sdcard_cd_gpio" = "GPP_G5" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 59d69dc..1495366 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -150,7 +150,7 @@ }" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # GPIO for SD card detect register "sdcard_cd_gpio" = "VGPIO_39" diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 010cae2..e97d19e 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -50,7 +50,7 @@ register "cnvi_bt_core" = "true" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "1" diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index fb55da4..b864da6 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -19,7 +19,7 @@ register "sagv" = "SaGv_Enabled" # S0ix enable - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port A0 register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # Type-A Port A1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b82f583..69ec546 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -68,7 +68,7 @@ register "TcssAuxOri" = "0" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 51895b2..fbb8418 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -75,7 +75,7 @@ register "TcssAuxOri" = "0" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index 1c4af58..580ca76 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -20,7 +20,7 @@ register "sagv" = "CONFIG(ATLAS_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled" # Disable S0ix - register "s0ix_enable" = "0" + register "s0ix_enable" = "false" # Display configuration (4 DPs) register "ddi_ports_config" = "{ diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 317de80..6e1ecfd 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -105,7 +105,7 @@ register "tcc_offset" = "1" # TCC of 99C # Disable S0ix - register "s0ix_enable" = "0" + register "s0ix_enable" = "false" # Enable Turbo register "eist_enable" = "true" diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb index df0dbdf..10782b2 100644 --- a/src/mainboard/protectli/vault_ehl/devicetree.cb +++ b/src/mainboard/protectli/vault_ehl/devicetree.cb @@ -11,7 +11,7 @@ register "eist_enable" = "true" # Enable lpss s0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/purism/librem_jsl/devicetree.cb b/src/mainboard/purism/librem_jsl/devicetree.cb index f8e494a..c00404d 100644 --- a/src/mainboard/purism/librem_jsl/devicetree.cb +++ b/src/mainboard/purism/librem_jsl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/jasperlake register "eist_enable" = "true" - register "s0ix_enable" = "0" + register "s0ix_enable" = "false" register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb index e26e6b2..cf1a8b8 100644 --- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb +++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb @@ -19,7 +19,7 @@ register "PcieClkSrcClkReq[14]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcClkReq[15]" = "PCIE_CLK_NOTUSED" - register "s0ix_enable" = "0" + register "s0ix_enable" = "false" register "eist_enable" = "true" diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb index d96249d..94b5970 100644 --- a/src/mainboard/system76/tgl-u/devicetree.cb +++ b/src/mainboard/system76/tgl-u/devicetree.cb @@ -15,7 +15,7 @@ register "eist_enable" = "true" # Enable s0ix, required for TGL-U - register "s0ix_enable" = "1" + register "s0ix_enable" = "true" # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) # Enable C6 DRAM diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index e5c7f54..d446ef0 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -128,7 +128,7 @@ uint32_t gen4_dec; /* Enable S0iX support */ - int s0ix_enable; + bool s0ix_enable; /* Enable DPTF support */ int dptf_enable; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index e8d417e..6785eba 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -141,7 +141,7 @@ uint32_t gen4_dec; /* Enable S0iX support */ - int s0ix_enable; + bool s0ix_enable; /* S0iX: Selectively disable individual sub-states, by default all are enabled. */ enum lpm_state_mask LpmStateDisableMask; -- To view, visit https://review.coreboot.org/c/coreboot/+/84159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6 Gerrit-Change-Number: 84159 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: tree: Use eist_enable as bool for newly merged files
by Elyes Haouas (Code Review) Sept. 1, 2024

Sept. 1, 2024

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84156?usp=email ) Change subject: tree: Use eist_enable as bool for newly merged files ...................................................................... tree: Use eist_enable as bool for newly merged files Change-Id: Icc01852dc5bd04cfa151e8fa7c5bcc160ed978c6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84156 Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/protectli/vault_adl_p/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb M src/mainboard/system76/mtl/devicetree.cb 3 files changed, 3 insertions(+), 3 deletions(-) Approvals: Sean Rhodes: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/protectli/vault_adl_p/devicetree.cb b/src/mainboard/protectli/vault_adl_p/devicetree.cb index f11dc6a..0089a5f 100644 --- a/src/mainboard/protectli/vault_adl_p/devicetree.cb +++ b/src/mainboard/protectli/vault_adl_p/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # FSP configuration - register "eist_enable" = "1" + register "eist_enable" = "true" # Sagv Configuration register "sagv" = "SaGv_Enabled" diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index 145dbc2..5a6424e 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -13,7 +13,7 @@ register "sagv" = "SaGv_Enabled" # FSP Silicon - register "eist_enable" = "1" + register "eist_enable" = "true" register "cnvi_bt_core" = "true" register "cnvi_bt_audio_offload" = "true" diff --git a/src/mainboard/system76/mtl/devicetree.cb b/src/mainboard/system76/mtl/devicetree.cb index 9a4cfb4..0bd6721 100644 --- a/src/mainboard/system76/mtl/devicetree.cb +++ b/src/mainboard/system76/mtl/devicetree.cb @@ -11,7 +11,7 @@ }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Thermal register "tcc_offset" = "8" -- To view, visit https://review.coreboot.org/c/coreboot/+/84156?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc01852dc5bd04cfa151e8fa7c5bcc160ed978c6 Gerrit-Change-Number: 84156 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Subrata Banik (Code Review) Sept. 1, 2024

Sept. 1, 2024

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Paul Menzel. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 13: (3 comments) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/15a81e6e_4237d4dd?us… : PS3, Line 110: SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 > Subrata, […] Acknowledged File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/b8f01014_f1061f93?us… : PS5, Line 29: GPE1_STS > Sure. Let me make the change. Acknowledged https://review.coreboot.org/c/coreboot/+/84103/comment/da90660e_07a08ad3?us… : PS5, Line 114: GPE1_STS(0) > > Subrata, […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 13 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 01 Sep 2024 03:11:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Subrata Banik (Code Review) Sept. 1, 2024

Sept. 1, 2024

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Paul Menzel. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 13: (4 comments) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/5eb4794c_422abf59?us… : PS7, Line 121: if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)) { > sure. agree. Acknowledged File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/af391b71_7bac40c5?us… : PS11, Line 115: 0 > Subrata, […] Acknowledged File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/84103/comment/d426ee2b_f76c4125?us… : PS13, Line 144: * drop this new line https://review.coreboot.org/c/coreboot/+/84103/comment/7cbea562_2a62725f?us… : PS13, Line 146: drop this new line -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 13 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 01 Sep 2024 03:11:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/gpio: support 16-bit CPU Port ID
by Subrata Banik (Code Review) Sept. 1, 2024

Sept. 1, 2024

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Paul Menzel, Saurabh Mishra, Wonkyu Kim. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83981?usp=email ) Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83981?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d Gerrit-Change-Number: 83981 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 01 Sep 2024 03:08:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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