December 2023 - coreboot-gerrit

[XS] Change in coreboot[main]: soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_S
by jason-ch chen (Code Review) Dec. 1, 2023

Dec. 1, 2023

Attention is currently required from: Hung-Te Lin, jason-ch chen. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79348?usp=email to look at the new patch set (#2). Change subject: soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_S ...................................................................... soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_S Update BND_NORTH_APB2_S's domain 5 permission to allow the access from APU. The APU requires certain information saved in BND_NORTH_APB2_S for voltage tuning. If this information cannot be retrieved, the APU may operate at a high frequency with low voltage. Consequently, the APU may not function as expected. Change-Id: I967b138dc5517e54da7fbf94b9e502e478c991b5 Signed-off-by: Nina Wu <nina-cm.wu(a)mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/devapc.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/79348/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79348?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I967b138dc5517e54da7fbf94b9e502e478c991b5 Gerrit-Change-Number: 79348 Gerrit-PatchSet: 2 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-CC: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: mb/google/rex/variants/deku: Complete USB configuration
by Eran Mitrani (Code Review) Dec. 1, 2023

Dec. 1, 2023

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Subrata Banik, Tarun. Eran Mitrani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79356?usp=email ) Change subject: mb/google/rex/variants/deku: Complete USB configuration ...................................................................... mb/google/rex/variants/deku: Complete USB configuration +-------------+----------------+------------+ | USB 2.0 | Connector Type | OC Mapping | +-------------+----------------+------------+ | 1 | Type-C | OC_0 | +-------------+----------------+------------+ | 2 | Type-C | OC_0 | +-------------+----------------+------------+ | 3 | Type-C | OC-0 | +-------------+----------------+------------+ | 4 | Type-A | OC_3 | +-------------+----------------+------------+ | 5 | Type-C | OC_0 | +-------------+----------------+------------+ | 6 | Type-A | OC_3 | +-------------+----------------+------------+ | 7 | Type-A | OC_3 | +-------------+----------------+------------+ | 8 | Type-A | OC_3 | +-------------+----------------+------------+ | 9 | Type-A | OC_3 | +-------------+----------------+------------+ | 10 | BT | NA | +-------------+----------------+------------+ +---------------------+-------------------+------------+ | USB 3.2 Gen 2x1 | Connector Details | OC Mapping | +---------------------+-------------------+------------+ | 1 | Type-A | OC_3 | +---------------------+-------------------+------------+ | 2 | Type-A | OC_3 | +---------------------+-------------------+------------+ +------+-------------------+------------+ | TCPx | Connector Details | OC Mapping | +------+-------------------+------------+ | 1 | Type C port 0 | OC_0 | +------+-------------------+------------+ | 2 | Type C port 1 | OC_0 | +------+-------------------+------------+ | 3 | Type C port 2 | OC_0 | +------+-------------------+------------+ | 4 | Type C port 3 | OC_0 | +------+-------------------+------------+ BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: I90d3d984af6d40efb4553cf5675617700161d2d7 --- M src/mainboard/google/rex/variants/deku/overridetree.cb 1 file changed, 191 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/79356/1 diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb index 1163292..86a015cf 100644 --- a/src/mainboard/google/rex/variants/deku/overridetree.cb +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -98,6 +98,158 @@ .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end # PCIE11 SSD card + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(3, 1))" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C3"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port0 as dfp[0].typec_port + device generic 0 on end + end + chip drivers/intel/usb4/retimer + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port1 as dfp[1].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port2 as dfp[0].typec_port + device generic 0 on end + end + chip drivers/intel/usb4/retimer + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + # FIXME - location need to be corrected once we have the final design + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C3"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(5, 1))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(5, 2))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 3))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 4))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A4"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 4))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B01)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(5, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(5, 2))" + device ref usb3_port2 on end + end + end + end + end device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" @@ -105,6 +257,44 @@ device i2c 50 on end end end + device ref soc_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + use conn2 as mux_conn[2] + use conn3 as mux_conn[3] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + #USB2_C0 + use usb2_port2 as usb2_port + use tcss_usb3_port0 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + #USB2_C1 + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn + #USB2_C2 + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 2 alias conn2 on end + end + chip drivers/intel/pmc_mux/conn + #USB2_C3 + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 3 alias conn3 on end + end + end + end + end end - end -- To view, visit https://review.coreboot.org/c/coreboot/+/79356?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I90d3d984af6d40efb4553cf5675617700161d2d7 Gerrit-Change-Number: 79356 Gerrit-PatchSet: 1 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: mb/google/rex/var/deku: Enable LAN0, LAN1
by Eran Mitrani (Code Review) Dec. 1, 2023

Dec. 1, 2023

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Subrata Banik, Tarun. Hello Dinesh Gehlot, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79292?usp=email to look at the new patch set (#10). Change subject: mb/google/rex/var/deku: Enable LAN0, LAN1 ...................................................................... mb/google/rex/var/deku: Enable LAN0, LAN1 google/deku is a Chromebox featuring two LAN ports. Add overridetree.cb entry to configure the LAN0 LAN1 devices. BUG=b:305793886 TEST=Built FW image correctly. Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: I8980dabc7f9fc731a2b60c599e1e48c9b11dabb4 Signed-off-by: Eran Mitrani <mitrani(a)google.com> --- M src/mainboard/google/rex/variants/deku/gpio.c M src/mainboard/google/rex/variants/deku/overridetree.cb 2 files changed, 32 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/79292/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/79292?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8980dabc7f9fc731a2b60c599e1e48c9b11dabb4 Gerrit-Change-Number: 79292 Gerrit-PatchSet: 10 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: mb/google/rex/variants/deku: Add basic DTT
by Eran Mitrani (Code Review) Dec. 1, 2023

Dec. 1, 2023

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Subrata Banik, Tarun. Hello Dinesh Gehlot, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79353?usp=email to look at the new patch set (#3). Change subject: mb/google/rex/variants/deku: Add basic DTT ...................................................................... mb/google/rex/variants/deku: Add basic DTT Add default Intel DPTF. BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: Id681754fc8e7b418de35f66df097cadd4aad7448 Signed-off-by: Eran Mitrani <mitrani(a)google.com> --- M src/mainboard/google/rex/variants/deku/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/79353/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79353?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id681754fc8e7b418de35f66df097cadd4aad7448 Gerrit-Change-Number: 79353 Gerrit-PatchSet: 3 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Shuo Liu (Code Review) Dec. 1, 2023

Dec. 1, 2023

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Nill Ge, Patrick Rudolph, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/xeon_sp/spr/chip.c: https://review.coreboot.org/c/coreboot/+/78327/comment/b9264756_22e3c52e : PS2, Line 51: noop_set_resources in our setting, pci_domain_set_resources is needed here. -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 01:26:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Shuo Liu (Code Review) Dec. 1, 2023

Dec. 1, 2023

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Nill Ge, Patrick Rudolph, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hi, Arthur, we evaluated this CR and like the change. Here is some thoughts to sync with you and the loop. 1) We will move GNR codes based on this new design. Both GNR codes and your changes are based on multi-domain design, and hence theoretically they naturally and mutually fit. But GNR codes is based on FSP2.4 new IIO interface while SPR and previous gen are based on FSP2.3 or earlier, hence we need to seek some adoption logics to make the common codes to support both. For this, we could have separate discussion. 2) We evaluated this change on our SPR test machine and found that PCI resource setting is needed, otherwise, some legacy IO access (RTC, et al) might be mistakenly taken by BMC video device without BAR programed. This issue might not occur on every machine, but as a robustness enhancement, we suggest to take care in this CR as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 01:24:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: libpayload: Fix the stack and data labels
by Yu-Ping Wu (Code Review) Dec. 1, 2023

Dec. 1, 2023

Attention is currently required from: Julius Werner, Paul Menzel, Yi Chou. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79144?usp=email ) Change subject: libpayload: Fix the stack and data labels ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79144?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I589040f4db60b35813ea9f4ba9503244bd7def00 Gerrit-Change-Number: 79144 Gerrit-PatchSet: 8 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yi Chou <yich(a)google.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 00:33:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: mb/google/brox: Update storage settings for SSD and UFS
by Shelley Chen (Code Review) Dec. 1, 2023

Dec. 1, 2023

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79295?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brox: Update storage settings for SSD and UFS ...................................................................... mb/google/brox: Update storage settings for SSD and UFS Brox has SSD and UFS storage per different SKU. 1. Set SSD on CPU PCIe port (PCIEX4_A) and configure related gpio settings according to the schematic. 2. Enable UFS, also enable ISH since it is PCI function 0, required for UFS function 7 to be enabled. 3. Set unused SRCCLKREQ signals to NC. 4. Remove unused gpio settings in variant gpio table to prevent unexpected overrides. BUG=b:311450057 BRANCH=None TEST=emerge-brox coreboot Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79295 Reviewed-by: Shelley Chen <shchen(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brox/Kconfig M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brox/variants/baseboard/brox/gpio.c M src/mainboard/google/brox/variants/brox/gpio.c 4 files changed, 38 insertions(+), 220 deletions(-) Approvals: Shelley Chen: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index f6f33b6..74bea81 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -47,6 +47,7 @@ select SOC_INTEL_CRASHLOG select SOC_INTEL_RAPTORLAKE select SOC_INTEL_ALDERLAKE_PCH_P + select DRIVERS_INTEL_ISH select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index c8b4c5a..42bf467 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -168,22 +168,21 @@ end device ref heci1 on end device ref sata on end - device ref pcie_rp8 on - # Enable SD Card PCIE 8 using clk 3 - register "pch_pcie_rp[PCH_RP(8)]" = "{ - .clk_src = 3, + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 3 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 3, - .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, - }" - end #PCIE8 SD card - device ref pcie_rp9 on - # Enable NVMe PCIE 9 using clk 1 - register "pch_pcie_rp[PCH_RP(9)]" = "{ - .clk_src = 1, - .clk_req = 1, + .clk_src = 3, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - end #PCIE9-12 SSD + end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref ufs on end device ref uart0 on end device ref gspi1 on end device ref pch_espi on diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index daf1b96..a909533 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -145,12 +145,12 @@ PAD_CFG_GPI_INT(GPP_D3, NONE, PLTRST, LEVEL), /* GPP_D4 : [NF1: IMGCLKOUT0 NF2: BK4 NF5: SBK4 NF6: USB_C_GPP_D4] ==> SOC_GPP_D4 */ PAD_NC(GPP_D4, NONE), - /* GPP_D5 : SRCCLKREQ0_L ==> PCIE_CLKREQ0_ODL */ - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* GPP_D5 : SRCCLKREQ0_L ==> NC */ + PAD_NC(GPP_D5, NONE), /* GPP_D6 : [NF1: SRCCLKREQ1# NF6: USB_C_GPP_D6] ==> WLAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), - /* GPP_D7 : SRCCLKREQ2_L ==> PCIE_CLKREQ2_ODL */ - PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* GPP_D7 : SRCCLKREQ2_L ==> NC */ + PAD_NC(GPP_D7, NONE), /* GPP_D8 : [NF1: SRCCLKREQ3# NF6: USB_C_GPP_D8] ==> SSD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> USB_C2_LSX_TX */ @@ -158,7 +158,7 @@ /* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> USB_C2_LSX_RX_STRAP */ PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), /* GPP_D11 : [] ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 0, DEEP), + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* GPP_D12 : [NF1: ISH_SPI_MOSI NF2: DDP4_CTRLDATA NF4: TBT_LSX3_RXD NF5: BSSB_LS3_TX NF6: USB_C_GPP_D12 NF7: GSPI2_MOSI] ==> SOC_GPP_D12 */ PAD_NC(GPP_D12, DN_20K), /* GPP_D13 : [NF1: ISH_UART0_RXD NF3: I2C6_SDA NF6: USB_C_GPP_D13] ==> UART0_ISH_RX_DBG_TX */ @@ -261,8 +261,8 @@ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF3), /* GPP_F18 : [NF3: THC1_SPI2_INT# NF6: USB_C_GPP_F18] ==> TCHSCR_INT_ODL */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3), - /* GPP_F19 : SRCCLKREQ6 ==> PCIE_CLKREQ5_ODL */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* GPP_F19 : SRCCLKREQ6 ==> NC */ + PAD_NC(GPP_F19, NONE), /* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> SOC_GPP_F20 */ PAD_NC(GPP_F20, NONE), /* GPP_F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> SOC_GPP_F21 */ @@ -306,16 +306,16 @@ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* GPP_H18 : [NF1: PROC_C10_GATE# NF6: USB_C_GPP_H18] ==> CPU_C10_GATE_L */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), - /* GPP_H19 : SRCCLKREQ4_L ==> PCIE_CLKREQ4_ODL */ - PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* GPP_H19 : SRCCLKREQ4_L ==> NC */ + PAD_NC(GPP_H19, NONE), /* GPP_H20 : IMGCLKOUT1 ==> BOARD_ID7 */ PAD_CFG_GPI(GPP_H20, NONE, DEEP), /* GPP_H21 : [NF1: IMGCLKOUT2 NF6: USB_C_GPP_H21] ==> SOC_GPP_H21 */ PAD_NC(GPP_H21, NONE), /* GPP_H22 : IMGCLKOUT3 ==> BOARD_ID8 */ PAD_CFG_GPI(GPP_H22, NONE, DEEP), - /* GPP_H23 : SRCCLKREQ5_L ==> PCIE_CLKREQ5_ODL */ - PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), + /* GPP_H23 : SRCCLKREQ5_L ==> NC */ + PAD_NC(GPP_H23, NONE), /* GPP_R0 : [NF1: HDA_BCLK NF2: I2S0_SCLK NF3: DMIC_CLK_B0 NF4: HDAPROC_BCLK] ==> HDA_HP_BCLK_R */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), @@ -371,14 +371,26 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* GPP_D11 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG), /* GPP_E8 : GPP_E8 ==> PCH_WP_OD */ PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 0, DEEP), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), /* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_S0, NONE, DEEP), }; const struct pad_config *__weak variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/brox/variants/brox/gpio.c b/src/mainboard/google/brox/variants/brox/gpio.c index 444adc4..5805bee 100644 --- a/src/mainboard/google/brox/variants/brox/gpio.c +++ b/src/mainboard/google/brox/variants/brox/gpio.c @@ -4,213 +4,19 @@ #include <boardid.h> #include <soc/gpio.h> -static const struct pad_config board_id0_1_overrides[] = { - /* B2 : VRALERT# ==> NC */ - PAD_NC(GPP_B2, NONE), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), - /* B15 : TIME_SYNC0 ==> NC */ - PAD_NC(GPP_B15, NONE), - /* C3 : SML0CLK ==> NC */ - PAD_NC(GPP_C3, NONE), - /* C4 : SML0DATA ==> NC */ - PAD_NC(GPP_C4, NONE), - /* D13 : ISH_UART0_RXD ==> PCH_I2C_CAM_SDA */ - PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3), - /* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */ - PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3), - /* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */ - PAD_CFG_GPI(GPP_F19, UP_20K, DEEP), - /* F20 : EXT_PWR_GATE# ==> HPS_RST_R */ - PAD_CFG_GPO(GPP_F20, 0, DEEP), - /* F21 : EXT_PWR_GATE2# ==> WAKE_ON_WWAN_ODL */ - PAD_NC(GPP_F21, NONE), - /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_H13, 1, DEEP), - /* H21 : IMGCLKOUT2 ==> WLAN_INT_L */ - PAD_CFG_GPI_APIC(GPP_H21, NONE, DEEP, EDGE_SINGLE, NONE), - /* GPD2: LAN_WAKE# ==> NC */ - PAD_NC(GPD2, NONE), -}; - -/* Early pad configuration in bootblock for board id < 2 */ -static const struct pad_config early_gpio_table[] = { - /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), - /* - * D1 : ISH_GP1 ==> FP_RST_ODL - * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. - * To ensure proper power sequencing for the FPMCU device, reset signal is driven low - * early on in bootblock, followed by enabling of power. Reset signal is deasserted - * later on in ramstage. Since reset signal is asserted in bootblock, it results in - * FPMCU not working after a S3 resume. This is a known issue. - */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ - PAD_CFG_GPO(GPP_E0, 0, DEEP), - /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ - PAD_CFG_GPI(GPP_E13, NONE, DEEP), - /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ - PAD_CFG_GPO(GPP_E16, 0, DEEP), - /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), - /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_F18, NONE, DEEP), - /* F21 : EXT_PWR_GATE2# ==> NC */ - PAD_NC(GPP_F21, NONE), - /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_H13, 1, DEEP), -}; - -/* Early pad configuration in bootblock for board id 2 */ -static const struct pad_config early_gpio_table_id2[] = { - /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ - PAD_CFG_GPO(GPP_A12, 1, DEEP), - /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), - /* - * D1 : ISH_GP1 ==> FP_RST_ODL - * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. - * To ensure proper power sequencing for the FPMCU device, reset signal is driven low - * early on in bootblock, followed by enabling of power. Reset signal is deasserted - * later on in ramstage. Since reset signal is asserted in bootblock, it results in - * FPMCU not working after a S3 resume. This is a known issue. - */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), - /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ - PAD_CFG_GPO(GPP_E0, 0, DEEP), - /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ - PAD_CFG_GPI(GPP_E13, NONE, DEEP), - /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ - PAD_CFG_GPO(GPP_E16, 0, DEEP), - /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), - /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_F18, NONE, DEEP), - /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ - PAD_CFG_GPO(GPP_F21, 0, DEEP), - /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_NC(GPP_H13, UP_20K), -}; - -/* Early pad configuration in bootblock for board id 4 */ -static const struct pad_config early_gpio_table_id4[] = { - /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ - PAD_CFG_GPO(GPP_A12, 1, DEEP), - /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* H6 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* H7 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - /* - * D1 : ISH_GP1 ==> FP_RST_ODL - * FP_RST_ODL comes out of reset as hi-z and does not have an external - * pull-down. To ensure proper power sequencing for the FPMCU device, - * reset signal is driven low early on in bootblock, followed by - * enabling of power. Reset signal is deasserted later on in ramstage. - * Since reset signal is asserted in bootblock, it results in FPMCU not - * working after a S3 resume. This is a known issue. - */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), - /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ - PAD_CFG_GPO(GPP_E0, 0, DEEP), - /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ - PAD_CFG_GPI(GPP_E13, NONE, DEEP), - /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ - PAD_CFG_GPO(GPP_E16, 0, DEEP), - /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), - /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_F18, NONE, DEEP), - /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ - PAD_CFG_GPO(GPP_F21, 0, DEEP), - /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_NC(GPP_H13, UP_20K), -}; static const struct pad_config romstage_gpio_table[] = { - /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), - /* Enable touchscreen, hold in reset */ - /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ - PAD_CFG_GPO(GPP_C0, 1, DEEP), - /* C1 : SMBDATA ==> USI_RST_L */ - PAD_CFG_GPO(GPP_C1, 0, DEEP), - - /* D1 : ISH_GP1 ==> FP_RST_ODL */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 0, DEEP), - - /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ - PAD_CFG_GPO(GPP_F21, 1, DEEP), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 1, DEEP), }; const struct pad_config *variant_gpio_override_table(size_t *num) { - const uint32_t id = board_id(); - if (id == BOARD_ID_UNKNOWN || id < 2) { - *num = ARRAY_SIZE(board_id0_1_overrides); - return board_id0_1_overrides; - } - *num = 0; return NULL; } -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - const uint32_t id = board_id(); - if (id == BOARD_ID_UNKNOWN || id < 2) { - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; - } else if (id >= 4) { - *num = ARRAY_SIZE(early_gpio_table_id4); - return early_gpio_table_id4; - } - - *num = ARRAY_SIZE(early_gpio_table_id2); - return early_gpio_table_id2; -} - const struct pad_config *variant_romstage_gpio_table(size_t *num) { *num = ARRAY_SIZE(romstage_gpio_table); -- To view, visit https://review.coreboot.org/c/coreboot/+/79295?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e Gerrit-Change-Number: 79295 Gerrit-PatchSet: 5 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yen-hsing Lee <yen-hsing.lee(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: nb/amd/pi/00730F01: drop leftover family10_northbridge PCI driver
by Felix Held (Code Review) Dec. 1, 2023

Dec. 1, 2023

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79094?usp=email ) Change subject: nb/amd/pi/00730F01: drop leftover family10_northbridge PCI driver ...................................................................... nb/amd/pi/00730F01: drop leftover family10_northbridge PCI driver This is likely a copy-paste leftover, since this SoC neither has a PCI device with the device ID 0x1200 nor is family 10h. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7095f208a7503545ea012241d058692a510109f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79094 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 0 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 3ac94e5..be4e75a 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -649,12 +649,6 @@ .device = PCI_DID_AMD_16H_MODEL_303F_NB_HT, }; -static const struct pci_driver family10_northbridge __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_10H_NB_HT, -}; - static void fam16_finalize(void *chip_info) { struct device *dev; -- To view, visit https://review.coreboot.org/c/coreboot/+/79094?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7095f208a7503545ea012241d058692a510109f3 Gerrit-Change-Number: 79094 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: nb/amd/pi/00730F01: drop leftover family10_northbridge PCI driver
by Matt DeVillier (Code Review) Dec. 1, 2023

Dec. 1, 2023

Attention is currently required from: Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79094?usp=email ) Change subject: nb/amd/pi/00730F01: drop leftover family10_northbridge PCI driver ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79094?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7095f208a7503545ea012241d058692a510109f3 Gerrit-Change-Number: 79094 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 01 Dec 2023 00:05:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0