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Change in coreboot[master]: Herobrine T32 scripts working in standalone environment
by Ravi kumar (Code Review) Sept. 11, 2024

Sept. 11, 2024

Hello mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47365 to review the following change. Change subject: Herobrine T32 scripts working in standalone environment ...................................................................... Herobrine T32 scripts working in standalone environment Change-Id: I451344d887c7b6c0983594e4dea4ca2b030d65f1 --- M util/qualcomm/scripts/cmm/debug_cb_common.cmm A util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm 2 files changed, 123 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/47365/1 diff --git a/util/qualcomm/scripts/cmm/debug_cb_common.cmm b/util/qualcomm/scripts/cmm/debug_cb_common.cmm index cbcb004..a722864 100644 --- a/util/qualcomm/scripts/cmm/debug_cb_common.cmm +++ b/util/qualcomm/scripts/cmm/debug_cb_common.cmm @@ -126,6 +126,11 @@ else d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /nocode + print "Hacking DDR ranges..." + B::D.S MD:0x1485B000 %LE %Long 0x80000000 + B::D.S MD:0x1485B004 %LE %Long 0 + B::D.S MD:0x1485B008 %LE %Long 0x80000000 + print %String "Now the control is in ROMStage, press enter after debugging to go to next stage" print %String "Press enter to go to next stage" enter diff --git a/util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm b/util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm new file mode 100644 index 0000000..8693a5f --- /dev/null +++ b/util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm @@ -0,0 +1,118 @@ +;============================================================================ +;## SPDX-License-Identifier: GPL-2.0-only +;============================================================================ +; Name: +; debug_cb_trogdor.cmm +; +; Description: +; Debug coreboot trogdor front-end +;============================================================================ + +;============================================================================ +; CMM script variables +;============================================================================ + +LOCAL &TargetPkg + +GLOBAL &BBEntryAddr // Bootblock Entry +GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec +GLOBAL &VEREntryAddr // Verstage Entry +GLOBAL &ROMEntryAddr // Romstage Entry +GLOBAL &QCLEntryAddr // QCLstage Entry +GLOBAL &RAMEntryAddr // Ramstage Entry +GLOBAL &BL31EntryAddr // BL31 Entry +GLOBAL &DCEntryAddr // Depthcharge Entry + +GLOBAL &PreRamConsoleAddr +GLOBAL &RamConsoleAddr +GLOBAL &PreRamCbfsCache +GLOBAL &VBoot2Work +GLOBAL &Stack +GLOBAL &Ttb +GLOBAL &Timestamp +GLOBAL &CbmemTop +GLOBAL &PostRamCbfsCache + +GLOBAL &CBTablePtr + +;============================================================================ + +;--------------------------------------------------- +; Entry point +;--------------------------------------------------- +ENTRY &ImageName &RegAddress + + // Later these can be parameterized + &TargetPkg="herobrinePkg" + + // These settings come from .../src/soc/qualcomm/sc7280/memlayout.ld + &BBEntryAddr=0x14819000 + &VEREntryAddr=0x14680000 + &ROMEntryAddr=0x14680000 + &QCLEntryAddr=0x1486c950 + &RAMEntryAddr=0xA0800000 + &BL31EntryAddr=0x80C00000 + &DCEntryAddr=0xF1000000 + &KernelEntryAddr=0xD0000000 + + &PreRamConsoleAddr=0x14834800 + &VBoot2Work=0x1484F000 + &Stack=0x1484B000 + &Ttb=0x1483D000 + &Timestamp=0x1483C800 + &PreRamCbfsCache=0x14823000 + &CbmemTop=0x280000000 + &PostRamCbfsCache=0x9F800000 + // End of memlayout.ld settings + + // Common commands irrespective of &Mode + PATH + &CwDir=os.pwd() + PATH + &CwDir + + // position at top of coreboot tree + // find depth count for source loading + cd ..\..\..\.. + &srcpath=os.pwd() + + +;--------------------------------------------------- +; Setup area and log +;--------------------------------------------------- + area.clear + area.reset + area.create CB_Logs 1000. 8192. + area.select CB_Logs + + area.view CB_Logs + + PRINT %String "Source Path: &srcpath" + + symbol.sourcepath.setbasedir &srcpath\src + + // Make parsing simple, upper-case parameters + &ImageName=STRING.UPR("&ImageName") + if (STR.CP("&ImageName","0X*")) + ( + &RegAddress=&ImageName + &ImageName="" + ) + &RegAddress=STRING.UPR("&RegAddress") + + PRINT %String "ImageName: &ImageName" + PRINT %String "RegAddress: &RegAddress" + + ;sys.d + ;sys.up + b.d + y.reset + + if (STR.CP("&RegAddress","0X*")) + D.S EZAXI:&RegAddress %LE %Long 0x80000000 + + go &BBEntryAddr + wait !run() + + DO debug_cb_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName + + enddo -- To view, visit https://review.coreboot.org/c/coreboot/+/47365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I451344d887c7b6c0983594e4dea4ca2b030d65f1 Gerrit-Change-Number: 47365 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

6 43

Change in coreboot[master]: sb/intel/i82371eb: Leave I/O ports 0x2e-0x2f unclaimed
by Keith Hui (Code Review) July 23, 2024

July 23, 2024

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41458 ) Change subject: sb/intel/i82371eb: Leave I/O ports 0x2e-0x2f unclaimed ...................................................................... sb/intel/i82371eb: Leave I/O ports 0x2e-0x2f unclaimed This change reflects vendor setup for asus/p3b-f. Change-Id: I11972b650d95a48e4d372defe201cc9e743d5b30 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/acpi/i82371eb.asl 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/41458/1 diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl index 4a1b385..f0f6a0c 100644 --- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -34,7 +34,9 @@ /* Aliased DMA ports */ IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) /* Aliased PIC ports */ - IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, ) + /* Do not claim 0x2e-0x2f, per P3B-F vendor DSDT */ + IO (Decode16, 0x0022, 0x0022, 0x01, 0x0C, ) + IO (Decode16, 0x0030, 0x0030, 0x01, 0x10, ) /* Aliased timer ports */ IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, ) IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, ) -- To view, visit https://review.coreboot.org/c/coreboot/+/41458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11972b650d95a48e4d372defe201cc9e743d5b30 Gerrit-Change-Number: 41458 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 10

Change in ...coreboot[master]: autoport: Add support for Haswell-LynxPoint platform
by Iru Cai (vimacs) (Code Review) July 14, 2024

July 14, 2024

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30890 to review the following change. Change subject: autoport: Add support for Haswell-LynxPoint platform ...................................................................... autoport: Add support for Haswell-LynxPoint platform It can now generate a buildable source for Clevo W650SZ. TODO: - Support Lynx Point LP (GPIO registers differ from non-LP) - Use PCH HD-Audio in azilia instead of the CPU/Northbridge HD-Audio Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/azalia.go A util/autoport/haswell.go A util/autoport/lynxpoint.go M util/autoport/main.go 4 files changed, 625 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30890/1 diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go index c525189..3090dd0 100644 --- a/util/autoport/azalia.go +++ b/util/autoport/azalia.go @@ -62,4 +62,9 @@ RegisterPCI(0x8086, 0x1c20, azalia{}) /* C216/ivybridge */ RegisterPCI(0x8086, 0x1e20, azalia{}) + /* Haswell */ + RegisterPCI(0x8086, 0x0c0c, azalia{}) + /* Lynx Point */ + RegisterPCI(0x8086, 0x8c20, azalia{}) + RegisterPCI(0x8086, 0x9c20, azalia{}) } diff --git a/util/autoport/haswell.go b/util/autoport/haswell.go new file mode 100644 index 0000000..d3c9d9f --- /dev/null +++ b/util/autoport/haswell.go @@ -0,0 +1,119 @@ +package main + +type haswellmc struct { + variant string +} + +func (i haswellmc) Scan(ctx Context, addr PCIDevData) { + inteltool := ctx.InfoSource.GetInteltool() + + /* FIXME:XX Move this somewhere else. */ + MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h") + MainboardEnable += (` /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +`) + + DevTree = DevTreeNode{ + Chip: "northbridge/intel/haswell", + MissingParent: "northbridge", + Comment: "FIXME: check gfx.ndid and gfx.did", + Registers: map[string]string{ + "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7), + "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7), + "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7), + "gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3), + "gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff), + "gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff), + "gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff), + "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff), + "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff), + "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]), + "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001), + "gpu_ddi_e_connected": FormatBool(((inteltool.IGD[0x64000] >> 4) & 1) == 0), + /* FIXME:XX hardcoded. */ + "gfx.ndid": "3", + "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/haswell", + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + { + Chip: "lapic", + Dev: 0xacac, + Disabled: true, + }, + }, + Registers: map[string]string{ + /* FIXME:XX hardcoded. */ + "c1_acpower": "1", + "c2_acpower": "3", + "c3_acpower": "5", + "c1_battery": "1", + "c2_battery": "3", + "c3_battery": "5", + }, + }, + }, + }, + + { + Chip: "domain", + Dev: 0, + PCIController: true, + ChildPCIBus: 0, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x3, Func: 0}, writeEmpty: true, additionalComment: "Mini-HD audio"}, + }, + }, + }, + } + + PutPCIDev(addr, "Host bridge") + + /* FIXME:XX some configs are unsupported. */ + + KconfigBool["CPU_INTEL_HASWELL"] = true + KconfigBool["NORTHBRIDGE_INTEL_HASWELL"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + KconfigInt["MAX_CPUS"] = 8 + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/common/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/haswell/acpi/haswell.asl", + }, DSDTInclude{ + File: "drivers/intel/gma/acpi/default_brightness_levels.asl", + }) +} + +func init() { + RegisterPCI(0x8086, 0x0c00, haswellmc{variant: "Desktop"}) + RegisterPCI(0x8086, 0x0c04, haswellmc{variant: "Mobile"}) + RegisterPCI(0x8086, 0x0a04, haswellmc{variant: "ULT"}) + RegisterPCI(0x8086, 0x0c08, haswellmc{variant: "Server"}) + for _, id := range []uint16{ + 0x0402, 0x0412, 0x0422, + 0x0406, 0x0416, 0x0426, + 0x0d16, 0x0d26, 0x0d36, + 0x0a06, 0x0a16, 0x0a26, + } { + RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}}) + } +} diff --git a/util/autoport/lynxpoint.go b/util/autoport/lynxpoint.go new file mode 100644 index 0000000..df20c3f --- /dev/null +++ b/util/autoport/lynxpoint.go @@ -0,0 +1,495 @@ +package main + +import ( + "fmt" + "os" +) + +type lynxpoint struct { + variant string + node *DevTreeNode +} + +func (b lynxpoint) writeGPIOSet(ctx Context, sb *os.File, + val uint32, set uint, partno int, constraint uint32) { + + max := uint(32) + if set == 3 { + max = 12 + } + + bits := [6][2]string{ + {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"}, + {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"}, + {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"}, + {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"}, + {"GPIO_NO_INVERT", "GPIO_INVERT"}, + {"GPIO_NO_BLINK", "GPIO_BLINK"}, + } + + for i := uint(0); i < max; i++ { + if ((constraint>>i)&1 == 1) { + fmt.Fprintf(sb, " .gpio%d = %s,\n", + (set-1)*32+i, + bits[partno][(val>>i)&1]) + } + } +} + +func (b lynxpoint) GPIO(ctx Context, inteltool InteltoolData) { + var constraint uint32 + gpio := Create(ctx, "gpio.c") + defer gpio.Close() + + AddROMStageFile("gpio.c", "") + + Add_gpl(gpio) + gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n") + + /* TODO: different in LP PCH */ + addresses := [3][6]int{ + {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18}, + {0x30, 0x34, 0x38, 0x64, -1, -1}, + {0x40, 0x44, 0x48, 0x68, -1, -1}, + } + + for set := 1; set <= 3; set++ { + for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} { + addr := addresses[set-1][partno] + if addr < 0 { + continue + } + fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n", + set, set, part) + + constraint = 0xffffffff + switch part { + case "direction": + /* Ignored on native mode */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + case "level": + /* Level doesn't matter for input */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])] + case "reset": + /* Only show reset */ + constraint = inteltool.GPIO[uint16(addresses[set-1][3])] + case "invert": + /* Only on input and only show inverted GPIO */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][1])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][4])] + case "blink": + /* Only on output and only show blinking GPIO */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][5])] + } + b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint) + gpio.WriteString("};\n\n") + } + } + + gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; +`) +} + +func (b lynxpoint) IsPCIeHotplug(ctx Context, port int) bool { + portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}] + if !ok { + return false + } + return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0 +} + +func (b lynxpoint) GetGPIOHeader() string { + return "southbridge/intel/lynxpoint/pch.h" +} + +func (b lynxpoint) EnableGPE(in int) { + b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2" +} + +func (b lynxpoint) EncodeGPE(in int) int { + return in + 0x10 +} + +func (b lynxpoint) DecodeGPE(in int) int { + return in - 0x10 +} + +func (b lynxpoint) NeedRouteGPIOManually() { + b.node.Comment += ", FIXME: set gpiX_routing for EC support" +} + +func (b lynxpoint) Scan(ctx Context, addr PCIDevData) { + + SouthBridge = &b + + inteltool := ctx.InfoSource.GetInteltool() + b.GPIO(ctx, inteltool) + + KconfigBool["SOUTHBRIDGE_INTEL_LYNXPOINT"] = true + if b.variant == "Lynx Point LP" { + KconfigBool["INTEL_LYNXPOINT_LP"] = true + } + KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true + KconfigInt["USBDEBUG_HCD_INDEX"] = 2 + KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this" + dmi := ctx.InfoSource.GetDMI() + if dmi.Vendor == "LENOVO" { + KconfigInt["DRAM_RESET_GATE_GPIO"] = 10 + } else { + KconfigInt["DRAM_RESET_GATE_GPIO"] = 60 + } + KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this" + + /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices. + But most systems don't have any of those. But the config needs to be set + nevertheless. So set it to southbridge subsys/subvendor. */ + KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e])) + KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30])) + + ich9GetFlashSize(ctx) + + DSDTDefines = append(DSDTDefines, + DSDTDefine{ + Key: "BRIGHTNESS_UP", + Value: "\\_SB.PCI0.GFX0.INCB", + }, + DSDTDefine{ + Key: "BRIGHTNESS_DOWN", + Value: "\\_SB.PCI0.GFX0.DECB", + }, + DSDTDefine{ + Key: "ACPI_VIDEO_DEVICE", + Value: "\\_SB.PCI0.GFX0", + }) + + /* SPI init */ + MainboardIncludes = append(MainboardIncludes, "southbridge/intel/lynxpoint/pch.h") + + cur := DevTreeNode{ + Chip: "southbridge/intel/lynxpoint", + Comment: "Intel Series 8 Lynx Point PCH", + + Registers: map[string]string{ + "pirqa_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x60]), + "pirqb_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x61]), + "pirqc_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x62]), + "pirqd_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x63]), + "pirqe_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x68]), + "pirqf_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x69]), + "pirqg_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6a]), + "pirqh_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6b]), + "sata_ahci": "1", + "gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]), + "gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]), + "gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]), + "gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]), + "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"}, + }, + } + + b.node = &cur + + PutPCIChip(addr, cur) + PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/platform.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/pch.asl", + }) + + sb := Create(ctx, "romstage.c") + defer sb.Close() + Add_gpl(sb) + sb.WriteString(`#include <stdint.h> +#include <cpu/intel/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { +`) + RestoreDIRRoute(sb, "D31IR", uint16(inteltool.RCBA[0x3140])) + RestoreDIRRoute(sb, "D29IR", uint16(inteltool.RCBA[0x3144])) + RestoreDIRRoute(sb, "D28IR", uint16(inteltool.RCBA[0x3146])) + RestoreDIRRoute(sb, "D27IR", uint16(inteltool.RCBA[0x3148])) + RestoreDIRRoute(sb, "D26IR", uint16(inteltool.RCBA[0x314c])) + RestoreDIRRoute(sb, "D25IR", uint16(inteltool.RCBA[0x3150])) + RestoreDIRRoute(sb, "D22IR", uint16(inteltool.RCBA[0x315c])) + RestoreDIRRoute(sb, "D20IR", uint16(inteltool.RCBA[0x3160])) + + sb.WriteString(` + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +};`) + + sb.WriteString(` + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry(unsigned long bist) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = DEFAULT_PCIEXBAR, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 1, /* desktop/server, FIXME: check this */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* FIXME: check this */ + .ec_present = 0, + .dimm_channel0_disabled = 0, /* FIXME: leave channel 0 enabled */ + .dimm_channel1_disabled = 0, /* FIXME: leave channel 1 enabled */ + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ +`) + + pdo1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x64] + ocmap1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x74:0x78] + pdo2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x64] + ocmap2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x74:0x78] + + for port := uint(0); port < 14; port++ { + var port_oc int = -1 + var port_pos string + var port_disable uint8 + + if port < 8 { + port_disable = (pdo1 >> port) & 1 + for oc := 0; oc < 4; oc++ { + if ((ocmap1[oc] & (1 << port)) != 0) { + port_oc = oc + break + } + } + } else { + port_disable = (pdo2 >> (port - 8)) & 1 + for oc := 0; oc < 4; oc++ { + if ((ocmap2[oc] & (1 << (port - 8))) != 0) { + port_oc = oc + 4 + break + } + } + } + if port_disable == 1 { + port_pos = "USB_PORT_SKIP" + } else { + port_pos = "USB_PORT_BACK_PANEL" + } + if port_oc == -1 { + fmt.Fprintf(sb, " { 0x0040, %d, USB_OC_PIN_SKIP, %s },\n", + (port_disable ^ 1), port_pos) + } else { + fmt.Fprintf(sb, " { 0x0040, %d, %d, %s },\n", + (port_disable ^ 1), port_oc, port_pos) + } + } + + sb.WriteString(` }, + .usb3_ports = { +`) + + xpdo := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xe8] + u3ocm := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xc8:0xd0] + + for port := uint(0); port < 6; port++ { + var port_oc int = -1 + port_disable := (xpdo >> port) & 1 + for oc := 0; oc < 8; oc++ { + if (u3ocm[oc] & (1 << port)) != 0 { + port_oc = oc + break + } + } + if port_oc == -1 { + fmt.Fprintf(sb, " { %d, USB_OC_PIN_SKIP },\n", + (port_disable ^ 1)) + } else { + fmt.Fprintf(sb, " { %d, %d },\n", + (port_disable ^ 1), port_oc) + } + } + + sb.WriteString(` }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + .bist = bist, + }; + + romstage_common(&romstage_params); +}`) + + gnvs := Create(ctx, "acpi_tables.c") + defer gnvs.Close() + + Add_gpl(gnvs) + gnvs.WriteString(`#include <southbridge/intel/lynxpoint/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} +`) + +} + +func init() { + for _, id := range []uint16 { + 0x8c41, 0x8c49, 0x8c4b, 0x8c4f, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Mobile"}) + } + + for _, id := range []uint16 { + 0x8c42, 0x8c44, 0x8c46, 0x8c4a, + 0x8c4c, 0x8c4e, 0x8c50, 0x8c5c, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Desktop"}) + } + + for _, id := range []uint16 { + 0x8c52, 0x8c54, 0x8c56, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Server"}) + } + + for _, id := range []uint16 { + 0x9c41, 0x9c43, 0x9c45, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point LP"}) + } + + /* PCIe bridge */ + for _, id := range []uint16{ + 0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e, + 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* SMBus controller */ + RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"}) + RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"}) + RegisterPCI(0x8086, 0x8c22, GenericPCI{MissingParent: "smbus"}) + RegisterPCI(0x8086, 0x9c22, GenericPCI{MissingParent: "smbus"}) + + /* SATA */ + for _, id := range []uint16{ + 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, + 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, + 0x9c03, 0x9c05, 0x9c07, 0x9c0f, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* EHCI */ + for _, id := range []uint16{ + 0x9c26, 0x8c26, 0x8c2d, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* XHCI */ + RegisterPCI(0x8086, 0x8c31, GenericPCI{}) + RegisterPCI(0x8086, 0x9c31, GenericPCI{}) + + /* ME and children */ + for _, id := range []uint16{ + 0x8c3a, 0x8c3b, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* Ethernet */ + RegisterPCI(0x8086, 0x8c33, GenericPCI{}) +} diff --git a/util/autoport/main.go b/util/autoport/main.go index 05a829b..c1920a7 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -236,6 +236,12 @@ pcidev.ConfigDump[addr]) } +func RestoreDIRRoute(f *os.File, regname string, val uint16) { + fmt.Fprintf(f, " RCBA_SET_REG_16(%s, DIR_ROUTE(PIRQ%c, PIRQ%c, PIRQ%c, PIRQ%c)),\n", + regname, 'A' + (val & 7), 'A' + ((val >> 4) & 7), + 'A' + ((val >> 8) & 7), 'A' + ((val >> 12) & 7)) +} + func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) { fmt.Fprintf(f, " pci_write_config32(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n", pcidev.Bus, pcidev.Dev, pcidev.Func, addr, -- To view, visit https://review.coreboot.org/c/coreboot/+/30890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a Gerrit-Change-Number: 30890 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

15 92

Change in coreboot[master]: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant
by Iru Cai (vimacs) (Code Review) June 16, 2024

June 16, 2024

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39398 to review the following change. Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ...................................................................... mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/hp/8560w.md A Documentation/mainboard/hp/8560w_flash.webp M Documentation/mainboard/index.md M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig.name A src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt A src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb 10 files changed, 477 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39398/1 diff --git a/Documentation/mainboard/hp/8560w.md b/Documentation/mainboard/hp/8560w.md new file mode 100644 index 0000000..6a7c197 --- /dev/null +++ b/Documentation/mainboard/hp/8560w.md @@ -0,0 +1,82 @@ +# HP EliteBook 8560w + +This page describes how to run coreboot on the [HP EliteBook 8560w]. + +## Required proprietary blobs + +- Intel Firmware Descriptor, ME and GbE firmware +- EC: please read [EliteBook Series](elitebook_series) + +## Flashing instructions + +HP EliteBook 8560w has an 8MB SOIC-8 flash chip on the bottom of the +mainboard. You just need to remove the service cover, and use an SOIC-8 +clip to read and flash the chip. + +![8560w_chip_location](8560w_flash.webp) + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Model | MX25L6406E | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | no | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| In circuit flashing | yes | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +## Untested + +- mainboards with 4 memory slots + +## Working + +- i7-2720QM, 8G+8G +- Arch Linux boot from SeaBIOS payload +- EHCI debug: the port is beside the eSATA port +- SATA +- eSATA +- USB2 and USB3 +- keyboard +- Gigabit Ethernet +- WLAN +- WWAN +- VGA and DisplayPort +- audio +- EC ACPI +- Using `me_cleaner` +- dock: PS/2 keyboard, USB, DisplayPort +- TPM +- S3 suspend/resume + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | SMSC LPC47n217 | ++------------------+--------------------------------------------------+ +| EC | SMSC KBC1126 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[HP EliteBook 8560w]: https://support.hp.com/us-en/product/hp-elitebook-8560w-mobile-workstation/… diff --git a/Documentation/mainboard/hp/8560w_flash.webp b/Documentation/mainboard/hp/8560w_flash.webp new file mode 100644 index 0000000..b8295bc --- /dev/null +++ b/Documentation/mainboard/hp/8560w_flash.webp Binary files differ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index e46e0f3..a20a0bf 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -55,6 +55,7 @@ ### EliteBook series - [EliteBook common](hp/elitebook_series.md) +- [EliteBook 8560w](hp/8560w.md) - [EliteBook 8760w](hp/8760w.md) ## Intel diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig index d0105ff..0ec0d27 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig @@ -37,6 +37,7 @@ default "2760p" if BOARD_HP_2760P default "8460p" if BOARD_HP_8460P default "8470p" if BOARD_HP_8470P + default "8560w" if BOARD_HP_8560W default "8770w" if BOARD_HP_8770W default "folio_9470m" if BOARD_HP_FOLIO_9470M default "revolve_810_g1" if BOARD_HP_REVOLVE_810_G1 @@ -47,6 +48,7 @@ default "EliteBook 2760p" if BOARD_HP_2760P default "EliteBook 8460p" if BOARD_HP_8460P default "EliteBook 8470p" if BOARD_HP_8470P + default "EliteBook 8560w" if BOARD_HP_8560W default "EliteBook 8770w" if BOARD_HP_8770W default "EliteBook Folio 9470m" if BOARD_HP_FOLIO_9470M default "EliteBook Revolve 810 G1" if BOARD_HP_REVOLVE_810_G1 @@ -75,6 +77,7 @@ default 1 if BOARD_HP_2760P default 1 if BOARD_HP_8460P default 2 if BOARD_HP_8470P + default 1 if BOARD_HP_8560W default 2 if BOARD_HP_8770W default 0 if BOARD_HP_FOLIO_9470M default 2 if BOARD_HP_REVOLVE_810_G1 # FIXME: check this diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name index c4a8662..360373e 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name @@ -61,6 +61,17 @@ select SOUTHBRIDGE_INTEL_C216 select SUPERIO_SMSC_LPC47N217 +config BOARD_HP_8560W + bool "EliteBook 8560w" + + select BOARD_HP_SNB_IVB_LAPTOPS + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_SMSC_LPC47N217 + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + config BOARD_HP_8770W bool "EliteBook 8770w" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt new file mode 100644 index 0000000..af1e296 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-8560w-mobile-workstation/… +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c new file mode 100644 index 0000000..57eafe2 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/smsc/lpc47n217/lpc47n217.h> +#include <ec/hp/kbc1126/ec.h> + +#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* USB0 */ + { 1, 1, 0 }, /* USB1 */ + { 1, 1, 1 }, /* eSATA */ + { 1, 1, 1 }, /* camera */ + { 0, 0, 2 }, + { 1, 0, 2 }, /* bluetooth */ + { 0, 0, 3 }, + { 1, 0, 3 }, + { 0, 1, 4 }, + { 1, 1, 4 }, /* WWAN */ + { 1, 0, 5 }, + { 1, 0, 5 }, /* dock */ + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c new file mode 100644 index 0000000..29358aa --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c new file mode 100644 index 0000000..d7573d5 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c1631, /* Subsystem ID */ + + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c1631), + AZALIA_PIN_CFG(0, 0x0a, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0b, 0x0421401f), + AZALIA_PIN_CFG(0, 0x0c, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0x90a60130), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb new file mode 100644 index 0000000..d716b46 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb @@ -0,0 +1,60 @@ +# +# This file is part of the coreboot project. +# +# Copyright 2020 The coreboot project Authors. +# +# SPDX-License-Identifier: GPL-2.0-or-later +# + +chip northbridge/intel/sandybridge + device domain 0x0 on + subsystemid 0x103c 0x1631 inherit + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 off end # Internal graphics + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" + # HDD(0), ODD(1), eSATA(4) + register "sata_port_map" = "0x3b" + + device pci 1c.0 on end # PCIe Port #1, WWAN + device pci 1c.1 on end # PCIe Port #2, ExpressCard + device pci 1c.2 on end # PCIe Port #3, SD/MMC + device pci 1c.3 on end # PCIe Port #4, WLAN + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8, NEC USB 3.0 Host Controller + device pci 1f.0 on # LPC bridge + chip ec/hp/kbc1126 + register "ec_data_port" = "0x60" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off end # COM2 + end + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/39398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 Gerrit-Change-Number: 39398 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

6 34

Change in coreboot[master]: cpu/x86/smm: Add save state ops for different save states.
by Arthur Heymans (Code Review) June 13, 2024

June 13, 2024

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45472 ) Change subject: cpu/x86/smm: Add save state ops for different save states. ...................................................................... cpu/x86/smm: Add save state ops for different save states. Change-Id: I67ab44fbdca5fac5837d32ffda5caad61e534473 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/cpu/amd/smm/amd64_save_state.c A src/cpu/intel/smm/em64t100_save_state.c A src/cpu/intel/smm/em64t101_save_state.c M src/cpu/x86/Kconfig M src/cpu/x86/smm/Makefile.inc A src/cpu/x86/smm/legacy_save_state.c 6 files changed, 476 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/45472/1 diff --git a/src/cpu/amd/smm/amd64_save_state.c b/src/cpu/amd/smm/amd64_save_state.c new file mode 100644 index 0000000..6aabb56 --- /dev/null +++ b/src/cpu/amd/smm/amd64_save_state.c @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <cpu/x86/save_state.h> +#include <cpu/amd/amd64_save_state.h> + +static void *amd64_get_reg_base(const enum cpu_reg reg, const int node) +{ + const amd64_smm_state_save_area_t *save_state = + (const amd64_smm_state_save_area_t *)smm_get_save_state(node); + + switch (reg) { + case RAX: + return (void *)&save_state->rax; + case RBX: + return (void *)&save_state->rbx; + case RCX: + return (void *)&save_state->rcx; + case RDX: + return (void *)&save_state->rdx; + } + + return NULL; +} + +enum get_set { + GET, + SET +}; + +static int amd64_get_set(const enum get_set op_type, const enum cpu_reg reg, + const int node, void *in_out, const uint8_t length) +{ + + void *reg_base = amd64_get_reg_base(reg, node); + + if (!reg_base) + return -1; + + switch (length) { + case 1: + case 2: + case 4: + case 8: + switch (op_type) { + case GET: + memcpy(in_out, reg_base, length); + return 0; + case SET: + memcpy(reg_base, in_out, length); + } + } + + return -1; +} + +static int amd64_get_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length) +{ + return amd64_get_set(GET, reg, node, out, length); +} + +static int amd64_set_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length) +{ + return amd64_get_set(SET, reg, node, in, length); +} + +/* bits in smm_io_trap */ +#define SMM_IO_TRAP_PORT_OFFSET 16 +#define SMM_IO_TRAP_PORT_ADDRESS_MASK 0xffff +#define SMM_IO_TRAP_RW (1 << 0) +#define SMM_IO_TRAP_VALID (1 << 1) + +static inline u16 get_io_address(u32 info) +{ + return ((info >> SMM_IO_TRAP_PORT_OFFSET) & + SMM_IO_TRAP_PORT_ADDRESS_MASK); +} + +static int amd64_apmc_node(u8 cmd) +{ + amd64_smm_state_save_area_t *state; + u32 smm_io_trap; + int node; + + for (node = 0; node < CONFIG_MAX_CPUS; node++) { + state = smm_get_save_state(node); + smm_io_trap = state->smm_io_trap_offset; + + /* Check for Valid IO Trap Word (bit1==1) */ + if (!(smm_io_trap & SMM_IO_TRAP_VALID)) + continue; + /* Make sure it was a write (bit0==0) */ + if (smm_io_trap & SMM_IO_TRAP_RW) + continue; + /* Check for APMC IO port */ + if (pm_acpi_smi_cmd_port() != get_io_address(smm_io_trap)) + continue; + /* Check AL against the requested command */ + reg_al = state->rax; + if (reg_al == cmd) + return node; + } + + return -1; +} + +static const uint32_t revisions[] = { + 0x00020064, + 0x00030064, + SMM_REV_INVALID, +}; + +static const struct smm_save_state_ops ops = { + .revision_table = revisions, + .get_reg = amd64_get_reg, + .set_reg = amd64_set_reg, + .apmc_node = amd64_apmc_node, +}; + +const struct smm_save_state_ops *amd64_ops = &ops; diff --git a/src/cpu/intel/smm/em64t100_save_state.c b/src/cpu/intel/smm/em64t100_save_state.c new file mode 100644 index 0000000..c654fd9 --- /dev/null +++ b/src/cpu/intel/smm/em64t100_save_state.c @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <cpu/x86/save_state.h> +#include <cpu/intel/em64t100_save_state.h> + +static void *em64t100_get_reg_base(const enum cpu_reg reg, const int node) +{ + const em64t100_smm_state_save_area_t *save_state = + (const em64t100_smm_state_save_area_t *)smm_get_save_state(node); + + switch (reg) { + case RAX: + return (void *)&save_state->rax; + case RBX: + return (void *)&save_state->rbx; + case RCX: + return (void *)&save_state->rcx; + case RDX: + return (void *)&save_state->rdx; + } + + return NULL; +} + +enum get_set { + GET, + SET +}; + +static int em64t100_get_set(const enum get_set op_type, const enum cpu_reg reg, + const int node, void *in_out, const uint8_t length) +{ + + void *reg_base = em64t100_get_reg_base(reg, node); + + if (!reg_base) + return -1; + + switch (length) { + case 1: + case 2: + case 4: + case 8: + switch (op_type) { + case GET: + memcpy(in_out, reg_base, length); + return 0; + case SET: + memcpy(reg_base, in_out, length); + } + } + + return -1; +} + +static int em64t100_get_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length) +{ + return em64t100_get_set(GET, reg, node, out, length); +} + +static int em64t100_set_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length) +{ + return em64t100_get_set(SET, reg, node, in, length); +} + +static int em64t100_apmc_node(u8 cmd) +{ + em64t100_smm_state_save_area_t *state; + int node; + + for (node = 0; node < CONFIG_MAX_CPUS; node++) { + state = smm_get_save_state(node); + + /* Check for Synchronous IO (bit0 == 1) */ + if (!(state->io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (state->io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + + /* Check AX against the requested command */ + if ((state->rax & 0xff) != cmd) + continue; + + return node; + } + + return -1; +} + +static const uint32_t revisions[] = { + 0x00030100, + SMM_REV_INVALID, +}; + +static const struct smm_save_state_ops ops = { + .revision_table = revisions, + .get_reg = em64t100_get_reg, + .set_reg = em64t100_set_reg, + .apmc_node = em64t100_apmc_node, +}; + +const struct smm_save_state_ops *em64t100_ops = &ops; diff --git a/src/cpu/intel/smm/em64t101_save_state.c b/src/cpu/intel/smm/em64t101_save_state.c new file mode 100644 index 0000000..2d1f9bc --- /dev/null +++ b/src/cpu/intel/smm/em64t101_save_state.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <cpu/x86/save_state.h> +#include <cpu/intel/em64t101_save_state.h> + +static void *em64t101_get_reg_base(const enum cpu_reg reg, const int node) +{ + const em64t101_smm_state_save_area_t *save_state = (const em64t101_smm_state_save_area_t *)smm_get_save_state(node); + + switch (reg) { + case RAX: + return (void *)&save_state->rax; + case RBX: + return (void *)&save_state->rbx; + case RCX: + return (void *)&save_state->rcx; + case RDX: + return (void *)&save_state->rdx; + } + + return NULL; +} + +enum get_set { + GET, + SET +}; + +static int em64t101_get_set(const enum get_set op_type, const enum cpu_reg reg, + const int node, void *in_out, const uint8_t length) +{ + + void *reg_base = em64t101_get_reg_base(reg, node); + + if (!reg_base) + return -1; + + switch (length) { + case 1: + case 2: + case 4: + case 8: + switch (op_type) { + case GET: + memcpy(in_out, reg_base, length); + return 0; + case SET: + memcpy(reg_base, in_out, length); + } + } + + return -1; +} + +static int em64t101_get_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length) +{ + return em64t101_get_set(GET, reg, node, out, length); +} + +static int em64t101_set_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length) +{ + return em64t101_get_set(SET, reg, node, in, length); +} + +static int em64t101_apmc_node(u8 cmd) +{ + em64t101_smm_state_save_area_t *state; + int node; + + for (node = 0; node < CONFIG_MAX_CPUS; node++) { + state = smm_get_save_state(node); + + /* Check for Synchronous IO (bit0 == 1) */ + if (!(state->io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (state->io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + + /* Check AX against the requested command */ + if ((state->rax & 0xff) != cmd) + continue; + + return node; + } + + return -1; +} + +static const uint32_t revisions[] = { + 0x00030101, + SMM_REV_INVALID, +}; + +static const struct smm_save_state_ops ops = { + .revision_table = revisions, + .get_reg = em64t101_get_reg, + .set_reg = em64t101_set_reg, + .apmc_node = em64t101_apmc_node, +}; + +const struct smm_save_state_ops *em64t101_ops = &ops; diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 5394cd0..ad6f7b7 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -96,6 +96,32 @@ default y depends on !(NO_SMM || SMM_ASEG) +config X86_LEGACY_SAVE_STATE + bool + help + Select this on platforms that have CPUs with a legacy SMM save + state area. + +config X86_EM64T100_SAVE_STATE + bool + help + Select this on platforms that have CPUs with a SMM save + state area revision 0x00030100. These are mostly small + core (atom) Intel targets. + +config X86_EM64T101_SAVE_STATE + bool + help + Select this on platforms that have CPUs with a SMM save + state area revision 0x00030101. These are mostly big + core (core i) Intel targets. + +config X86_AMD64_SAVE_STATE + bool + help + Select this on platforms that have CPUs with a AMD64 save + state area. + if SMM_TSEG config SMM_MODULE_HEAP_SIZE diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index e0ee5c0..cb62023 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -29,6 +29,10 @@ endif smm-y += save_state.c +smm-$(CONFIG_X86_LEGACY_SAVE_STATE) += legacy_save_state.c +smm-$(CONFIG_X86_EM64T100_SAVE_STATE) += ../../intel/smm/em64t100_save_state.c +smm-$(CONFIG_X86_EM64T101_SAVE_STATE) += ../../intel/smm/em64t101_save_state.c +smm-$(CONFIG_X86_AMD64_SAVE_STATE) += ../../amd/smm/amd64_save_state.c ifeq ($(CONFIG_SMM_TSEG),y) diff --git a/src/cpu/x86/smm/legacy_save_state.c b/src/cpu/x86/smm/legacy_save_state.c new file mode 100644 index 0000000..59fa99f --- /dev/null +++ b/src/cpu/x86/smm/legacy_save_state.c @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <cpu/x86/save_state.h> +#include <cpu/x86/legacy_save_state.h> + +static void *legacy_get_reg_base(const enum cpu_reg reg, const int node) +{ + const legacy_smm_state_save_area_t *save_state = + (const legacy_smm_state_save_area_t *)smm_get_save_state(node); + + switch (reg) { + case RAX: + return (void *)&save_state->eax; + case RBX: + return (void *)&save_state->ebx; + case RCX: + return (void *)&save_state->ecx; + case RDX: + return (void *)&save_state->edx; + } + + return NULL; +} + +enum get_set { + GET, + SET +}; + +static int legacy_get_set(const enum get_set op_type, const enum cpu_reg reg, + const int node, void *in_out, const uint8_t length) +{ + + void *reg_base = legacy_get_reg_base(reg, node); + + if (!reg_base) + return -1; + + switch (length) { + case 1: + case 2: + case 4: + switch (op_type) { + case GET: + memcpy(in_out, reg_base, length); + return 0; + case SET: + memcpy(reg_base, in_out, length); + } + } + + return -1; +} + +static int legacy_get_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length) +{ + return legacy_get_set(GET, reg, node, out, length); +} + +static int legacy_set_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length) +{ + return legacy_get_set(SET, reg, node, in, length); +} + +static int legacy_apmc_node(u8 cmd) +{ + legacy_smm_state_save_area_t *state; + int node; + + for (node = 0; node < CONFIG_MAX_CPUS; node++) { + state = smm_get_save_state(node); + + /* Check for Synchronous IO (bit0 == 1) */ + if (!(state->io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (state->io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + + /* Check AX against the requested command */ + if ((state->rax & 0xff) != cmd) + continue; + + return node; + } + + return -1; +} + +static const uint32_t revisions[] = { + 0x00030002, + 0x00030007, + SMM_REV_INVALID, +}; + +static const struct smm_save_state_ops ops = { + .revision_table = revisions, + .get_reg = legacy_get_reg, + .set_reg = legacy_set_reg, + .apmc_node = legacy_apmc_node, +}; + +const struct smm_save_state_ops *legacy_ops = &ops; -- To view, visit https://review.coreboot.org/c/coreboot/+/45472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67ab44fbdca5fac5837d32ffda5caad61e534473 Gerrit-Change-Number: 45472 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: src/mainboard: Port for Chuwi Minibook (m3/8GB)
by Sergey Larin (Code Review) June 8, 2024

June 8, 2024

Sergey Larin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38250 ) Change subject: src/mainboard: Port for Chuwi Minibook (m3/8GB) ...................................................................... src/mainboard: Port for Chuwi Minibook (m3/8GB) Hardware: - Intel Core m3-8100Y (Amber Lake aka Kabylake) - Sunrise Point-LP C iHDCP 2.2 Premium - ITE IT8987E EC - Unknown soldered 8GB memory - SPD was extracted from BIOS image (BIOS says it's Micron/2 ranks/13-15-15-34) - 1200x1920 eDP display (yep it's rotated) - mini-HDMI port - 1 USB 3.0, 1 USB 2.0, 1 USB Type-C port (as charger but working) - eMMC storage (unknown) - SD card slot - M.2 2242 slot - Intel WiFi chip Currently hangs after postcar stage. Signed-off-by: cerg2010cerg2010 <cerg2010cerg2010(a)mail.ru> Change-Id: Ifd3ec441659c0543bbd0d59101ac53fb561a7369 --- M src/drivers/spi/flashconsole.c A src/mainboard/chuwi/Kconfig A src/mainboard/chuwi/Kconfig.name A src/mainboard/chuwi/minibook/Kconfig A src/mainboard/chuwi/minibook/Kconfig.name A src/mainboard/chuwi/minibook/Makefile.inc A src/mainboard/chuwi/minibook/acpi/ec.asl A src/mainboard/chuwi/minibook/acpi/mainboard.asl A src/mainboard/chuwi/minibook/acpi/superio.asl A src/mainboard/chuwi/minibook/acpi_tables.c A src/mainboard/chuwi/minibook/board_info.txt A src/mainboard/chuwi/minibook/data.vbt A src/mainboard/chuwi/minibook/devicetree.cb A src/mainboard/chuwi/minibook/dsdt.asl A src/mainboard/chuwi/minibook/gma-mainboard.ads A src/mainboard/chuwi/minibook/gpio.h A src/mainboard/chuwi/minibook/hda_verb.c A src/mainboard/chuwi/minibook/mainboard.c A src/mainboard/chuwi/minibook/ramstage.c A src/mainboard/chuwi/minibook/romstage.c A src/mainboard/chuwi/minibook/spd/Makefile.inc A src/mainboard/chuwi/minibook/spd/micron.spd.hex A src/mainboard/chuwi/minibook/spd/spd.h A src/mainboard/chuwi/minibook/spd/spd_util.c A src/superio/ite/it8987e/Kconfig A src/superio/ite/it8987e/Makefile.inc A src/superio/ite/it8987e/it8987e.h A src/superio/ite/it8987e/superio.c 28 files changed, 1,366 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/38250/1 diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c index 80c63e0..149a84e 100644 --- a/src/drivers/spi/flashconsole.c +++ b/src/drivers/spi/flashconsole.c @@ -22,11 +22,11 @@ #define LINE_BUFFER_SIZE 128 #define READ_BUFFER_SIZE 0x100 -static const struct region_device *rdev_ptr; -static struct region_device rdev; -static uint8_t line_buffer[LINE_BUFFER_SIZE]; -static size_t offset; -static size_t line_offset; +static const struct region_device *g_rdev_ptr; +static struct region_device g_rdev; +static uint8_t g_line_buffer[LINE_BUFFER_SIZE]; +static size_t g_offset; +static size_t g_line_offset; void flashconsole_init(void) { @@ -36,11 +36,11 @@ size_t len = READ_BUFFER_SIZE; size_t i; - if (fmap_locate_area_as_rdev_rw("CONSOLE", &rdev)) { + if (fmap_locate_area_as_rdev_rw("CONSOLE", &g_rdev)) { printk(BIOS_INFO, "Can't find 'CONSOLE' area in FMAP\n"); return; } - size = region_device_sz(&rdev); + size = region_device_sz(&g_rdev); /* * We need to check the region until we find a 0xff indicating @@ -56,7 +56,7 @@ // Fill the buffer on first iteration if (i == 0) { len = MIN(READ_BUFFER_SIZE, size - offset); - if (rdev_readat(&rdev, buffer, offset, len) != len) + if (rdev_readat(&g_rdev, buffer, offset, len) != len) return; } if (buffer[i] == 0xff) { @@ -75,29 +75,29 @@ return; } - offset = offset; - rdev_ptr = &rdev; + g_offset = offset; + g_rdev_ptr = &g_rdev; } void flashconsole_tx_byte(unsigned char c) { - if (!rdev_ptr) + if (!g_rdev_ptr) return; - size_t region_size = region_device_sz(rdev_ptr); + size_t region_size = region_device_sz(g_rdev_ptr); - line_buffer[line_offset++] = c; + g_line_buffer[g_line_offset++] = c; - if (line_offset >= LINE_BUFFER_SIZE || - offset + line_offset >= region_size || c == '\n') { + if (g_line_offset >= LINE_BUFFER_SIZE || + g_offset + g_line_offset >= region_size || c == '\n') { flashconsole_tx_flush(); } } void flashconsole_tx_flush(void) { - size_t offset = offset; - size_t len = line_offset; + size_t offset = g_offset; + size_t len = g_line_offset; size_t region_size; static int busy; @@ -107,23 +107,23 @@ if (busy) return; - if (!rdev_ptr) + if (!g_rdev_ptr) return; busy = 1; - region_size = region_device_sz(rdev_ptr); + region_size = region_device_sz(g_rdev_ptr); if (offset + len >= region_size) len = region_size - offset; - if (rdev_writeat(&rdev, line_buffer, offset, len) != len) + if (rdev_writeat(&g_rdev, g_line_buffer, offset, len) != len) return; // If the region is full, stop future write attempts if (offset + len >= region_size) return; - offset = offset + len; - line_offset = 0; + g_offset = offset + len; + g_line_offset = 0; busy = 0; } diff --git a/src/mainboard/chuwi/Kconfig b/src/mainboard/chuwi/Kconfig new file mode 100644 index 0000000..234d863 --- /dev/null +++ b/src/mainboard/chuwi/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_CHUWI + +choice + prompt "Mainboard model" + +source "src/mainboard/chuwi/*/Kconfig.name" + +endchoice + +source "src/mainboard/chuwi/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "CHUWI Innovation And Technology(ShenZhen)co.,Ltd" + +endif # VENDOR_CHUWI diff --git a/src/mainboard/chuwi/Kconfig.name b/src/mainboard/chuwi/Kconfig.name new file mode 100644 index 0000000..2582c97 --- /dev/null +++ b/src/mainboard/chuwi/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_CHUWI + bool "CHUWI Innovation And Technology(ShenZhen)co.,Ltd" diff --git a/src/mainboard/chuwi/minibook/Kconfig b/src/mainboard/chuwi/minibook/Kconfig new file mode 100644 index 0000000..32881b8 --- /dev/null +++ b/src/mainboard/chuwi/minibook/Kconfig @@ -0,0 +1,73 @@ +if BOARD_CHUWI_MINIBOOK + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_CONVERTIBLE + select BOARD_ROMSIZE_KB_8192 + select SUPERIO_ITE_IT8987E + select SOC_INTEL_KABYLAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_EDP + select GENERIC_SPD_BIN + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select ADD_FSP_BINARIES + select FSP_USE_REPO + +config SPI_FLASH_INCLUDE_ALL_DRIVERS + bool + default n + +config SPI_FLASH + bool + default y + +config SPI_FLASH_WINBOND + bool + default y + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_ID + string + default "8086,591c" + +config IRQ_SLOT_COUNT + int + default 18 + +config MINIBOOK_EC_BIN_PATH + string + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ec.bin" + +config FSP_FD_PATH + string + #default "3rdparty/fsp/AmberLakeFspBinPkg/Fsp.fd" + default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" + +config FSP_HEADER_PATH + string + #default "3rdparty/fsp/AmberLakeFspBinPkg/Include/" + default "3rdparty/fsp/KabylakeFspBinPkg/Include/" + +config MAX_CPUS + int + default 4 + +config CBFS_SIZE + hex + default 0x600000 + +config MAINBOARD_DIR + string + default "chuwi/minibook" + +config MAINBOARD_PART_NUMBER + string + default "MiniBook" + +endif diff --git a/src/mainboard/chuwi/minibook/Kconfig.name b/src/mainboard/chuwi/minibook/Kconfig.name new file mode 100644 index 0000000..a8cb30a --- /dev/null +++ b/src/mainboard/chuwi/minibook/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_CHUWI_MINIBOOK + bool "MiniBook" diff --git a/src/mainboard/chuwi/minibook/Makefile.inc b/src/mainboard/chuwi/minibook/Makefile.inc new file mode 100644 index 0000000..7c7ca2a --- /dev/null +++ b/src/mainboard/chuwi/minibook/Makefile.inc @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +#ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +cbfs-files-y += ec.bin +ec.bin-file := $(call strip_quotes,$(CONFIG_MINIBOOK_EC_BIN_PATH)) +ec.bin-type := raw +ec.bin-position := 0xffa40000 diff --git a/src/mainboard/chuwi/minibook/acpi/ec.asl b/src/mainboard/chuwi/minibook/acpi/ec.asl new file mode 100644 index 0000000..ecc384e --- /dev/null +++ b/src/mainboard/chuwi/minibook/acpi/ec.asl @@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Johanna Schander <coreboot(a)mimoja.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (EC) +{ + Name (_HID, EisaId ("PNP0C09")) + Name (_UID, 0) + + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + Name (ACEX, 0) + + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xFF) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + XXX0, 8, + XXX1, 8, + XXX2, 8, + Offset (0x11), + KBCD, 8, + Offset (0x20), + RCMD, 8, + RCST, 8, + TESR, 8, + Offset (0x60), + TSR1, 8, + TSR2, 8, + TSR3, 8, + TSI, 4, + HYST, 4, + TSHT, 8, + TSLT, 8, + TSSR, 8, + CHGR, 16, + Offset (0x72), + CHGT, 8, + Offset (0x7F), + LSTE, 1, + Offset (0x80), + ECWR, 8, + XX10, 8, + XX11, 16, + B1DC, 16, + B1FV, 16, + B1FC, 16, + XX15, 16, + B1ST, 8, + B1CR, 16, + B1RC, 16, + B1VT, 16, + BPCN, 8, + Offset (0xC0), + VER1, 8, + VER2, 8, + RSV1, 8, + RSV2, 8, + CCI0, 8, + CCI1, 8, + CCI2, 8, + CCI3, 8, + CTL0, 8, + CTL1, 8, + CTL2, 8, + CTL3, 8, + CTL4, 8, + CTL5, 8, + CTL6, 8, + CTL7, 8, + MGI0, 8, + MGI1, 8, + MGI2, 8, + MGI3, 8, + MGI4, 8, + MGI5, 8, + MGI6, 8, + MGI7, 8, + MGI8, 8, + MGI9, 8, + MGIA, 8, + MGIB, 8, + MGIC, 8, + MGID, 8, + MGIE, 8, + MGIF, 8, + MGO0, 8, + MGO1, 8, + MGO2, 8, + MGO3, 8, + MGO4, 8, + MGO5, 8, + MGO6, 8, + MGO7, 8, + MGO8, 8, + MGO9, 8, + MGOA, 8, + MGOB, 8, + MGOC, 8, + MGOD, 8, + MGOE, 8, + MGOF, 8, + , 3, + TPCC, 1, + , 2, + DRMD, 1, + Offset (0xF1) + } + + Method (_REG, 2, NotSerialized) + { + } + + // KEY_RFKILL??? + Method (_Q01, 0, NotSerialized) + { + } + + // AC plugged? + Method (_Q0A, 0, NotSerialized) + { + } + + // AC unplugged? + Method (_Q0B, 0, NotSerialized) + { + } + + // Lid open/closed + Method (_Q0C, 0, NotSerialized) + { + } + + // Lid open/closed + Method (_Q0D, 0, NotSerialized) + { + } + + // Brigtness up + Method (_Q06, 0, NotSerialized) + { + } + + // Brigtness down + Method (_Q07, 0, NotSerialized) + { + } + + // Power down event + Method (_Q54, 0, NotSerialized) + { + } + + // ??? USB Type C/UCSI Something? + Method (_Q79, 0, NotSerialized) + { + } + + // ??? DCI (OTG?) + Method (_QDD, 0, NotSerialized) + { + } +} diff --git a/src/mainboard/chuwi/minibook/acpi/mainboard.asl b/src/mainboard/chuwi/minibook/acpi/mainboard.asl new file mode 100644 index 0000000..20d993a --- /dev/null +++ b/src/mainboard/chuwi/minibook/acpi/mainboard.asl @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + + Method (_LID) + { + if (LEqual(\_SB.PCI0.LPCB.EC.LSTE,0)) + { + Return (One) + } + else + { + Return (Zero) + } + } + + Method (_STA) + { + Return (_LID) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + + Method (_STA) + { + Return (0xF) + } + + Name (_PRW, Package () { 27, 4 }) + } + +} diff --git a/src/mainboard/chuwi/minibook/acpi/superio.asl b/src/mainboard/chuwi/minibook/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/chuwi/minibook/acpi/superio.asl diff --git a/src/mainboard/chuwi/minibook/acpi_tables.c b/src/mainboard/chuwi/minibook/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/chuwi/minibook/acpi_tables.c diff --git a/src/mainboard/chuwi/minibook/board_info.txt b/src/mainboard/chuwi/minibook/board_info.txt new file mode 100644 index 0000000..ebb9053 --- /dev/null +++ b/src/mainboard/chuwi/minibook/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Chuwi +Board name: Minibook +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/chuwi/minibook/data.vbt b/src/mainboard/chuwi/minibook/data.vbt new file mode 100644 index 0000000..16eac95 --- /dev/null +++ b/src/mainboard/chuwi/minibook/data.vbt Binary files differ diff --git a/src/mainboard/chuwi/minibook/devicetree.cb b/src/mainboard/chuwi/minibook/devicetree.cb new file mode 100644 index 0000000..20ec6d9 --- /dev/null +++ b/src/mainboard/chuwi/minibook/devicetree.cb @@ -0,0 +1,264 @@ +chip soc/intel/skylake + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x00000069" + register "gen4_dec" = "0x0000006d" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "2" # IDK why 2 really + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_iGFX" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "SaGv_Enabled" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 4A | 28A | 24A | 24A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ \ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = VR_CFG_AMP(4), \ + .voltage_limit = 1520, \ + .ac_loadline = 1800, \ + .dc_loadline = 1800, \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ \ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = VR_CFG_AMP(28), \ + .voltage_limit = 1520, \ + .ac_loadline = 400, \ + .dc_loadline = 400, \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ \ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = VR_CFG_AMP(24), \ + .voltage_limit = 1520, \ + .ac_loadline = 570, \ + .dc_loadline = 570, \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ \ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = VR_CFG_AMP(24), \ + .voltage_limit = 1520, \ + .ac_loadline = 570, \ + .dc_loadline = 570, \ + }" + + # Enable Root Port 6 (WiFi) + register "PcieRpEnable[5]" = "1" + + register "PcieRpLtrEnable[5]" = "1" + + # USB + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) + register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Wireless + register "usb2_ports[8]" = "USB2_PORT_FLEX(OC_SKIP)" # Touchpad + + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (left) + + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" + register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" + register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" + + # PL1 override 8W + register "tdp_pl1_override" = "8" + + # PL2 override 18W + register "tdp_pl2_override" = "18" + + # Send an extra VR mailbox command + register "SendVrMbxCmd" = "1" + + # Lock Down + register "common_soc_config" = "{ \ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, \ + }" + + # I2C4 is marked as "IoExpander" in BIOS + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoPci, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoAcpiHidden, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoPci, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + register "sdcard_cd_gpio_default" = "GPP_B17" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # Thermal Subsystem + device pci 07.0 on end # ??? + device pci 08.0 on end # Gaussian Mixture Model + device pci 14.0 on end # USB xHCI + device pci 14.2 on end # Thermal Subsystem + # TODO fill I2C + device pci 15.0 on end # I2C Controller #0 + device pci 15.1 on end # I2C Controller #0 + device pci 15.2 on end # I2C Controller #0 + device pci 16.0 on end # Management Engine Interface 1 + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 1 + device pci 1e.0 on end # Serial IO UART0 + device pci 1e.3 on end # SPI Controller #0 + device pci 1e.4 on end # SD Host Controller + device pci 1e.6 on end # SD Host Controller + device pci 1f.0 on # LPC + chip superio/ite/it8987e + device pnp 4e.4 off end # System Wake Up Control + device pnp 4e.5 on # KBC/Mouse Interface + irq 0x70 = 12 + end + device pnp 4e.6 on # KBC/Keyboard Interface + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.a off end # Consumer IR + device pnp 4e.f on # Shared Memory/Flash Interface + io 0x60 = 0x200 + irq 0x70 = 0 + irq 0x71 = 2 + irq 0xf4 = 9 + end + device pnp 4e.10 on # Real Time Clock + io 0x60 = 0x912 + io 0x62 = 0x910 + irq 0x70 = 8 + end + device pnp 4e.11 on # Power Management I/F Channel 1 (PMC1) + io 0x60 = 0x62 + io 0x62 = 0x66 + irq 0x70 = 0 + end + device pnp 4e.12 on # Power Management I/F Channel 2 (PMC2) + io 0x60 = 0x68 + io 0x62 = 0x6c + irq 0x70 = 0 + irq 0xf0 = 0 + end + device pnp 4e.13 off end # Serial Peripheral Interface (SSPI) + device pnp 4e.14 off end # Platform Environment Control Interface (PECI) + device pnp 4e.17 off end # Power Management I/F Channel 3 (PMC3) + device pnp 4e.18 off end # Power Management I/F Channel 3 (PMC4) + device pnp 4e.19 off end # Power Management I/F Channel 3 (PMC5) + end + end # LPC Bridge + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + end +end diff --git a/src/mainboard/chuwi/minibook/dsdt.asl b/src/mainboard/chuwi/minibook/dsdt.asl new file mode 100644 index 0000000..ef48745 --- /dev/null +++ b/src/mainboard/chuwi/minibook/dsdt.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +){ + //Platform + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/chuwi/minibook/gma-mainboard.ads b/src/mainboard/chuwi/minibook/gma-mainboard.ads new file mode 100644 index 0000000..452cf26 --- /dev/null +++ b/src/mainboard/chuwi/minibook/gma-mainboard.ads @@ -0,0 +1,33 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +-- Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Internal, + DP1, + HDMI1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/chuwi/minibook/gpio.h b/src/mainboard/chuwi/minibook/gpio.h new file mode 100644 index 0000000..e8460a7 --- /dev/null +++ b/src/mainboard/chuwi/minibook/gpio.h @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + /* GPIO */ _PAD_CFG_STRUCT(GPP_A0, 0x4000100, 0x1000), + /* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), + /* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), + /* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), + /* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), + /* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), + /* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A7, 0x44000100, 0x1000), + /* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), + /* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), + /* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x44000100, 0x1000), + /* SUSWARN#/SUSPWRDNACK */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), + /* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), + /* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3000), + /* SD_1P8_SEL */ _PAD_CFG_STRUCT(GPP_A16, 0x44000500, 0x0), + /* SD_PWR_EN# */ _PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x40800102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A19, 0x40000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x42000100, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B0, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B1, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B2, 0x44000201, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B5, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B6, 0x44000102, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B7, 0x44000102, 0x3000), + /* SRCCLKREQ3# */ _PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x3000), + /* SRCCLKREQ4# */ _PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0), + /* SRCCLKREQ5# */ _PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0), + /* EXT_PWR_GATE# */ _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), + /* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), + /* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B14, 0x44000100, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000201, 0x800), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x42000100, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x46000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x44000100, 0x1000), + /* GSPI1_CS# */ _PAD_CFG_STRUCT(GPP_B19, 0x44000700, 0x0), + /* GSPI1_CLK */ _PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), + /* GSPI1_MISO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), + /* GSPI1_MOSI */ _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B23, 0x44000100, 0x1000), + /* SMBCLK */ _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x2800), + /* SMBDATA */ _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x2800), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C3, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C4, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C6, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C7, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x44000102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x86080102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x4000201, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C11, 0x44000102, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C12, 0x44000200, 0x2400), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C13, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C14, 0x44000201, 0x800), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C15, 0x82180102, 0x0), + /* I2C0_SDA */ _PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), + /* I2C0_SCL */ _PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), + /* I2C1_SDA */ _PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), + /* I2C1_SCL */ _PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), + /* UART2_RXD */ _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), + /* UART2_TXD */ _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C22, 0x44000200, 0x2400), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C23, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D0, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D1, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D2, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D3, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D4, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D5, 0x44000102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D6, 0x44000102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D7, 0x44000102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D8, 0x44000102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x40000102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x40000102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D13, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D14, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D15, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D16, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D17, 0x44000200, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D18, 0x44000201, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x44000201, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x4000201, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E0, 0x44000100, 0x1000), + /* SATAXPCIE1 */ _PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E2, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E4, 0x44000100, 0x1000), + /* SATA_DEVSLP1 */ _PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x80180102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E8, 0x44000201, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E10, 0x44000200, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E11, 0x44000201, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E12, 0x44000200, 0x3000), + /* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), + /* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), + /* DDPD_HPD2 */ _PAD_CFG_STRUCT(GPP_E15, 0x44000702, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x3000), + /* EDP_HPD */ _PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), + /* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), + /* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E20, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E21, 0x44000102, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E22, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), + /* BATLOW# */ _PAD_CFG_STRUCT(GPD0, 0x4000702, 0x0), + /* ACPRESENT */ _PAD_CFG_STRUCT(GPD1, 0x4000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPD2, 0x4000100, 0x1000), + /* PWRBTN# */ _PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), + /* SLP_S3# */ _PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), + /* SLP_S4# */ _PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), + /* SLP_A# */ _PAD_CFG_STRUCT(GPD6, 0x4000600, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPD7, 0x4000201, 0x0), + /* SUSCLK */ _PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPD9, 0x4000200, 0x0), + /* SLP_S5# */ _PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPD11, 0x4000200, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F0, 0x44000200, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F1, 0x44000200, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F2, 0x44000200, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F3, 0x44000200, 0x1000), + /* I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2000000), + /* I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F6, 0x44000201, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F7, 0x80180102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F8, 0x40080100, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F9, 0x44000201, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F10, 0x44000200, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F11, 0x44000201, 0x0), + /* EMMC_CMD */ _PAD_CFG_STRUCT(GPP_F12, 0x44000702, 0x0), + /* EMMC_DATA0 */ _PAD_CFG_STRUCT(GPP_F13, 0x44000702, 0x0), + /* EMMC_DATA1 */ _PAD_CFG_STRUCT(GPP_F14, 0x44000702, 0x0), + /* EMMC_DATA2 */ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x0), + /* EMMC_DATA3 */ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x0), + /* EMMC_DATA4 */ _PAD_CFG_STRUCT(GPP_F17, 0x44000702, 0x0), + /* EMMC_DATA5 */ _PAD_CFG_STRUCT(GPP_F18, 0x44000702, 0x0), + /* EMMC_DATA6 */ _PAD_CFG_STRUCT(GPP_F19, 0x44000702, 0x0), + /* EMMC_DATA7 */ _PAD_CFG_STRUCT(GPP_F20, 0x44000702, 0x0), + /* EMMC_RCLK */ _PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), + /* EMMC_CLK */ _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x44000200, 0x1000), + /* SD_CMD */ _PAD_CFG_STRUCT(GPP_G0, 0x44000702, 0x0), + /* SD_DATA0 */ _PAD_CFG_STRUCT(GPP_G1, 0x44000702, 0x0), + /* SD_DATA1 */ _PAD_CFG_STRUCT(GPP_G2, 0x44000702, 0x0), + /* SD_DATA2 */ _PAD_CFG_STRUCT(GPP_G3, 0x44000702, 0x0), + /* SD_DATA3 */ _PAD_CFG_STRUCT(GPP_G4, 0x44000702, 0x0), + /* SD_CD# */ _PAD_CFG_STRUCT(GPP_G5, 0x44000700, 0x3000), + /* SD_CLK */ _PAD_CFG_STRUCT(GPP_G6, 0x44000702, 0x0), + /* SD_WP */ _PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x0), +}; + +#endif + +#endif diff --git a/src/mainboard/chuwi/minibook/hda_verb.c b/src/mainboard/chuwi/minibook/hda_verb.c new file mode 100644 index 0000000..c654e70 --- /dev/null +++ b/src/mainboard/chuwi/minibook/hda_verb.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC269VC */ + 0x10ec0269, /* Vendor ID */ + 0x10ec0000, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x10ec0000), + AZALIA_PIN_CFG(0, 0x12, 0xb7a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170120), + AZALIA_PIN_CFG(0, 0x15, 0x04211010), + AZALIA_PIN_CFG(0, 0x17, 0x40000000), + AZALIA_PIN_CFG(0, 0x18, 0x04a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40e4a205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/chuwi/minibook/mainboard.c b/src/mainboard/chuwi/minibook/mainboard.c new file mode 100644 index 0000000..e88b42a --- /dev/null +++ b/src/mainboard/chuwi/minibook/mainboard.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <smbios.h> +#include <string.h> +#include <cbfs.h> + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t ser_len; + + cbfs_file_data(&cbfs_region, &file); + + ser_len = region_device_sz(&cbfs_region); + if (ser_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, + 0, ser_len) == ser_len) { + serial_number[ser_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, + MAX_SERIAL_LENGTH); + + return serial_number; +} diff --git a/src/mainboard/chuwi/minibook/ramstage.c b/src/mainboard/chuwi/minibook/ramstage.c new file mode 100644 index 0000000..94f8071 --- /dev/null +++ b/src/mainboard/chuwi/minibook/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/chuwi/minibook/romstage.c b/src/mainboard/chuwi/minibook/romstage.c new file mode 100644 index 0000000..f1fe3ae --- /dev/null +++ b/src/mainboard/chuwi/minibook/romstage.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <console/console.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include "spd/spd.h" +#include <ec/acpi/ec.h> +#include <stdint.h> +#include <stddef.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + printk(BIOS_INFO, "SPD index %d\n", 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + struct region_device spd_rdev; + + mem_cfg->DqPinsInterleaved = 0; + if (get_spd_cbfs_rdev(&spd_rdev, 0) < 0) + die("spd.bin not found\n"); + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ + // TODO evaluate google/eve way of loading + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + //mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + print_spd_info((uint8_t *)mem_cfg->MemorySpdPtr00); + + mupd->FspmTestConfig.DmiVc1 = 1; +} diff --git a/src/mainboard/chuwi/minibook/spd/Makefile.inc b/src/mainboard/chuwi/minibook/spd/Makefile.inc new file mode 100644 index 0000000..3f2fde0 --- /dev/null +++ b/src/mainboard/chuwi/minibook/spd/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Johanna Schander <coreboot(a)mimoja.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd_util.c + +SPD_BIN = $(obj)/spd.bin + +# It's probably the same SPD used for 16GB version +SPD_SOURCES += micron # 0b0000 8GB diff --git a/src/mainboard/chuwi/minibook/spd/micron.spd.hex b/src/mainboard/chuwi/minibook/spd/micron.spd.hex new file mode 100644 index 0000000..0f1c25f --- /dev/null +++ b/src/mainboard/chuwi/minibook/spd/micron.spd.hex @@ -0,0 +1,32 @@ +91 20 f1 03 05 1a 05 0a 03 11 01 08 0a 00 00 01 +78 78 90 50 90 11 50 e0 90 06 3c 3c 01 90 00 00 +00 b1 00 00 00 00 00 a8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2c 00 00 00 00 00 00 00 da b0 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/chuwi/minibook/spd/spd.h b/src/mainboard/chuwi/minibook/spd/spd.h new file mode 100644 index 0000000..36363cc --- /dev/null +++ b/src/mainboard/chuwi/minibook/spd/spd.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2019 Johanna Schander <coreboot(a)mimoja.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#include <gpio.h> +#include "../gpio.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/chuwi/minibook/spd/spd_util.c b/src/mainboard/chuwi/minibook/spd/spd_util.c new file mode 100644 index 0000000..a8adf61 --- /dev/null +++ b/src/mainboard/chuwi/minibook/spd/spd_util.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> + +#include "spd.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } + }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + {6, 4, 7, 5, 1, 3, 2, 0}, + {3, 1, 6, 4, 2, 0, 5, 7} + }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + /* Cannot find these in original BIOS, so use defaults */ + /* They are valid, probably */ + const u16 RcompResistor[3] = {200, 81, 162}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + /* Cannot find these in original BIOS, so use defaults */ + /* They are valid, probably */ + static const u16 RcompTarget[5] = {100, 40, 40, 23, 40}; + + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} diff --git a/src/superio/ite/it8987e/Kconfig b/src/superio/ite/it8987e/Kconfig new file mode 100644 index 0000000..b8e3258 --- /dev/null +++ b/src/superio/ite/it8987e/Kconfig @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8987E + bool + select SUPERIO_ITE_COMMON_PRE_RAM diff --git a/src/superio/ite/it8987e/Makefile.inc b/src/superio/ite/it8987e/Makefile.inc new file mode 100644 index 0000000..01e4d3e --- /dev/null +++ b/src/superio/ite/it8987e/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8987E) += superio.c diff --git a/src/superio/ite/it8987e/it8987e.h b/src/superio/ite/it8987e/it8987e.h new file mode 100644 index 0000000..4e265df --- /dev/null +++ b/src/superio/ite/it8987e/it8987e.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8987E_H +#define SUPERIO_ITE_IT8987E_H + +#define IT8987E_SWUC 0x04 /* System Wake-Up */ +#define IT8987E_KBCM 0x05 /* PS/2 mouse */ +#define IT8987E_KBCK 0x06 /* PS/2 keyboard */ +#define IT8987E_IR 0x0a /* Consumer IR */ +#define IT8987E_SMFI 0x0f /* Shared Memory/Flash Interface */ +#define IT8987E_RTCT 0x10 /* RTC-like Timer */ +#define IT8987E_PMC1 0x11 /* Power Management Channel 1 */ +#define IT8987E_PMC2 0x12 /* Power Management Channel 2 */ +#define IT8987E_SSPI 0x13 /* Serial Peripheral Interface */ +#define IT8987E_PECI 0x14 /* Platform EC Interface */ +#define IT8987E_PMC3 0x17 /* Power Management Channel 3 */ +#define IT8987E_PMC4 0x18 /* Power Management Channel 4 */ +#define IT8987E_PMC5 0x19 /* Power Management Channel 5 */ + + +#endif /* SUPERIO_ITE_IT8987E_H */ diff --git a/src/superio/ite/it8987e/superio.c b/src/superio/ite/it8987e/superio.c new file mode 100644 index 0000000..dce7a6f --- /dev/null +++ b/src/superio/ite/it8987e/superio.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> + +#include "it8987e.h" + +static void it8987e_init(struct device *dev) +{ +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8987e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, IT8987E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, IT8987E_KBCM, PNP_IRQ0, }, + { NULL, IT8987E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, + { NULL, IT8987E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, IT8987E_SMFI, PNP_IO0 | PNP_IRQ0 | PNP_MSC4, 0xfff0, }, + { NULL, IT8987E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0 + | PNP_MSC0 | PNP_MSC1 | PNP_MSC2, + 0xfffe, 0xfffe, 0xfffe, 0xfffe}, + { NULL, IT8987E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0 | PNP_MSC0, + 0x07fc, 0x07fc, 0xfff0 }, + { NULL, IT8987E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 }, + { NULL, IT8987E_PECI, PNP_IO0, 0xfff8 }, + { NULL, IT8987E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x07ff, 0x07ff }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8987e_ops = { + CHIP_NAME("ITE IT8987E Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/38250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd3ec441659c0543bbd0d59101ac53fb561a7369 Gerrit-Change-Number: 38250 Gerrit-PatchSet: 1 Gerrit-Owner: Sergey Larin <cerg2010cerg2010(a)mail.ru> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mainboard/lenovo: Add Thinkpad Edge S220 (a.k.a E220s)
by Bill XIE (Code Review) June 8, 2024

June 8, 2024

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48771 ) Change subject: mainboard/lenovo: Add Thinkpad Edge S220 (a.k.a E220s) ...................................................................... mainboard/lenovo: Add Thinkpad Edge S220 (a.k.a E220s) The code is based on autoport and that for s230u Tested: - CPU i3-2357M - Slotted DIMM 2GiB - Camera - pci-e and usb2 on Mini PCI-E slot for wlan - sata and usb2 on Mini PCI-E slot for wwan - On board SDHCI connected to pci-e - libgfxinit-based graphic init - Sound - S3 - EHCI debug - Seabios Payload Change-Id: I746798b13e83d1971bb7be93751a15875d16c337 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/s220.md A Documentation/mainboard/lenovo/s220_ready_to_flash.jpg M src/mainboard/hp/snb_ivb_laptops/cmos.default A src/mainboard/lenovo/s220/Kconfig A src/mainboard/lenovo/s220/Kconfig.name A src/mainboard/lenovo/s220/Makefile.inc A src/mainboard/lenovo/s220/acpi/ec.asl A src/mainboard/lenovo/s220/acpi/gpe.asl A src/mainboard/lenovo/s220/acpi/platform.asl A src/mainboard/lenovo/s220/acpi/superio.asl A src/mainboard/lenovo/s220/acpi_tables.c A src/mainboard/lenovo/s220/board_info.txt A src/mainboard/lenovo/s220/data.vbt A src/mainboard/lenovo/s220/devicetree.cb A src/mainboard/lenovo/s220/dsdt.asl A src/mainboard/lenovo/s220/early_init.c A src/mainboard/lenovo/s220/ec.c A src/mainboard/lenovo/s220/ec.h A src/mainboard/lenovo/s220/gma-mainboard.ads A src/mainboard/lenovo/s220/gpio.c A src/mainboard/lenovo/s220/hda_verb.c A src/mainboard/lenovo/s220/mainboard.c A src/mainboard/lenovo/s220/smihandler.c 24 files changed, 1,269 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/48771/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 95efe55..c0976e0 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -103,6 +103,7 @@ - [T420](lenovo/t420.md) - [T420 / T520 / X220 / T420s / W520 common](lenovo/Sandy_Bridge_series.md) - [X1](lenovo/x1.md) +- [S220](lenovo/s220.md) ### Ivy Bridge series diff --git a/Documentation/mainboard/lenovo/s220.md b/Documentation/mainboard/lenovo/s220.md new file mode 100644 index 0000000..2bbc22d --- /dev/null +++ b/Documentation/mainboard/lenovo/s220.md @@ -0,0 +1,36 @@ +# Lenovo Edge S220 (a.k.a E220s) + +## Disassembly Instructions + +You must remove the following parts to access the SPI flash: + +![S220 ready to flash](s220_ready_to_flash.jpg) + +* Keyboard +* Hard Drive Cover +* Palmrest + +Its [Hardware Maintenance Manual](https://thinkpads.com/support/hmm/hmm_pdf/e220s_s220_hmm_en_0a60672… can be used as a guidance of disassembly. + +The vendor IFD VSCC list contains: +- MACRONIX_MX25L6405 (0xc2, 0x2017) +- WINBOND_NEX_W25X64 (0xef, 0x3017) +- ATMEL_AT25DF641 (0x1f, 0x4800) + +The general [flashing tutorial] has more details. + +Tested: +- CPU i3-2357M +- Slotted DIMM 2GiB +- Camera +- pci-e and usb2 on Mini PCI-E slot for wlan +- sata and usb2 on Mini PCI-E slot for wwan +- On board SDHCI connected to pci-e +- libgfxinit-based graphic init +- Sound +- S3 +- EHCI debug +- Seabios Payload + +[flashing tutorial]: ../../flash_tutorial/ext_power.md + diff --git a/Documentation/mainboard/lenovo/s220_ready_to_flash.jpg b/Documentation/mainboard/lenovo/s220_ready_to_flash.jpg new file mode 100644 index 0000000..3fbafce --- /dev/null +++ b/Documentation/mainboard/lenovo/s220_ready_to_flash.jpg Binary files differ diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default index ba33ddf..ad822d5 100644 --- a/src/mainboard/hp/snb_ivb_laptops/cmos.default +++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default @@ -2,5 +2,4 @@ debug_level=Debug power_on_after_fail=Disable nmi=Enable -volume=0x3 sata_mode=AHCI diff --git a/src/mainboard/lenovo/s220/Kconfig b/src/mainboard/lenovo/s220/Kconfig new file mode 100644 index 0000000..e909399 --- /dev/null +++ b/src/mainboard/lenovo/s220/Kconfig @@ -0,0 +1,59 @@ +if BOARD_LENOVO_THINKPAD_EDGE_S220 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select SYSTEM_TYPE_LAPTOP + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select SOUTHBRIDGE_INTEL_C216 + select EC_COMPAL_ENE932 + select EC_ACPI + select NO_UART_ON_SUPERIO + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_PANEL_1_ON_LVDS + select SERIRQ_CONTINUOUS_MODE + select INTEL_GMA_HAVE_VBT + +config MAINBOARD_DIR + string + default lenovo/s220 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad Edge S220/E220s" + +config VGA_BIOS_FILE + string + default "pci8086,0116.rom" + +config VGA_BIOS_ID + string + default "8086,0116" + +config DRAM_RESET_GATE_GPIO + int + default 10 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config EC_BASE_ADDRESS + hex + default 0xff000000 + +config PS2K_EISAID + default "PTL0001" + +config PS2M_EISAID + default "LEN0031" + +endif diff --git a/src/mainboard/lenovo/s220/Kconfig.name b/src/mainboard/lenovo/s220/Kconfig.name new file mode 100644 index 0000000..78a5af3 --- /dev/null +++ b/src/mainboard/lenovo/s220/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKPAD_EDGE_S220 + bool "ThinkPad Edge S220/E220s" diff --git a/src/mainboard/lenovo/s220/Makefile.inc b/src/mainboard/lenovo/s220/Makefile.inc new file mode 100644 index 0000000..a0a3aa1 --- /dev/null +++ b/src/mainboard/lenovo/s220/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-y += ec.c +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/s220/acpi/ec.asl b/src/mainboard/lenovo/s220/acpi/ec.asl new file mode 100644 index 0000000..20a9096 --- /dev/null +++ b/src/mainboard/lenovo/s220/acpi/ec.asl @@ -0,0 +1,347 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (EC0) +{ + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 0) + + Name (_GPE, THINKPAD_EC_GPE) + Mutex (ECLK, 0x07) + + /* EmbeddedControl should work as well, but memory mapped is faster. */ + OperationRegion (ERAM, SystemMemory, (CONFIG_EC_BASE_ADDRESS + 0x100), 0x100) + Field (ERAM, ByteAcc, Lock, Preserve) + { + , 1, + , 1, + HKFA, 1, // FN lock (Hotkey / FN row toggle) + , 1, + , 1, + , 1, + , 1, + + Offset(0x0c), + HLCL, 8, // LED control + + Offset(0x46), + , 4, + ONAC, 1, + , 3, + + Offset(0x81), + PAGE, 8, + } + + /* Battery info page 0 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0xA0), + SBRC, 16, /* Remaining capacity */ + SBFC, 16, /* Full-charge capacity */ + SBAE, 16, + SBRS, 16, + SBAC, 16, /* Present rate */ + SBVO, 16, /* Present voltage */ + SBAF, 16, + SBBS, 16, + } + + /* Battery info page 1 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0xA0), + , 15, + SBCM, 1, /* Power unit (0 == mA/mAh, 1 == mW/mWh) */ + SBMD, 16, + SBCC, 16, + } + + /* Battery info page 2 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0xA0), + SBDC, 16, /* Design Capacity */ + SBDV, 16, /* Design Voltage */ + SBOM, 16, + SBSI, 16, + SBDT, 16, + SBSN, 16, /* Serial number */ + } + + /* Battery info page 4 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0xA0), + SBCH, 32, /* Type (LiON) */ + } + + /* Battery info page 5 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0xA0), + SBMN, 128, /* Manufacturer */ + } + + /* Battery info page 6 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0xA0), + SBDN, 128, /* Model */ + } + + Method (_CRS, 0, Serialized) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + IO (Decode16, 0x700, 0x700, 0, 8) + Memory32Fixed(ReadOnly, CONFIG_EC_BASE_ADDRESS, 0x1000, FF00) + }) + Return (ECMD) + } + + /* Increase brightness hotkey */ + Method (_Q14, 0, NotSerialized) { + BRIGHTNESS_UP() + ^HKEY.MHKQ (0x1010) + } + + /* Decrease brightness hotkey */ + Method (_Q15, 0, NotSerialized) { + BRIGHTNESS_DOWN() + ^HKEY.MHKQ (0x1011) + } + + /* Video output switch hotkey */ + Method (_Q16, 0, NotSerialized) { + Notify (\_SB.PCI0.GFX0, 0x82) + ^HKEY.MHKQ (0x1007) + } + + Method (_Q19, 0, NotSerialized) + { + ^HKEY.MHKQ (0x1018) + } + + /* Switched to AC power */ + Method (_Q26, 0, NotSerialized) + { + Store (One, PWRS) + Notify (^AC, 0x80) + Notify (^BAT0, 0x80) + \PNOT () + ^HKEY.MHKQ (0x6040) + } + + /* Switched to battery power */ + Method (_Q27, 0, NotSerialized) + { + Store (Zero, PWRS) + Notify (^AC, 0x80) + Notify (^BAT0, 0x80) + \PNOT () + ^HKEY.MHKQ (0x6040) + } + + /* Lid openend */ + Method (_Q2A, 0, NotSerialized) + { + Store (One, LIDS) + Notify(^LID, 0x80) + ^HKEY.MHKQ (0x5002) + } + + /* Lid closed */ + Method (_Q2B, 0, NotSerialized) + { + Store (Zero, LIDS) + Notify(^LID, 0x80) + ^HKEY.MHKQ (0x5001) + } + + /* Tablet swivel down */ + Method (_Q35, 0, NotSerialized) + { + ^HKEY.MHKQ (0x60c0) + ^HKEY.MHKQ (0x500a) + } + + /* Tablet swivel up */ + Method (_Q36, 0, NotSerialized) + { + ^HKEY.MHKQ (0x60c0) + ^HKEY.MHKQ (0x5009) + } + + /* Tablet rotate lock button */ + Method (_Q37, 0, NotSerialized) + { + ^HKEY.MHKQ (0x6020) + } + + /* Numlock pressed */ + Method (_Q3F, 0, NotSerialized) + { + ^HKEY.MHKQ (0x6000) + } + + /* RFKill status changed */ + Method (_Q41, 0, NotSerialized) { + ^HKEY.MHKQ (0x7000) + } + + /* Mute hotkey */ + Method (_Q43, 0, NotSerialized) { + ^HKEY.MHKQ (0x1017) + } + + /* Settings hotkey */ + Method (_Q5A, 0, NotSerialized) + { + ^HKEY.MHKQ (0x101D) + } + + /* Search hotkey */ + Method (_Q5B, 0, NotSerialized) + { + ^HKEY.MHKQ (0x101E) + } + + /* Scale hotkey */ + Method (_Q5C, 0, NotSerialized) + { + ^HKEY.MHKQ (0x101F) + } + + /* File hotkey */ + Method (_Q5D, 0, NotSerialized) + { + ^HKEY.MHKQ (0x1020) + } + + /* RFkill hotkey */ + Method (_Q64, 0, NotSerialized) { + ^HKEY.MHKQ (0x1005) + } + + /* Mic mute hotkey */ + Method (_Q6A, 0, NotSerialized) + { + ^HKEY.MHKQ (0x101B) + } + + /* FN key pressed */ + Method (_Q70, 0, NotSerialized) { } + + /* FN+Esc pressed / FN row mode switch */ + Method (_Q74, 0, NotSerialized) { + XOr(One, HKFA, HKFA) + ^HKEY.MHKQ (0x6060) + } + + /* Implements enough of the Lenovo hotkey device for + * thinkpad-acpi to work, no real support for hotkey masking */ + Device (HKEY) + { + Name (_HID, EisaId ("LEN0068")) + + Name (DHKC, Zero) + Name (DHKV, Zero) + Name (DHKN, 0xFC018070) // Hotkey mask + Mutex (XDHK, 0x07) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Method (MHKV, 0, NotSerialized) + { + Return (0x0100) // Interface version 1.0 + } + + Method (MHKA, 0, NotSerialized) // Hotkey all mask + { + Return (0xFFFFFFFF) + } + + Method (MHKM, 2, NotSerialized) // Set hotkey mask + { + Acquire (XDHK, 0xFFFF) + + ShiftLeft (One, Decrement (Arg0), Local0) + If (Arg1) { + Or (Local0, DHKN, DHKN) + } Else { + And (Not(Local0), DHKN, DHKN) + } + + Release (XDHK) + } + + Method (MHKC, 1, NotSerialized) // Hotkey disable? + { + Acquire (XDHK, 0xFFFF) + + Store (Arg0, DHKC) + + Release (XDHK) + } + + Method (MHKP, 0, NotSerialized) // Hotkey poll + { + Acquire (XDHK, 0xFFFF) + + Store (Zero, Local0) + + if (DHKV) { + Store (DHKV, Local0) + Store (Zero, DHKV) + } + + Release (XDHK) + + Return (Local0) + } + + Method (MHKQ, 1, NotSerialized) // Send hotkey event + { + Acquire (XDHK, 0xFFFF) + + Store (Arg0, DHKV) + + Release (XDHK) + + Notify (HKEY, 0x80) // Status Change + } + } + + /* LED support for thinkpad-acpi */ + Method (LED, 2, NotSerialized) + { + Or (Arg0, Arg1, HLCL) + } + + Device (AC) + { + Name (_HID, "ACPI0003") + Name (_PCL, Package (1) { \_SB }) + + Method (_PSR, 0, NotSerialized) + { + Return (ONAC) + } + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } + + /* Battery is H8 compatible, but requires an explicit delay */ + #define BATTERY_PAGE_DELAY_MS 20 + #include <ec/lenovo/h8/acpi/battery.asl> + + /* LID is H8 compatible */ + #include <ec/lenovo/h8/acpi/lid.asl> +} diff --git a/src/mainboard/lenovo/s220/acpi/gpe.asl b/src/mainboard/lenovo/s220/acpi/gpe.asl new file mode 100644 index 0000000..8124ec7 --- /dev/null +++ b/src/mainboard/lenovo/s220/acpi/gpe.asl @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (_GPE) +{ + Name (PDET, Zero) + Method (PNOT, 2, Serialized) { + ShiftLeft (Arg0, Arg1, Local0) + Not( ShiftLeft (One, Arg1), Local1) + Or (Local0, And (Local1, PDET), PDET) + If (LEqual (PDET, Zero)) { + // Palm removed + \_SB.PCI0.LPCB.EC0.HKEY.MHKQ (0x60B1) + } Else { + // Palm detected + \_SB.PCI0.LPCB.EC0.HKEY.MHKQ (0x60B0) + } + } + + Method (TINV, 2, Serialized) { + ShiftLeft (One, Arg1, Local0) + If (LEqual (Arg0, Zero)) { + Not (Local0, Local0) + And (GIV0, Local0, GIV0) + } Else { + Or (GIV0, Local0, GIV0) + } + } + + /* Palm detect sensor 1 */ + Method (_L12, 0, NotSerialized) { + // Invert trigger + TINV (GP02, 2) + + PNOT (GP02, 0) + } + + /* Palm detect sensor 2 */ + Method (_L14, 0, NotSerialized) { + // Invert trigger + TINV (GP04, 4) + + PNOT (GP04, 1) + } +} diff --git a/src/mainboard/lenovo/s220/acpi/platform.asl b/src/mainboard/lenovo/s220/acpi/platform.asl new file mode 100644 index 0000000..149fb3a --- /dev/null +++ b/src/mainboard/lenovo/s220/acpi/platform.asl @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + /* Turn on radios */ + Store (One, GP33) /* WLBT_OFF_5# (To pin 5 of WiFi mPCIe) */ + Store (One, GP36) /* WLBT_OFF_51# (To pin 51 of WiFi mPCIe) */ + /* There also is RF_OFF# on pin 20, controlled by the EC */ + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* Turn off radios */ + Store (Zero, GP33) /* WLBT_OFF_5# (To pin 5 of WiFi mPCIe) */ + Store (Zero, GP36) /* WLBT_OFF_51# (To pin 51 of WiFi mPCIe) */ + /* There also is RF_OFF# on pin 20, controlled by the EC */ +} + +Scope(\_SI) +{ + Method(_SST, 1, NotSerialized) + { + If (LLess(Arg0, 2)) + { + /* Thinkpad LED on */ + \_SB.PCI0.LPCB.EC0.LED (Zero, 0x80) + } + Else + { + /* Thinkpad LED blinking */ + \_SB.PCI0.LPCB.EC0.LED (Zero, 0xC0) + } + } +} diff --git a/src/mainboard/lenovo/s220/acpi/superio.asl b/src/mainboard/lenovo/s220/acpi/superio.asl new file mode 100644 index 0000000..ee2eabe --- /dev/null +++ b/src/mainboard/lenovo/s220/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/s220/acpi_tables.c b/src/mainboard/lenovo/s220/acpi_tables.c new file mode 100644 index 0000000..c85058d --- /dev/null +++ b/src/mainboard/lenovo/s220/acpi_tables.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* The lid is open by default. */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/s220/board_info.txt b/src/mainboard/lenovo/s220/board_info.txt new file mode 100644 index 0000000..cdbf8b8 --- /dev/null +++ b/src/mainboard/lenovo/s220/board_info.txt @@ -0,0 +1,4 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +FIXME: put ROM package, ROM socketed, Release year diff --git a/src/mainboard/lenovo/s220/data.vbt b/src/mainboard/lenovo/s220/data.vbt new file mode 100644 index 0000000..f7882f9 --- /dev/null +++ b/src/mainboard/lenovo/s220/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/s220/devicetree.cb b/src/mainboard/lenovo/s220/devicetree.cb new file mode 100644 index 0000000..22429c9 --- /dev/null +++ b/src/mainboard/lenovo/s220/devicetree.cb @@ -0,0 +1,84 @@ +chip northbridge/intel/sandybridge + register "gfx" = "GMA_STATIC_DISPLAYS(1)" + register "gpu_cpu_backlight" = "0x00000f55" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" + register "gpu_panel_power_backlight_off_delay" = "2700" + register "gpu_panel_power_backlight_on_delay" = "3800" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "95" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x13121312" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + subsystemid 0x17aa 0x21e4 inherit + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 off end # PEG + device pci 02.0 on end # iGPU + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x00000000" + register "gen2_dec" = "0x000c0701" + register "gen3_dec" = "0x000c0069" + register "gen4_dec" = "0x000c06a1" + register "gpi13_routing" = "2" + register "gpi7_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x19" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x21e4 + chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/s220/dsdt.asl b/src/mainboard/lenovo/s220/dsdt.asl new file mode 100644 index 0000000..6d67b91 --- /dev/null +++ b/src/mainboard/lenovo/s220/dsdt.asl @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define THINKPAD_EC_GPE 23 + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include "acpi/gpe.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/lenovo/s220/early_init.c b/src/mainboard/lenovo/s220/early_init.c new file mode 100644 index 0000000..e04b4df --- /dev/null +++ b/src/mainboard/lenovo/s220/early_init.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include "ec.h" + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 0, 1, 1 }, + { 0, 1, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 0, 0, 3 }, + { 0, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 0, 0, 5 }, + { 0, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + /* Memory map KB9012 EC registers */ + pci_write_config32(PCH_LPC_DEV, LGMR, + CONFIG_EC_BASE_ADDRESS | 1); + pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0); + + /* Enable external USB port power. */ + if (CONFIG(USBDEBUG)) + ec_mm_set_bit(0x3b, 4); +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x52, id_only); + read_spd(&spd[2], 0x51, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/lenovo/s220/ec.c b/src/mainboard/lenovo/s220/ec.c new file mode 100644 index 0000000..285a8d5 --- /dev/null +++ b/src/mainboard/lenovo/s220/ec.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "ec.h" +#include <ec/compal/ene932/ec.h> + +/* The keyboard matrix tells the EC how the keyboard is wired internally */ +static void set_keyboard_matrix_us(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE5); +} + +/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs */ +static void enter_apm_mode(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE9); +} + +void lenovo_s230u_ec_init(void) +{ + set_keyboard_matrix_us(); + + /* + * The EC has a special "blinking Caps Lock LED" mode which it normally + * enters when it believes the OS is not responding. It occasionally + * disables battery charging when in this mode, although other + * functionality is unaffected. Although the EC starts in APM mode by + * default, it only leaves the "blinking Caps Lock LED" mode after + * receiving the following command. + */ + enter_apm_mode(); + + /* Enable external USB port power. */ + ec_mm_set_bit(0x3b, 4); +} diff --git a/src/mainboard/lenovo/s220/ec.h b/src/mainboard/lenovo/s220/ec.h new file mode 100644 index 0000000..273f58b --- /dev/null +++ b/src/mainboard/lenovo/s220/ec.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _MAINBOARD_LENOVO_S230U_EC_H +#define _MAINBOARD_LENOVO_S230U_EC_H + +void lenovo_s230u_ec_init(void); + +#define ECMM(x) (*((volatile u8 *)(CONFIG_EC_BASE_ADDRESS + x))) +#define ec_mm_read(addr) (ECMM(0x100 + addr)) +#define ec_mm_write(addr, data) (ECMM(0x100 + addr) = data) +#define ec_mm_set_bit(addr, bit) (ECMM(0x100 + addr) |= 1 << bit) +#define ec_mm_clr_bit(addr, bit) (ECMM(0x100 + addr) &= ~(1 << bit)) + +#endif /* _MAINBOARD_LENOVO_S230U_EC_H */ diff --git a/src/mainboard/lenovo/s220/gma-mainboard.ads b/src/mainboard/lenovo/s220/gma-mainboard.ads new file mode 100644 index 0000000..03e6a55 --- /dev/null +++ b/src/mainboard/lenovo/s220/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + Analog, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/s220/gpio.c b/src/mainboard/lenovo/s220/gpio.c new file mode 100644 index 0000000..ea8a906 --- /dev/null +++ b/src/mainboard/lenovo/s220/gpio.c @@ -0,0 +1,258 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_OUTPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/s220/hda_verb.c b/src/mainboard/lenovo/s220/hda_verb.c new file mode 100644 index 0000000..0bb7e02 --- /dev/null +++ b/src/mainboard/lenovo/s220/hda_verb.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x14f1506e, /* Codec Vendor / Device ID: Conexant */ + 0x17aa21e4, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa21e4), + AZALIA_PIN_CFG(0, 0x19, 0x04211040), + AZALIA_PIN_CFG(0, 0x1a, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1b, 0x04a11060), + AZALIA_PIN_CFG(0, 0x1c, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1e, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1f, 0x90170110), + AZALIA_PIN_CFG(0, 0x20, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x22, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x23, 0x90a60170), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x17aa21e4, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x17aa21e4), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x58560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/s220/mainboard.c b/src/mainboard/lenovo/s220/mainboard.c new file mode 100644 index 0000000..7f2c7fd --- /dev/null +++ b/src/mainboard/lenovo/s220/mainboard.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <console/console.h> +#include <drivers/intel/gma/int15.h> +#include <ec/acpi/ec.h> +#include <southbridge/intel/common/gpio.h> +#include <string.h> +#include <smbios.h> +#include "ec.h" + +#include <acpi/acpi.h> + +static u8 mainboard_fill_ec_version(char *buf, u8 buf_len) +{ + u8 i, c; + char str[16 + 1]; /* 16 ASCII chars + \0 */ + + /* Build ID */ + for (i = 0; i < 8; i++) { + c = ec_mm_read(0xf0 + i); + if (c < 0x20 || c > 0x7f) { + i = snprintf(str, sizeof(str), "*INVALID"); + break; + } + str[i] = c; + } + + i = MIN(buf_len, i); + memcpy(buf, str, i); + + return i; +} + +static void mainboard_smbios_strings( + struct device *dev, struct smbios_type11 *t) +{ + char tpec[] = "IBM ThinkPad Embedded Controller -[ ]-"; + u16 fwvh, fwvl; + + mainboard_fill_ec_version(tpec + 35, 17); + t->count = smbios_add_string(t->eos, tpec); + + /* Apparently byteswapped compared to H8 */ + fwvh = ec_mm_read(0xe8); + fwvl = ec_mm_read(0xe9); + + printk(BIOS_INFO, "EC Firmware ID %.54s, Version %d.%d%d%c\n", tpec, + fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->get_smbios_strings = mainboard_smbios_strings, + + install_intel_vga_int15_handler( + GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, + 0); + + if (!acpi_is_wakeup_s3()) + lenovo_s230u_ec_init(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/s220/smihandler.c b/src/mainboard/lenovo/s220/smihandler.c new file mode 100644 index 0000000..62bba44 --- /dev/null +++ b/src/mainboard/lenovo/s220/smihandler.c @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/compal/ene932/ec.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/pmutil.h> + +#include "ec.h" + +#define GPE_PALMDET1 2 +#define GPE_PALMDET2 4 +#define GPE_EC_SCI 7 +#define GPE_EC_SMI 8 +/* FIXME: check this */ +#define GPE_EC_WAKE 13 + +enum sleep_states { + S0 = 0, + S1 = 1, + S3 = 3, + S4 = 4, + S5 = 5, +}; + +enum ec_smi_event { + EC_SMI_EVENT_IDLE = 0x80, + EC_SMI_BATTERY_LOW = 0xb3, +}; + +/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs. */ +static void ec_enter_apm_mode(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE9); +} +/* Tell EC to operate in ACPI mode, thus generating SCIs on events, not SMIs. */ +static void ec_enter_acpi_mode(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE8); +} + +static uint8_t ec_get_smi_event(void) +{ + ec_kbc_write_cmd(0x56); + return ec_kbc_read_ob(); +} + +static void ec_process_smi(uint8_t src) +{ + /* + * Reading the SMI source satisfies the EC in terms of responding to + * the event, regardless of whether we take an action or not. + */ + + printk(BIOS_DEBUG, "Unhandled EC_SMI event 0x%x\n", src); +} + +static void handle_ec_smi(void) +{ + uint8_t src; + + while ((src = ec_get_smi_event()) != EC_SMI_EVENT_IDLE) + ec_process_smi(src); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SMI)) + handle_ec_smi(); +} + +int mainboard_smi_apmc(u8 data) +{ + printk(BIOS_INFO, "mainboard_smi_apmc(%02x)\n", data); + + switch (data) { + case APM_CNT_ACPI_ENABLE: + printk(BIOS_DEBUG, "Enable ACPI mode\n"); + ec_enter_acpi_mode(); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + gpi_route_interrupt(GPE_PALMDET1, GPI_IS_SCI); + gpi_route_interrupt(GPE_PALMDET2, GPI_IS_SCI); + break; + case APM_CNT_ACPI_DISABLE: + printk(BIOS_DEBUG, "Disable ACPI mode\n"); + ec_enter_apm_mode(); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + break; + default: + printk(BIOS_DEBUG, "Unhandled ACPI command: 0x%x\n", data); + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == S3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I746798b13e83d1971bb7be93751a15875d16c337 Gerrit-Change-Number: 48771 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: mainboard/asus/p10s-series: Initial port to ASUS P10S-I
by Kevin Cody-Little (Code Review) June 8, 2024

June 8, 2024

Kevin Cody-Little has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37995 ) Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ...................................................................... mainboard/asus/p10s-series: Initial port to ASUS P10S-I Adapt supermicro/x11-lga1151-series for the very similar ASUS P10S-I (and eventually P10S-M) Kaby Lake server boards. This is still very broken but boots to a serial console, and one of the onboard network ports works, so long as a known good kernel is used as the payload. Change-Id: Icd20e69f16421518143b9d80b2a0d821ec37703e Signed-off-by: Kevin Cody <kcodyjr(a)gmail.com> --- A src/mainboard/asus/p10s-series/Kconfig A src/mainboard/asus/p10s-series/Kconfig.name A src/mainboard/asus/p10s-series/Makefile.inc A src/mainboard/asus/p10s-series/acpi/ec.asl A src/mainboard/asus/p10s-series/acpi/mainboard.asl A src/mainboard/asus/p10s-series/acpi/superio.asl A src/mainboard/asus/p10s-series/acpi_tables.c A src/mainboard/asus/p10s-series/board_info.txt A src/mainboard/asus/p10s-series/bootblock.c A src/mainboard/asus/p10s-series/cmos.default A src/mainboard/asus/p10s-series/cmos.layout A src/mainboard/asus/p10s-series/devicetree.cb A src/mainboard/asus/p10s-series/dsdt.asl A src/mainboard/asus/p10s-series/include/mainboard.h A src/mainboard/asus/p10s-series/mainboard.c A src/mainboard/asus/p10s-series/ramstage.c A src/mainboard/asus/p10s-series/romstage.c A src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt A src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h A src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb A src/mainboard/asus/p10s-series/variants/p10s-m/Makefile.inc A src/mainboard/asus/p10s-series/variants/p10s-m/board_info.txt A src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h A src/mainboard/asus/p10s-series/variants/p10s-m/mainboard.c A src/mainboard/asus/p10s-series/variants/p10s-m/overridetree.cb A src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd 26 files changed, 1,452 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37995/1 diff --git a/src/mainboard/asus/p10s-series/Kconfig b/src/mainboard/asus/p10s-series/Kconfig new file mode 100644 index 0000000..eac2272 --- /dev/null +++ b/src/mainboard/asus/p10s-series/Kconfig @@ -0,0 +1,89 @@ +config BOARD_ASUS_P10S_SERIES + def_bool n + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select MAINBOARD_HAS_LPC_TPM + select DRIVERS_ASPEED_AST2050 + select SUPERIO_ASPEED_AST2400 + select GENERATE_SMBIOS_TABLES + select IPMI_KCS + select MAINBOARD_NO_FSP_GOP + select SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND + select NO_FADT_8042 + +if BOARD_ASUS_P10S_SERIES + +config MAINBOARD_FAMILY + string + default "ASUS_P10S_SERIES" + +config MAINBOARD_PART_NUMBER + string + default "P10S-I" if BOARD_ASUS_P10S_I + default "P10S-M" if BOARD_ASUS_P10S_M + +config MAINBOARD_DIR + string + default "asus/p10s-series" + +config VARIANT_DIR + string + default "p10s-i" if BOARD_ASUS_P10S_I + default "p10s-m" if BOARD_ASUS_P10S_M + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +if VBOOT + +config VBOOT_SLOTS_RW_AB + default y + +endif + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro-rwab.fmd" if VBOOT_SLOTS_RW_AB + +config CBFS_SIZE + hex + default 0xb00000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config CONSOLE_POST + bool + default y + +config POST_DEVICE + bool + default n + +config DIMM_SPD_SIZE + int + default 512 + +endif # BOARD_ASUS_P10S_SERIES diff --git a/src/mainboard/asus/p10s-series/Kconfig.name b/src/mainboard/asus/p10s-series/Kconfig.name new file mode 100644 index 0000000..bd696e9 --- /dev/null +++ b/src/mainboard/asus/p10s-series/Kconfig.name @@ -0,0 +1,7 @@ +config BOARD_ASUS_P10S_I + bool "P10S-I" + select BOARD_ASUS_P10S_SERIES + +#config BOARD_ASUS_P10S_M +# bool "P10S-M" +# select BOARD_ASUS_P10S_SERIES diff --git a/src/mainboard/asus/p10s-series/Makefile.inc b/src/mainboard/asus/p10s-series/Makefile.inc new file mode 100644 index 0000000..cab662a --- /dev/null +++ b/src/mainboard/asus/p10s-series/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/asus/p10s-series/acpi/ec.asl b/src/mainboard/asus/p10s-series/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p10s-series/acpi/ec.asl diff --git a/src/mainboard/asus/p10s-series/acpi/mainboard.asl b/src/mainboard/asus/p10s-series/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p10s-series/acpi/mainboard.asl diff --git a/src/mainboard/asus/p10s-series/acpi/superio.asl b/src/mainboard/asus/p10s-series/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p10s-series/acpi/superio.asl diff --git a/src/mainboard/asus/p10s-series/acpi_tables.c b/src/mainboard/asus/p10s-series/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p10s-series/acpi_tables.c diff --git a/src/mainboard/asus/p10s-series/board_info.txt b/src/mainboard/asus/p10s-series/board_info.txt new file mode 100644 index 0000000..cfa02bc --- /dev/null +++ b/src/mainboard/asus/p10s-series/board_info.txt @@ -0,0 +1,2 @@ +Category: server +Vendor name: ASUS diff --git a/src/mainboard/asus/p10s-series/bootblock.c b/src/mainboard/asus/p10s-series/bootblock.c new file mode 100644 index 0000000..75afd2e --- /dev/null +++ b/src/mainboard/asus/p10s-series/bootblock.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <variant/gpio.h> +#include <superio/aspeed/common/aspeed.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <delay.h> +#include <console/uart.h> + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +static void early_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} + +void bootblock_mainboard_early_init(void) +{ + early_config_gpio(); + early_config_superio(); +} diff --git a/src/mainboard/asus/p10s-series/cmos.default b/src/mainboard/asus/p10s-series/cmos.default new file mode 100644 index 0000000..d564953 --- /dev/null +++ b/src/mainboard/asus/p10s-series/cmos.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Enable diff --git a/src/mainboard/asus/p10s-series/cmos.layout b/src/mainboard/asus/p10s-series/cmos.layout new file mode 100644 index 0000000..03aea17 --- /dev/null +++ b/src/mainboard/asus/p10s-series/cmos.layout @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: cpu +400 1 e 2 hyper_threading + +# ----------------------------------------------------------------- +# coreboot config options: southbridge +409 2 e 7 power_on_after_fail + +# ----------------------------------------------------------------- +# coreboot config options: bootloader +448 128 r 0 vbnv + +# ----------------------------------------------------------------- +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asus/p10s-series/devicetree.cb b/src/mainboard/asus/p10s-series/devicetree.cb new file mode 100644 index 0000000..efb1585 --- /dev/null +++ b/src/mainboard/asus/p10s-series/devicetree.cb @@ -0,0 +1,174 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Disabled" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # SATA configuration + register "SataMode" = "KBLFSP_SATA_MODE_AHCI" + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + register "SataPortsDevSlp" = "{\ + [0] = 0, \ + [1] = 0, \ + [2] = 0, \ + [3] = 0, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" + + # superspeed_inter-chip_supplement (SSIC) disabled + register "SsicPortEnable" = "0" + + # USB + register "usb2_ports" = "{ + [0] = USB2_PORT_EMPTY, + [1] = USB2_PORT_EMPTY, + [2] = USB2_PORT_EMPTY, + [3] = USB2_PORT_EMPTY, + [4] = USB2_PORT_EMPTY, + [5] = USB2_PORT_EMPTY, + [6] = USB2_PORT_EMPTY, + [7] = USB2_PORT_EMPTY, + [8] = USB2_PORT_EMPTY, + [9] = USB2_PORT_EMPTY, + [10] = USB2_PORT_EMPTY, + [11] = USB2_PORT_EMPTY, + [12] = USB2_PORT_EMPTY, + [13] = USB2_PORT_EMPTY, + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_EMPTY, + [1] = USB3_PORT_EMPTY, + [2] = USB3_PORT_EMPTY, + [3] = USB3_PORT_EMPTY, + [4] = USB3_PORT_EMPTY, + [5] = USB3_PORT_EMPTY, + [6] = USB3_PORT_EMPTY, + [7] = USB3_PORT_EMPTY, + [8] = USB3_PORT_EMPTY, + [9] = USB3_PORT_EMPTY, + }" + + # LPC + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + register "s0ix_enable" = "1" + register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" + register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" + register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" + register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" + + # No extra VR mailbox command + register "SendVrMbxCmd" = "0" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 on end # CPU PCIe Port 10 (x16) + device pci 01.1 off end # CPU PCIe Port 11 (x8) + device pci 01.2 off end # CPU PCIe Port 12 (x4) + device pci 02.0 off end # Integrated Graphics Device (IGD) + device pci 04.0 off end # SA thermal subsystem + device pci 05.0 off end # Imaging Unit + device pci 08.0 off end # Gaussion Mixture Model (GMM) + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 on end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1b.0 off end # PCH PCIe Port 17 + device pci 1b.1 off end # PCH PCIe Port 18 + device pci 1b.2 off end # PCH PCIe Port 19 + device pci 1b.3 off end # PCH PCIe Port 20 + device pci 1c.0 on end # PCH PCIe Port 1 + device pci 1c.1 off end # PCH PCIe Port 2 + device pci 1c.2 off end # PCH PCIe Port 3 + device pci 1c.3 off end # PCH PCIe Port 4 + device pci 1c.4 off end # PCH PCIe Port 5 + device pci 1c.5 on end # PCH PCIe Port 6 + device pci 1c.6 on end # PCH PCIe Port 7 + device pci 1c.7 off end # PCH PCIe Port 8 + device pci 1d.0 off end # PCH PCIe Port 9 + device pci 1d.1 off end # PCH PCIe Port 10 + device pci 1d.2 off end # PCH PCIe Port 11 + device pci 1d.3 off end # PCH PCIe Port 12 + device pci 1d.4 off end # PCH PCIe Port 13 + device pci 1d.5 off end # PCH PCIe Port 14 + device pci 1d.6 off end # PCH PCIe Port 15 + device pci 1d.7 off end # PCH PCIe Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # SPI #0 + device pci 1f.0 on # LPC Interface + chip superio/common + device pnp 2e.0 on end + end + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 on end + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 off end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # SPI Controller + device pci 1f.6 off end # GbE + device pci 1f.7 off end # Intel Trace Hub + end +end diff --git a/src/mainboard/asus/p10s-series/dsdt.asl b/src/mainboard/asus/p10s-series/dsdt.asl new file mode 100644 index 0000000..b88b1d2 --- /dev/null +++ b/src/mainboard/asus/p10s-series/dsdt.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <southbridge/intel/common/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/asus/p10s-series/include/mainboard.h b/src/mainboard/asus/p10s-series/include/mainboard.h new file mode 100644 index 0000000..ce84441 --- /dev/null +++ b/src/mainboard/asus/p10s-series/include/mainboard.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _BOARD_ASUS_P10S_SERIES_H +#define _BOARD_ASUS_P10S_SERIES_H + +#include <device/device.h> + +void variant_mainboard_init(struct device *dev); + +#endif /* _OARD_ASUS_P10S_SERIES_H */ diff --git a/src/mainboard/asus/p10s-series/mainboard.c b/src/mainboard/asus/p10s-series/mainboard.c new file mode 100644 index 0000000..750c856 --- /dev/null +++ b/src/mainboard/asus/p10s-series/mainboard.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mainboard.h> +#include <device/device.h> + +__weak void variant_mainboard_init(struct device *dev) +{ +} + +static void mainboard_init(struct device *dev) +{ + /* do common init */ + // placeholder for common mainboard initialization + + /* do variant init */ + variant_mainboard_init(dev); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/p10s-series/ramstage.c b/src/mainboard/asus/p10s-series/ramstage.c new file mode 100644 index 0000000..a16678e --- /dev/null +++ b/src/mainboard/asus/p10s-series/ramstage.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <soc/ramstage.h> +#include <variant/gpio.h> + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/asus/p10s-series/romstage.c b/src/mainboard/asus/p10s-series/romstage.c new file mode 100644 index 0000000..cb1f105 --- /dev/null +++ b/src/mainboard/asus/p10s-series/romstage.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + mem_cfg->UserBd = BOARD_TYPE_SERVER; + + mupd->FspmTestConfig.DmiVc1 = 1; +} diff --git a/src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt b/src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt new file mode 100644 index 0000000..adfd6c0 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Vendor name: ASUS +Board name: P10S-I +Board URL: https://www.asus.com/us/Commercial-Servers-Workstations/P10S-I/ +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h b/src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h new file mode 100644 index 0000000..a08ea53 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h @@ -0,0 +1,246 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_ASUS_P10S_I_H +#define _GPIO_ASUS_P10S_I_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { +/* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000), +/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), +/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), +/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), +/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), +/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), +/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), +/* PIRQA# */ _PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x00000000), +/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), +/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), +/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), +/* PME# */ _PAD_CFG_STRUCT(GPP_A11, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x80080201, 0x00000000), +/* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000000), +/* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000000), +/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x00000000), +/* CLKOUT_48 */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000000), +/* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000000), +/* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000000), +/* SPKR */ _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000000), +/* PCHHOT# */ _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x84000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x84000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C22, 0x42040102, 0x00003000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D2, 0x42020102, 0x00003000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000000), +/* SATAXPCIE0 */ _PAD_CFG_STRUCT(GPP_E0, 0x44000502, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x82020102, 0x00003000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000000), +/* SATA_LED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000000), +/* USB_OC0# */ _PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x00000000), +/* USB_OC1# */ _PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x00000000), +/* USB_OC2# */ _PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x00000000), +/* USB_OC3# */ _PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F5, 0x80100102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000000), +/* SATA_SCLOCK */ _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000000), +/* SATA_SLOAD */ _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000000), +/* SATA_SDATAOUT1 */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000000), +/* SATA_SDATAOUT2 */ _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000000), +/* USB_OC4# */ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x00000000), +/* USB_OC5# */ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G14, 0x84000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000000), +/* NMI# */ _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000000), +/* SMI# */ _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H1, 0x84000103, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000000), +/* SRCCLKREQ9# */ _PAD_CFG_STRUCT(GPP_H3, 0x44000602, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H4, 0x84000103, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000000), +/* SML2CLK */ _PAD_CFG_STRUCT(GPP_H10, 0x44000702, 0x00000000), +/* SML2DATA */ _PAD_CFG_STRUCT(GPP_H11, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000000), +/* SML3CLK */ _PAD_CFG_STRUCT(GPP_H13, 0x44000702, 0x00000000), +/* SML3DATA */ _PAD_CFG_STRUCT(GPP_H14, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000000), +/* SML4CLK */ _PAD_CFG_STRUCT(GPP_H16, 0x44000702, 0x00000000), +/* SML4DATA */ _PAD_CFG_STRUCT(GPP_H17, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000000), +/* LAN_WAKE# */ _PAD_CFG_STRUCT(GPD2, 0x04000702, 0x00000000), +/* PWRBTN# */ _PAD_CFG_STRUCT(GPD3, 0x04000702, 0x00000000), +/* SLP_S3# */ _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000000), +/* SLP_S4# */ _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000000), +/* SLP_A# */ _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000000), +/* SUSCLK */ _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000000), +/* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000000), +/* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000000), +/* DDPD_HPD2 */ _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000000), +/* DDPE_HPD3 */ _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000000), +/* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000000), +/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000000), +/* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000000), +/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000000), +/* DDPD_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000000), +/* DDPD_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000000), +}; + + +/*** XXX TODO XXX */ +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* LPC */ + +/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), +/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), +/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), +/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), +/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), +/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), +/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), +/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), +/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), +}; + +#endif /* _GPIO_ASUS_P10S_I_H */ diff --git a/src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb b/src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb new file mode 100644 index 0000000..2e722e4 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb @@ -0,0 +1,143 @@ +chip soc/intel/skylake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen3_dec" = "0x000c03e1" # UART3 + register "gen4_dec" = "0x000c02e1" # UART4 + + # PCIe configuration +# # Enable JPCIE1 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "0" + +# # Enable ASpeed PCI bridge +# register "PcieRpEnable[2]" = "1" +# register "PcieRpClkReqSupport[2]" = "0" + +# # Enable X550T (10GbE) +# register "PcieRpEnable[4]" = "1" +# register "PcieRpClkReqSupport[4]" = "0" + + # Enable I210 + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "0" + + # Enable I210 + register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "0" + + # Enable M.2 + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "0" + + # FIXME: find out why FSP crashes without this + register "PchHdaVcType" = "Vc1" + + # USB configuration + # USB2/3 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + + # ? + register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" + + # USB4/5 + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + + # USB0/1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + + # USB9/10 (USB3.0) + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" + + # USB6/7 (USB3.0) + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" + + # USB8 (USB3.0) + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" + + # IPMI USB HUB + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + device domain 0 on + device pci 01.0 on # CPU PCIe Slot + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X16" "SlotDataBusWidth16X" + end + device pci 1c.0 on # PCI Express Port 1 + device pci 00.0 on # Aspeed PCI Bridge + device pci 00.0 on end # Aspeed 2400 VGA + end + end + device pci 1c.5 on # PCI Express Port 5 + device pci 00.0 on end # 1GbE + end + device pci 1c.6 on # PCI Express Port 6 + device pci 00.0 on end # 1GbE + end + device pci 1d.0 on # PCI Express Port 9 + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2242" "SlotDataBusWidth4X" + end + device pci 1f.0 on # LPC Interface + chip drivers/ipmi + # On cold boot it takes a while for the BMC to start the IPMI service + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0xb + end + device pnp 2e.5 off end # KBC + device pnp 2e.7 on end # GPIO + device pnp 2e.b on # SUART3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.c on # SUART4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.d on end # iLPC2AHB + device pnp 2e.e on # Mailbox + io 0x60 = 0xa40 + irq 0x70 = 0x00 + end + end + end + end + end + end +end diff --git a/src/mainboard/asus/p10s-series/variants/p10s-m/Makefile.inc b/src/mainboard/asus/p10s-series/variants/p10s-m/Makefile.inc new file mode 100644 index 0000000..f3c87b2 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-m/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += mainboard.c diff --git a/src/mainboard/asus/p10s-series/variants/p10s-m/board_info.txt b/src/mainboard/asus/p10s-series/variants/p10s-m/board_info.txt new file mode 100644 index 0000000..b868459 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-m/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Vendor name: ASUS +Board name: P10S-M +Board URL: https://www.asus.com/us/Commercial-Servers-Workstations/P10S-M/ +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h b/src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h new file mode 100644 index 0000000..4c551d1 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h @@ -0,0 +1,269 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_ASUS_P10S_M_H +#define _GPIO_ASUS_P10S_M_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + _PAD_CFG_STRUCT(GPP_A0, 0x44000700, 0x00000010), /* RCIN# */ + _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */ + _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */ + _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */ + _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */ + _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */ + _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */ + _PAD_CFG_STRUCT(GPP_A7, 0x44000700, 0x00000010), /* PIRQA# */ + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */ + _PAD_CFG_STRUCT(GPP_A11, 0x44000700, 0x00000010), /* PME# */ + _PAD_CFG_STRUCT(GPP_A12, 0x84000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000010), /* SUSWARN#/SUSPWRDNACK */ + _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000010), /* SUS_STAT# */ + _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x00000010), /* SUS_ACK# */ + _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000010), /* CLKOUT_48 */ + _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000010), /* GPIO */ + /* reserved */ + //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffffff), /* ISH_GP1 */ + _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_B */ + _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000010), /* SLP_S0# */ + _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000010), /* PLTRST# */ + _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000010), /* SPKR */ + _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000010), /* PCHHOT# */ + + /* GPIO Group GPP_C */ + /* reserved */ + //_PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x00000010), /* SMBCLK */ + //_PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x00000010), /* SMBDATA */ + _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000010), /* GPIO */ + /* reserved */ + //_PAD_CFG_STRUCT(GPP_C3, 0x44000700, 0x00000010), /* SML0CLK */ + //_PAD_CFG_STRUCT(GPP_C4, 0x44000700, 0x00000010), /* SML0DATA */ + _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000010), /* GPIO */ + /* reserved */ + //_PAD_CFG_STRUCT(GPP_C6, 0x44000700, 0x00000010), /* SML1CLK */ + //_PAD_CFG_STRUCT(GPP_C7, 0x44000700, 0x00000010), /* SML1DATA */ + _PAD_CFG_STRUCT(GPP_C8, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C10, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C22, 0x42040100, 0x00003010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_D */ + _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D2, 0x42020100, 0x00003000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D22, 0x04000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_E */ + _PAD_CFG_STRUCT(GPP_E0, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E6, 0x82020100, 0x00003000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000010), /* SATA_LED# */ + _PAD_CFG_STRUCT(GPP_E9, 0x44000700, 0x00000010), /* USB_OC0# */ + _PAD_CFG_STRUCT(GPP_E10, 0x44000700, 0x00000010), /* USB_OC1# */ + _PAD_CFG_STRUCT(GPP_E11, 0x44000700, 0x00000010), /* USB_OC2# */ + _PAD_CFG_STRUCT(GPP_E12, 0x44000700, 0x00000010), /* USB_OC3# */ + + /* GPIO Group GPP_F */ + _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F5, 0x80100100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F9, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000010), /* SATA_SCLOCK */ + _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000010), /* SATA_SLOAD */ + _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000010), /* SATA_SDATAOUT1 */ + _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000010), /* SATA_SDATAOUT2 */ + _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x00000010), /* USB_OC4# */ + _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x00000010), /* USB_OC5# */ + _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_G */ + _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G2, 0x44000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G14, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000010), /* NMI# */ + _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000010), /* SMI# */ + _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_H */ + _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H1, 0x84000101, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H3, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H4, 0x84000101, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H10, 0x44000700, 0x00000010), /* SML2CLK */ + _PAD_CFG_STRUCT(GPP_H11, 0x44000700, 0x00000010), /* SML2DATA */ + _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H13, 0x44000700, 0x00000010), /* SML3CLK */ + _PAD_CFG_STRUCT(GPP_H14, 0x44000700, 0x00000010), /* SML3DATA */ + _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H16, 0x44000700, 0x00000010), /* SML4CLK */ + _PAD_CFG_STRUCT(GPP_H17, 0x44000700, 0x00000010), /* SML4DATA */ + _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_I */ + _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000010), /* DDPB_HPD0 */ + _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000010), /* DDPC_HPD1 */ + _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000010), /* DDPD_HPD2 */ + _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000010), /* DDPE_HPD3 */ + _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000010), /* DDPB_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000010), /* DDPB_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000010), /* DDPC_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000010), /* DDPC_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000010), /* DDPD_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000010), /* DDPD_CTRLDATA */ + + /* GPIO Group GPD */ + _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD2, 0x04000700, 0x00000010), /* LAN_WAKE# */ + _PAD_CFG_STRUCT(GPD3, 0x04000700, 0x00000010), /* PWRBTN# */ + _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000010), /* SLP_S3# */ + _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000010), /* SLP_S4# */ + _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000010), /* SLP_A# */ + _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000010), /* SUSCLK */ + _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000010), /* GPIO */ +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* GPIO Group GPP_A */ + /* LPC */ + _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */ + _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */ + _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */ + _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */ + _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */ + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */ + + /* Serial interrupt */ + _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */ +}; + +#endif /* _GPIO_ASUS_P10S_M_H */ diff --git a/src/mainboard/asus/p10s-series/variants/p10s-m/mainboard.c b/src/mainboard/asus/p10s-series/variants/p10s-m/mainboard.c new file mode 100644 index 0000000..7cf8883 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-m/mainboard.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mainboard.h> +#include <device/device.h> +#include <intelblocks/itss.h> +#include <intelblocks/pcr.h> +#include <soc/itss.h> +#include <soc/pcr_ids.h> + +void variant_mainboard_init(struct device *dev) +{ + /* TODO: + * Find out why the polarities from gpio.h gets overwritten by FSP. + * This sets irq polarity to the same values as vendor + * but I do not know if this is really needed.... + */ + itss_set_irq_polarity(33, 0); + itss_set_irq_polarity(34, 0); + + // TODO: NMI; is this needed? vendor sets it + pcr_write32(0xae, 0x01e4, 0x00000004); + pcr_write32(0xae, 0x01e8, 0x00000040); +} diff --git a/src/mainboard/asus/p10s-series/variants/p10s-m/overridetree.cb b/src/mainboard/asus/p10s-series/variants/p10s-m/overridetree.cb new file mode 100644 index 0000000..ea90e0b --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-m/overridetree.cb @@ -0,0 +1,124 @@ +chip soc/intel/skylake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_G" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen3_dec" = "0x000c03e1" # UART3 + register "gen4_dec" = "0x000c02e1" # UART4 + + # PCIe configuration + register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4 + register "PcieRpEnable[4]" = "1" # Enable PCH PCIe Port 5 / PCH SLOT5 + register "PcieRpEnable[8]" = "1" # Enable PCH PCIe Port 9 / GbE 1 + register "PcieRpEnable[9]" = "1" # Enable PCH PCIe Port 10 / GbE 2 + register "PcieRpEnable[10]" = "1" # Enable PCH PCIe Port 11 / Aspeed 2400 VGA + + # USB configuration + # USB0/1 + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + + # USB2/3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + + # USB4/5 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + + # USB6/7 (USB3.0) + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)" + + # USB8/9 (USB3.0) + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" + register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + + # USB10 (USB3.0) + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC5)" + + # IPMI USB HUB + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" + + device domain 0 on + device pci 01.0 on # CPU PCIe Port (x16) / PCIe Slot 6 (JPCIE6) + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" + end + device pci 01.1 on # CPU PCIe Port (x8) / PCIe Slot 7 (JPCIE7) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X" + end + device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" + end + device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" + end + device pci 1d.0 on # PCH PCIe Port 9 + device pci 00.0 on end # GbE 1 + end + device pci 1d.1 on # PCH PCIe Port 10 + device pci 00.1 on end # GbE 2 + end + device pci 1d.2 on # PCH PCIe Port 11 + device pci 00.0 on # Aspeed PCI Bridge + device pci 00.0 on end # Aspeed 2400 VGA + end + end + device pci 1f.0 on # LPC Interface + chip drivers/ipmi + # On cold boot it takes a while for the BMC to start the IPMI service + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 / COM1 (ext) + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 / COM2 (int) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0xb + end + device pnp 2e.5 off end # KBC + device pnp 2e.7 on end # GPIO + device pnp 2e.b on # SUART3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.c on # SUART4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.d on end # iLPC2AHB + device pnp 2e.e on # Mailbox + io 0x60 = 0xa40 + irq 0x70 = 0x00 + end + end + end + end + end + end +end diff --git a/src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd b/src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd new file mode 100644 index 0000000..a295680 --- /dev/null +++ b/src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd @@ -0,0 +1,36 @@ +FLASH 16M { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x4ff000 + } + SI_BIOS@0x500000 0xb00000 { + RW_SECTION_A@0x0 0x33e000 { + VBLOCK_A@0x0 0x20000 + FW_MAIN_A(CBFS)@0x20000 0x31dfc0 + RW_FWID_A@0x33dfc0 0x40 + } + RW_SECTION_B@0x33e000 0x33e000 { + VBLOCK_B@0x0 0x20000 + FW_MAIN_B(CBFS)@0x20000 0x31dfc0 + RW_FWID_B@0x33dfc0 0x40 + } + MISC_RW@0x67d000 0x62000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x20000 0x2000 + SMMSTORE(PRESERVE)@0x22000 0x40000 + } + WP_RO@0x6df000 0x421000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x41d000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x32d000 + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd20e69f16421518143b9d80b2a0d821ec37703e Gerrit-Change-Number: 37995 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Cody-Little <kcodyjr(a)gmail.com> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/...
by Matt Parnell (Code Review) June 8, 2024

June 8, 2024

Matt Parnell has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34946 ) Change subject: WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port ...................................................................... WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/ec/hp/it8987e/Kconfig A src/ec/hp/it8987e/Makefile.inc A src/ec/hp/it8987e/acpi/ac.asl A src/ec/hp/it8987e/acpi/battery.asl A src/ec/hp/it8987e/acpi/ec.asl A src/ec/hp/it8987e/acpi/kb.asl A src/ec/hp/it8987e/acpi/superio.asl A src/ec/hp/it8987e/acpi/tpm.asl A src/ec/hp/it8987e/chip.h A src/ec/hp/it8987e/ec.c A src/ec/hp/it8987e/ec.h A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 31 files changed, 5,065 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/1 diff --git a/src/ec/hp/it8987e/Kconfig b/src/ec/hp/it8987e/Kconfig new file mode 100644 index 0000000..54f7896 --- /dev/null +++ b/src/ec/hp/it8987e/Kconfig @@ -0,0 +1,4 @@ +config EC_HP_IT8987E + bool + help + Interface to QUANTA/HP IT8987E Embedded Controller. diff --git a/src/ec/hp/it8987e/Makefile.inc b/src/ec/hp/it8987e/Makefile.inc new file mode 100644 index 0000000..db11205 --- /dev/null +++ b/src/ec/hp/it8987e/Makefile.inc @@ -0,0 +1,8 @@ +ifeq ($(CONFIG_EC_HP_IT8987E),y) + +romstage-y += ec.c +ramstage-y += ec.c +smm-y += ec.c +smm-y += ../../../lib/delay.c + +endif diff --git a/src/ec/hp/it8987e/acpi/ac.asl b/src/ec/hp/it8987e/acpi/ac.asl new file mode 100644 index 0000000..bb4b4fe --- /dev/null +++ b/src/ec/hp/it8987e/acpi/ac.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope (EC0) + +Device (AC) +{ + Name (_HID, "ACPI0003") + Name (_PCL, Package () { \_SB }) + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + If ((^^PCI0.LPCB.EC0.ECOK == One)) + { + Local0 = ^^PCI0.LPCB.EC0.SW2S + } + Else + { + Local0 = One + } + + Return (Local0) + } + + Method (_STA) + { + Return (0x0F) + } +} diff --git a/src/ec/hp/it8987e/acpi/battery.asl b/src/ec/hp/it8987e/acpi/battery.asl new file mode 100644 index 0000000..75efd92 --- /dev/null +++ b/src/ec/hp/it8987e/acpi/battery.asl @@ -0,0 +1,252 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2013 Google Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; version 2 of +* the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +Device (BAT0) +{ + Name (FRST, One) + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (PBIF, Package (0x0D) + { + One, + 0xFFFFFFFF, + 0xFFFFFFFF, + One, + 0xFFFFFFFF, + 0xFA, + 0x96, + 0x0A, + 0x19, + "BAT0", + " ", + " ", + " " + }) + Name (PBST, Package (0x04) + { + Zero, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0x2710 + }) + Name (BAST, Zero) + Name (B1ST, 0x0F) + Name (B1WT, Zero) + Name (FABL, 0xFFFFFFFF) + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((^^PCI0.LPCB.EC0.ECOK == One)) + { + If (^^PCI0.LPCB.EC0.MBTS) + { + B1ST = 0x1F + } + Else + { + B1ST = 0x0F + } + } + Else + { + B1ST = 0x0F + } + + Return (B1ST) /* \_SB_.BAT0.B1ST */ + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If ((^^PCI0.LPCB.EC0.ECOK == One)) + { + If (^^PCI0.LPCB.EC0.MBTS) + { + UPBI () + } + Else + { + IVBI () + } + } + Else + { + IVBI () + } + + Return (PBIF) /* \_SB_.BAT0.PBIF */ + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If ((^^PCI0.LPCB.EC0.ECOK == One)) + { + If (^^PCI0.LPCB.EC0.MBTS) + { + UPBS () + } + Else + { + IVBS () + } + } + Else + { + IVBS () + } + + Return (PBST) /* \_SB_.BAT0.PBST */ + } + + Method (UPBI, 0, NotSerialized) + { + Local5 = ^^PCI0.LPCB.EC0.BFCC /* \_SB_.PCI0.LPCB.EC0_.BFCC */ + If ((Local5 && !(Local5 & 0x8000))) + { + Local5 >>= 0x05 + Local5 <<= 0x05 + PBIF [One] = Local5 + PBIF [0x02] = Local5 + Local2 = (Local5 / 0x64) + Local2 += One + If ((^^PCI0.LPCB.EC0.BADC < 0x0C80)) + { + Local4 = (Local2 * 0x0E) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x09) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x0B) + } + ElseIf ((SMA4 == One)) + { + Local4 = (Local2 * 0x0A) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x05) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x08) + } + Else + { + Local4 = (Local2 * 0x0C) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x07) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x0A) + } + + FABL = (Local4 + 0x02) + } + + Local0 = ^^PCI0.LPCB.EC0.BVLB /* \_SB_.PCI0.LPCB.EC0_.BVLB */ + Local1 = ^^PCI0.LPCB.EC0.BVHB /* \_SB_.PCI0.LPCB.EC0_.BVHB */ + Local1 <<= 0x08 + Local0 |= Local1 + PBIF [0x04] = Local0 + Sleep (0x32) + PBIF [0x0B] = "LION" + PBIF [0x09] = "Primary" + UPUM () + PBIF [Zero] = One + } + + Method (UPUM, 0, NotSerialized) + { + Local0 = Buffer (0x0A) + { + /* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00 // .. + } + Local6 = Buffer (0x05) + { + 0x36, 0x35, 0x35, 0x33, 0x35 // 65535 + } + Local7 = Buffer (0x05) + { + 0x31, 0x32, 0x33, 0x32, 0x31 // 12321 + } + PBIF [0x0C] = "HP" + } + + Method (UPBS, 0, NotSerialized) + { + If ((BRTM == One)) + { + Local0 = ^^PCI0.LPCB.EC0.MCUR /* \_SB_.PCI0.LPCB.EC0_.MCUR */ + If ((Local0 & 0x8000)) + { + If ((Local0 == 0xFFFF)) + { + PBST [One] = 0xFFFFFFFF + } + Else + { + Local1 = ~Local0 + Local1++ + Local3 = (Local1 & 0xFFFF) + PBST [One] = Local3 + } + } + Else + { + PBST [One] = Local0 + } + } + Else + { + PBST [One] = 0xFFFFFFFF + } + + Local5 = ^^PCI0.LPCB.EC0.MBRM /* \_SB_.PCI0.LPCB.EC0_.MBRM */ + If (!(Local5 & 0x8000)) + { + Local5 >>= 0x05 + Local5 <<= 0x05 + If ((Local5 != DerefOf (PBST [0x02]))) + { + PBST [0x02] = Local5 + } + } + + If ((!^^PCI0.LPCB.EC0.SW2S && (^^PCI0.LPCB.EC0.BACR == One))) + { + PBST [0x02] = FABL /* \_SB_.BAT0.FABL */ + } + + PBST [0x03] = ^^PCI0.LPCB.EC0.MBCV /* \_SB_.PCI0.LPCB.EC0_.MBCV */ + PBST [Zero] = ^^PCI0.LPCB.EC0.MBST /* \_SB_.PCI0.LPCB.EC0_.MBST */ + } + + Method (IVBI, 0, NotSerialized) + { + PBIF [One] = 0xFFFFFFFF + PBIF [0x02] = 0xFFFFFFFF + PBIF [0x04] = 0xFFFFFFFF + PBIF [0x09] = "Bad" + PBIF [0x0A] = "Bad" + PBIF [0x0B] = "Bad" + PBIF [0x0C] = "Bad" + } + + Method (IVBS, 0, NotSerialized) + { + PBST [Zero] = Zero + PBST [One] = 0xFFFFFFFF + PBST [0x02] = 0xFFFFFFFF + PBST [0x03] = 0x2710 + } +} diff --git a/src/ec/hp/it8987e/acpi/ec.asl b/src/ec/hp/it8987e/acpi/ec.asl new file mode 100644 index 0000000..0692ced --- /dev/null +++ b/src/ec/hp/it8987e/acpi/ec.asl @@ -0,0 +1,1201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * The mainboard must define a PNOT method to handle power + * state notifications and Notify CPU device objects to + * re-evaluate their _PPC and _CST tables. + */ + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (PHOT, One) + Name (ECAV, Zero) + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (BFFR, ResourceTemplate () + { + IO (Decode16, + 0x0062, // Range Minimum + 0x0062, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0066, // Range Minimum + 0x0066, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + }) + Return (BFFR) /* \_SB_.PCI0.LPCB.EC0_._CRS.BFFR */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + ^^^GFX0.CLID = 0x03 + Return (0x0F) + } + + OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + SMPR, 8, + SMST, 8, + SMAD, 8, + SMCM, 8, + SMD0, 256, + BCNT, 8, + SMAA, 8, + Offset (0x40), + SW2S, 1, + , 2, + ACCC, 1, + TRPM, 1, + Offset (0x41), + W7OS, 1, + QWOS, 1, + , 1, + SUSE, 1, + RFLG, 1, + Offset (0x43), + , 1, + , 1, + ACPS, 1, + ACKY, 1, + GFXT, 1, + Offset (0x44), + , 7, + DSMB, 1, + Offset (0x47), + TNT2, 8, + TNT3, 8, + Offset (0x4C), + STRM, 8, + Offset (0x4E), + LIDE, 1, + Offset (0x4F), + ACID, 8, + , 2, + PTHM, 1, + , 1, + BSEV, 1, + DPTL, 1, + Offset (0x52), + ECLS, 1, + Offset (0x55), + EC45, 8, + Offset (0x58), + RTMP, 8, + TNT1, 8, + Offset (0x5F), + , 1, + Offset (0x61), + SHPM, 8, + Offset (0x67), + , 1, + , 1, + GC6R, 1, + IGC6, 1, + , 2, + PVSE, 1, + PVSS, 1, + , 3, + PLGS, 1, + , 3, + TPDF, 1, + , 4, + BCTF, 1, + BMNF, 1, + BTVD, 1, + BF10, 1, + Offset (0x6C), + GWKR, 8, + Offset (0x70), + BADC, 16, + BFCC, 16, + BVLB, 8, + BVHB, 8, + BDVO, 8, + Offset (0x7F), + ECTB, 1, + Offset (0x82), + MBST, 8, + MCUR, 16, + MBRM, 16, + MBCV, 16, + Offset (0x8B), + LEDM, 3, + Offset (0x8D), + , 5, + MBFC, 1, + Offset (0x92), + SPSV, 8, + Offset (0x94), + GSSU, 1, + GSMS, 1, + Offset (0x95), + MMST, 4, + DMST, 4, + Offset (0xA0), + QBHK, 8, + Offset (0xA2), + QBBB, 8, + Offset (0xA4), + MBTS, 1, + , 6, + BACR, 1, + Offset (0xA6), + MBDC, 8, + Offset (0xA8), + ENWD, 1, + TMPR, 1, + Offset (0xAA), + , 1, + SMSZ, 1, + , 5, + RCDS, 1, + Offset (0xAD), + SADP, 8, + Offset (0xB2), + RPM1, 8, + RPM2, 8, + Offset (0xBA), + CLOW, 8, + CMAX, 8, + Offset (0xC1), + DPPC, 8, + Offset (0xC6), + , 1, + CVTS, 1, + Offset (0xCE), + NVDX, 8, + ECDX, 8, + EBPL, 1, + Offset (0xD2), + , 7, + DLYE, 1, + Offset (0xD4), + PSHD, 8, + PSLD, 8, + DBPL, 8, + STSP, 8, + Offset (0xDA), + PSIN, 8, + PSKB, 1, + PSTP, 1, + , 1, + PWOL, 1, + RTCE, 1, + Offset (0xE0), + DLYT, 8, + DLY2, 8, + Offset (0xE6), + SFHK, 8, + Offset (0xE9), + DTMT, 8, + PL12, 8, + ETMT, 8, + Offset (0xF2), + ZPDD, 1, + , 6, + ENPA, 1, + Offset (0xF4), + SFAN, 8, + Offset (0xF9), + , 7, + FTHM, 1 + } + + Name (ECOK, Zero) + Name (BATO, Zero) + Name (BATN, Zero) + Name (BATF, 0xC0) + Name (TMEE, Zero) + Name (TMDE, Zero) + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + If (((Arg0 == 0x03) && (Arg1 == One))) + { + ECOK = One + GBAS () + ECMI () + } + } + + Method (_GPE, 0, NotSerialized) // _GPE: General Purpose Events + { + Local0 = GGPE (0x02020017) + Return (Local0) + } + + Method (BPOL, 1, NotSerialized) + { + DBPL = Arg0 + EBPL = One + } + + Method (BPOM, 0, NotSerialized) + { + DBPL = Zero + EBPL = Zero + } + + Method (GBAS, 0, NotSerialized) + { + If ((ECOK == One)) + { + BATF = Zero + Local0 = MBTS /* \_SB_.PCI0.LPCB.EC0_.MBTS */ + Local1 = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */ + Local0 <<= 0x06 + Local1 <<= One + If (((BATO & 0x40) != Local0)) + { + BATF |= 0x40 + } + + If (((BATO & 0x02) != Local1)) + { + BATF |= 0x02 + } + + BATO = Zero + BATO = (Local0 | Local1) + } + } + + Method (_Q09, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + BPOM () + GBAS () + Notify (BAT0, 0x80) // Status Change + Notify (BAT0, 0x81) // Information Change + Notify (ADP1, 0x80) // Status Change + } + + Method (_Q0D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "_Q0D : Switch Display (Fn+F4)" + ^^^GFX0.GHDS (Zero) + Sleep (0xC8) + } + + Method (_Q10, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x87) // Device-Specific + } + + Method (_Q11, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x86) // Device-Specific + } + + Method (_Q15, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "!!! Wireless Button pressed !!!" + If ((OSYS >= 0x07DC)) + { + Notify (WLBT, 0x80) // Status Change + } + Else + { + If (BNLS) + { + BNLS = Zero + Local0 = One + } + Else + { + BNLS = One + Local0 = Zero + } + + If ((^^^^WMID.WMIF == One)) + { + If (((WWLS == One) & (WLDS == One))) + { + If (One) + { + SGOV (0x02070002, Local0) + } + Else + { + SGOV (0x01090008, Local0) + } + } + + If (((WBTS == One) & (BTDS == One))) + { + If (One) + { + SGOV (0x0203000C, Local0) + } + Else + { + SGOV (0x0103000C, Local0) + } + } + } + Else + { + If ((WLDS == One)) + { + If (One) + { + SGOV (0x02070002, Local0) + } + Else + { + SGOV (0x01090008, Local0) + } + } + + If ((BTDS == One)) + { + If (One) + { + SGOV (0x0203000C, Local0) + } + Else + { + SGOV (0x0103000C, Local0) + } + } + } + } + } + + Method (_Q20, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + GBAS () + If ((0x40 & BATF)) + { + Notify (BAT0, 0x81) // Information Change + } + + Notify (BAT0, 0x80) // Status Change + If ((0x02 & BATF)) + { + Notify (ADP1, 0x80) // Status Change + PWRS = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */ + If (SW2S) + { + ^^^^WMID.GWEV (0x03, Zero) + } + } + + PNOT () + } + } + + Method (_Q21, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If ((BCTF || BMNF)) + { + ^^^^WMID.GWEV (0x12, One) + } + } + } + + Method (_Q22, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + BACR = Zero + Notify (BAT0, 0x80) // Status Change + } + } + + Method (_Q2A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + Notify (BAT0, 0x80) // Status Change + } + + Method (_Q33, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Local0 = ^^RTC.RTMN /* \_SB_.PCI0.LPCB.RTC_.RTMN */ + FromBCD (Local0, Local0) + Local1 = ^^RTC.RTHR /* \_SB_.PCI0.LPCB.RTC_.RTHR */ + FromBCD (Local1, Local1) + Local2 = ^^RTC.RTDY /* \_SB_.PCI0.LPCB.RTC_.RTDY */ + Local3 = ^^RTC.RTSE /* \_SB_.PCI0.LPCB.RTC_.RTSE */ + FromBCD (Local3, Local3) + If ((ECOK == One)) + { + PSIN = 0xFF + Sleep (One) + PSLD = Local0 + PSHD = Local1 + PSIN = 0x1C + Sleep (One) + PSLD = Local2 + PSHD = Local3 + PSIN = 0x1D + } + } + + Method (_Q34, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If ((ENWD == One)) + { + TMPR = One + } + } + } + + Method (_Q46, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If ((CVTS == One)) + { + Local0 = 0x03 + Local0 <<= 0x10 + Local0 |= 0x03 + ^^^^WFTE.WMDE (Zero, One, Local0) + Notify (VBPA, 0xCC) // Hardware-Specific + } + + If ((CVTS == Zero)) + { + Local0 = 0x02 + Local0 <<= 0x10 + Local0 |= 0x02 + ^^^^WFTE.WMDE (Zero, One, Local0) + Notify (VBPA, 0xCD) // Hardware-Specific + } + } + } + + Method (_Q49, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If ((PVSS == One)) + { + If ((PVSE == One)) + { + ^^^^WMID.GWEV (0x14, 0xFE) + } + Else + { + ^^^^WMID.GWEV (0x14, 0xFF) + } + } + } + } + + Method (_Q4D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + ^^^^WMID.GWEV (0x00020001, Zero) + } + + Method (_Q6F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + ^^^^WMID.GWEV (0x04, Zero) + } + + Method (_Q70, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + SGOV (0x0204000A, Zero) + } + + Method (_Q71, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + SGOV (0x0204000A, One) + } + + Method (_Q80, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Sleep (0x14) + Notify (\_TZ.TZ01, 0x80) // Thermal Status Change + } + + Method (_Q82, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Sleep (0x14) + Debug = "_Q82 : Temperature reachs for Turbo Mode OFF" + TMDE = One + Notify (\_TZ.TZ01, 0x80) // Thermal Status Change + } + + Method (_Q83, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Sleep (0x14) + Debug = "_Q83 : Temperature reachs for Turbo Mode ON" + TMEE = One + Notify (\_TZ.TZ01, 0x80) // Thermal Status Change + } + + Method (_Q84, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((PHOT == One)) + { + PHOT = 0x02 + } + } + + Method (_Q85, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (B0D4, 0x90) // Device-Specific + } + + Method (_Q86, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((PHOT == One)) + { + PHOT = 0x03 + } + } + + Method (_Q8A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If (LIDE) + { + Debug = "_Q8A : LID Switch Event" + LIDE = Zero + Sleep (0x14) + Notify (LID0, 0x80) // Status Change + } + } + } + + Method (_Q8E, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If (CondRefOf (\_PR.PR00._PPC)) + { + Local0 = \_PR.PR00._PPC () + } + + Local1 = (MPPP - One) + If ((Local0 < Local1)) + { + Local0++ + CPUS (Local0) + } + + CLOW = Local0 + } + + Method (_Q8F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If (CondRefOf (\_PR.PR00._PPC)) + { + Local0 = \_PR.PR00._PPC () + } + + If (Local0) + { + Local0-- + CPUS (Local0) + } + + CLOW = Local0 + } + + Method (_Q99, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + } + + Method (_QA0, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + } + + Method (_QA1, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + } + + Method (_QE4, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Local1 = Zero + Local0 = PKPS /* \PKPS */ + If ((Local0 > 0x80)) + { + Local0 -= 0x80 + While ((Local0 > 0x06)) + { + Local0 -= 0x10 + Local1 += 0x06 + } + + Local1 += Local0 + If (((Local1 >= 0x07) & (Local1 <= 0x0C))) + { + Local1 += 0x12 + } + ElseIf (((Local1 >= 0x0D) & (Local1 <= 0x12))) + { + Local1 += 0x06 + } + ElseIf (((Local1 >= 0x13) & (Local1 <= 0x18))) + { + Local1 -= 0x0C + } + ElseIf (((Local1 >= 0x19) & (Local1 <= 0x1E))) + { + Local1 -= 0x0C + } + + Stall (0x05) + Local0 = Zero + Local3 = OFDA /* \OFDA */ + While ((Local1 > One)) + { + Local2 = DerefOf (Local3 [Local0]) + Local0 += Local2 + Local1 -= One + } + + Stall (0x0F) + Local1 = DerefOf (Local3 [Local0]) + Local2 = Zero + Stall (0x0F) + Name (KPFT, Buffer (0xA0){}) + While ((Local2 < 0xA0)) + { + If ((Local1 > Zero)) + { + KPFT [Local2] = DerefOf (Local3 [Local0]) + Local0++ + Local1 -= One + } + Else + { + KPFT [Local2] = Zero + } + + Local2++ + Stall (0x05) + } + + PKMC = KPFT /* \_SB_.PCI0.LPCB.EC0_._QE4.KPFT */ + PKWD = One + } + } + + Method (_QE5, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + ^^^^WMID.GWEV (0x12, PKPS) + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + SMW0, 16 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + SMB0, 8 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + FLD0, 64 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + FLD1, 128 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + FLD2, 192 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + FLD3, 256 + } + + Mutex (MUT0, 0x00) + Mutex (MUT1, 0x00) + Mutex (MUT2, 0x00) + Method (SMRD, 4, NotSerialized) + { + If (!ECOK) + { + Return (0xFF) + } + + If ((Arg0 != 0x07)) + { + If ((Arg0 != 0x09)) + { + If ((Arg0 != 0x0B)) + { + If ((Arg0 != 0x47)) + { + If ((Arg0 != 0xC7)) + { + Return (0x19) + } + } + } + } + } + + Acquire (MUT0, 0xFFFF) + Local0 = 0x04 + While ((Local0 > One)) + { + SMST &= 0x40 + SMCM = Arg2 + SMAD = Arg1 + SMPR = Arg0 + Local3 = Zero + While (!Local1 = (SMST & 0xBF)) + { + Sleep (0x02) + Local3++ + If ((Local3 == 0x32)) + { + SMST &= 0x40 + SMCM = Arg2 + SMAD = Arg1 + SMPR = Arg0 + Local3 = Zero + } + } + + If ((Local1 == 0x80)) + { + Local0 = Zero + } + Else + { + Local0-- + } + } + + If (Local0) + { + Local0 = (Local1 & 0x1F) + } + Else + { + If ((Arg0 == 0x07)) + { + Arg3 = SMB0 /* \_SB_.PCI0.LPCB.EC0_.SMB0 */ + } + + If ((Arg0 == 0x47)) + { + Arg3 = SMB0 /* \_SB_.PCI0.LPCB.EC0_.SMB0 */ + } + + If ((Arg0 == 0xC7)) + { + Arg3 = SMB0 /* \_SB_.PCI0.LPCB.EC0_.SMB0 */ + } + + If ((Arg0 == 0x09)) + { + Arg3 = SMW0 /* \_SB_.PCI0.LPCB.EC0_.SMW0 */ + } + + If ((Arg0 == 0x0B)) + { + Local3 = BCNT /* \_SB_.PCI0.LPCB.EC0_.BCNT */ + Local2 = 0x20 + If ((Local3 > Local2)) + { + Local3 = Local2 + } + + If ((Local3 < 0x11)) + { + Local2 = FLD1 /* \_SB_.PCI0.LPCB.EC0_.FLD1 */ + } + ElseIf ((Local3 < 0x19)) + { + Local2 = FLD2 /* \_SB_.PCI0.LPCB.EC0_.FLD2 */ + } + Else + { + Local2 = FLD3 /* \_SB_.PCI0.LPCB.EC0_.FLD3 */ + } + + Local3++ + Local4 = Buffer (Local3){} + Local3-- + Local5 = Zero + Name (OEMS, Buffer (0x46){}) + ToBuffer (Local2, OEMS) /* \_SB_.PCI0.LPCB.EC0_.SMRD.OEMS */ + While ((Local3 > Local5)) + { + GBFE (OEMS, Local5, RefOf (Local6)) + PBFE (Local4, Local5, Local6) + Local5++ + } + + PBFE (Local4, Local5, Zero) + Arg3 = Local4 + } + } + + Release (MUT0) + Return (Local0) + } + + Method (SMWR, 4, NotSerialized) + { + If (!ECOK) + { + Return (0xFF) + } + + If ((Arg0 != 0x06)) + { + If ((Arg0 != 0x08)) + { + If ((Arg0 != 0x0A)) + { + If ((Arg0 != 0x46)) + { + If ((Arg0 != 0xC6)) + { + Return (0x19) + } + } + } + } + } + + Acquire (MUT0, 0xFFFF) + Local0 = 0x04 + While ((Local0 > One)) + { + If ((Arg0 == 0x06)) + { + SMB0 = Arg3 + } + + If ((Arg0 == 0x46)) + { + SMB0 = Arg3 + } + + If ((Arg0 == 0xC6)) + { + SMB0 = Arg3 + } + + If ((Arg0 == 0x08)) + { + SMW0 = Arg3 + } + + If ((Arg0 == 0x0A)) + { + SMD0 = Arg3 + } + + SMST &= 0x40 + SMCM = Arg2 + SMAD = Arg1 + SMPR = Arg0 + Local3 = Zero + While (!Local1 = (SMST & 0xBF)) + { + Sleep (0x02) + Local3++ + If ((Local3 == 0x32)) + { + SMST &= 0x40 + SMCM = Arg2 + SMAD = Arg1 + SMPR = Arg0 + Local3 = Zero + } + } + + If ((Local1 == 0x80)) + { + Local0 = Zero + } + Else + { + Local0-- + } + } + + If (Local0) + { + Local0 = (Local1 & 0x1F) + } + + Release (MUT0) + Return (Local0) + } + + Method (GSHK, 0, Serialized) + { + If ((ECOK == One)) + { + Local0 = SFHK /* \_SB_.PCI0.LPCB.EC0_.SFHK */ + } + + Return (Local0) + } + + Method (SSHK, 1, Serialized) + { + If ((ECOK == One)) + { + SFHK = Arg0 + } + } + + Method (CPUS, 1, NotSerialized) + { + If (CondRefOf (\_PR.PR00._PPC)) + { + \_PR.CPPC = Arg0 + } + + If ((TCNT == 0x08)) + { + Notify (\_PR.PR00, 0x80) // Performance Capability Change + Notify (\_PR.PR01, 0x80) // Performance Capability Change + Notify (\_PR.PR02, 0x80) // Performance Capability Change + Notify (\_PR.PR03, 0x80) // Performance Capability Change + Notify (\_PR.PR04, 0x80) // Performance Capability Change + Notify (\_PR.PR05, 0x80) // Performance Capability Change + Notify (\_PR.PR06, 0x80) // Performance Capability Change + Notify (\_PR.PR07, 0x80) // Performance Capability Change + } + + If ((TCNT == 0x04)) + { + Notify (\_PR.PR00, 0x80) // Performance Capability Change + Notify (\_PR.PR01, 0x80) // Performance Capability Change + Notify (\_PR.PR02, 0x80) // Performance Capability Change + Notify (\_PR.PR03, 0x80) // Performance Capability Change + } + + If ((TCNT == 0x02)) + { + Notify (\_PR.PR00, 0x80) // Performance Capability Change + Notify (\_PR.PR01, 0x80) // Performance Capability Change + } + Else + { + Notify (\_PR.PR00, 0x80) // Performance Capability Change + } + } + + Method (ECMI, 0, NotSerialized) + { + If ((ECOK == One)) + { + OSTD () + CLOW = Zero + CMAX = (MPPP - One) + ACKY = FNKY /* \FNKY */ + SASU () + If ((SMA4 == One)) + { + SMSZ = Zero + } + Else + { + SMSZ = One + } + + ULID (Zero) + } + } + + Method (SASU, 0, NotSerialized) + { + If ((ECOK == One)) + { + If (CondRefOf (\_PR.PR00._PPC)) + { + Local0 = \_PR.PR00._PPC () + } + + Local1 = (MPPP - One) + If (((SW2S == Zero) || ((SADP >= One) & ( + SADP <= 0x02)))) + { + Local0 = Zero + CPUS (Local0) + CLOW = Local0 + } + + If ((SADP == 0x03)) + { + If ((Local0 < Local1)) + { + Local0++ + CPUS (Local0) + CLOW = Local0 + } + } + } + } + + Method (RPIO, 2, NotSerialized) + { + Local0 = Zero + If ((ECOK == One)) + { + EI01 = Arg0 + EI02 = Arg1 + Local0 = EI03 /* \EI03 */ + } + + Return (Local0) + } + + Method (WPIO, 3, NotSerialized) + { + If ((ECOK == One)) + { + EI01 = Arg0 + EI02 = Arg1 + EI03 = Arg2 + } + } + + Method (ECMD, 3, NotSerialized) + { + If ((ECOK == One)) + { + WPIO (Arg0, Arg1, Arg2) + While (EI03) + { + Stall (0xFF) + } + + Local0 = RPIO (0xFB, Zero) + Return (Local0) + } + } + + Method (CBCD, 0, NotSerialized) + { + If ((ECOK == One)) + { + Local0 = MBDC /* \_SB_.PCI0.LPCB.EC0_.MBDC */ + Local0 &= 0xE4 + MBDC = Local0 + } + } + + Method (ULID, 1, NotSerialized) + { + If ((ECOK == One)) + { + If ((ECLS == One)) + { + Local0 = Zero + } + Else + { + Local0 = One + } + + If (IGDS) + { + If ((Arg0 == One)) + { + If ((Local0 != LIDS)) + { + If (^^^GFX0.GLID (Local0)) + { + If ((LIDS == Zero)) + { + ^^^GFX0.CLID |= 0x80000000 /* External reference */ + } + + If ((LIDS == One)) + { + ^^^GFX0.CLID |= 0x80000001 /* External reference */ + } + } + } + } + } + + LIDS = Local0 + } + } + + Method (OSTD, 0, NotSerialized) + { + If ((ECOK == One)) + { + W7OS = Zero + SUSE = Zero + RFLG = Zero + If ((OSYS >= 0x07D0)) + { + If ((OSYS >= 0x07D9)) + { + W7OS = One + If ((OSKU == Zero)) + { + W7OS = Zero + } + } + } + Else + { + If ((OSYS == 0x03E8)) + { + RFLG = One + } + + If ((OSYS == 0x03E9)) + { + SUSE = One + } + } + } + Else + { + W7OS = Zero + SUSE = Zero + RFLG = Zero + } + } + + +#include "ac.asl" +#include "battery.asl" +#include "kb.asl" +#include "tpm.asl" +} diff --git a/src/ec/hp/it8987e/acpi/kb.asl b/src/ec/hp/it8987e/acpi/kb.asl new file mode 100644 index 0000000..bc42897 --- /dev/null +++ b/src/ec/hp/it8987e/acpi/kb.asl @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is \_SB.PCI0.LPCB + +Device (PS2K) +{ + Name (_CID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _CID: Compatible ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQ (Edge, ActiveHigh, Exclusive, ) + {1} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + FixedIO ( + 0x0060, // Address + 0x01, // Length + ) + FixedIO ( + 0x0064, // Address + 0x01, // Length + ) + IRQNoFlags () + {1} + } + EndDependentFn () + }) + + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + If (One) + { + Return (Package (0x02) + { + 0x3D, + 0x03 + }) + } + Else + { + Return (Package (0x02) + { + 0x1F, + 0x03 + }) + } + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + KBWK = Arg0 + } +} + +Device (PS2M) +{ + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + If ((CHID == 0x25)) + { + Return ("*SYN326A") + } + Else + { + Return ("*SYN326A") + } + } + + Method (_CID, 0, NotSerialized) // _CID: Compatible ID + { + Return (Package (0x03) + { + 0x001E2E4F, + 0x02002E4F, + 0x130FD041 + }) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQ (Edge, ActiveHigh, Exclusive, ) + {12} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + IRQNoFlags () + {12} + } + EndDependentFn () + }) + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + If (One) + { + Return (Package (0x02) + { + 0x3D, + 0x03 + }) + } + Else + { + Return (Package (0x02) + { + 0x1F, + 0x03 + }) + } + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + TPWK = Arg0 + } +} diff --git a/src/ec/hp/it8987e/acpi/superio.asl b/src/ec/hp/it8987e/acpi/superio.asl new file mode 100644 index 0000000..e912e04 --- /dev/null +++ b/src/ec/hp/it8987e/acpi/superio.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) +{ + Name (_HID, EisaId("PNP0A05")) + Name (_UID, 0) + Name (_ADR, 0) + +#ifdef SIO_EC_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_UID, 0) + Name (_ADR, 0) + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + } + EndDependentFn () + }) + } +#endif + +#ifdef SIO_ENABLE_PS2M + Device (PS2M) // Mouse + { + Name (_HID, EISAID("PNP0F13")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + } + EndDependentFn () + }) + } +#endif + +} diff --git a/src/ec/hp/it8987e/acpi/tpm.asl b/src/ec/hp/it8987e/acpi/tpm.asl new file mode 100644 index 0000000..d24d05f --- /dev/null +++ b/src/ec/hp/it8987e/acpi/tpm.asl @@ -0,0 +1,446 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (_SB.TPM) +{ + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + If (TCMF) + { + Return (0x01013469) + } + ElseIf ((TTDP == Zero)) + { + Return (0x310CD041) + } + Else + { + Return ("MSFT0101") + } + } + + Method (_STR, 0, NotSerialized) // _STR: Description String + { + If ((TTDP == Zero)) + { + Return (Unicode ("TPM 1.2 Device")) + } + Else + { + Return (Unicode ("TPM 2.0 Device")) + } + } + + Name (_UID, One) // _UID: Unique ID + Name (CRST, ResourceTemplate () + { + Memory32Fixed (ReadOnly, + 0x00000000, // Address Base + 0x00001000, // Address Length + _Y31) + Memory32Fixed (ReadOnly, + 0xFED70000, // Address Base + 0x00001000, // Address Length + _Y32) + }) + Name (CRSD, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + _Y33) + }) + Name (CRSI, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + _Y34) + }) + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + If ((AMDT == One)) + { + CreateDWordField (CRST, \_SB.TPM._Y31._BAS, MTFB) // _BAS: Base Address + CreateDWordField (CRST, \_SB.TPM._Y31._LEN, LTFB) // _LEN: Length + MTFB = TPMB /* \TPMB */ + LTFB = 0x1000 + CreateDWordField (CRST, \_SB.TPM._Y32._BAS, MTFC) // _BAS: Base Address + CreateDWordField (CRST, \_SB.TPM._Y32._LEN, LTFC) // _LEN: Length + MTFC = TPMC /* \TPMC */ + LTFC = 0x1000 + Return (CRST) /* \_SB_.TPM_.CRST */ + } + Else + { + If ((DTPT == One)) + { + CreateDWordField (CRSD, \_SB.TPM._Y33._BAS, MTFE) // _BAS: Base Address + CreateDWordField (CRSD, \_SB.TPM._Y33._LEN, LTFE) // _LEN: Length + MTFE = 0xFED40000 + LTFE = 0x0880 + Return (CRSD) /* \_SB_.TPM_.CRSD */ + } + ElseIf ((TTPF == One)) + { + CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFD) // _BAS: Base Address + CreateDWordField (CRSI, \_SB.TPM._Y34._LEN, LTFD) // _LEN: Length + MTFD = 0xFED40000 + LTFD = 0x5000 + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + ElseIf ((TTPF == Zero)) + { + CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFF) // _BAS: Base Address + MTFF = TPMM /* \TPMM */ + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + MTFE = Zero + LTFE = Zero + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + OperationRegion (TMMB, SystemMemory, 0xFED40000, 0x5000) + Field (TMMB, ByteAcc, Lock, Preserve) + { + Offset (0x04), + LCST, 32, + Offset (0x40), + CREQ, 32, + CSTS, 32, + Offset (0x4C), + SCMD, 32 + } + + OperationRegion (CRBD, SystemMemory, TPMM, 0x48) + Field (CRBD, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + HERR, 32, + Offset (0x40), + HCMD, 32, + HSTS, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((TTDP == Zero)) + { + If (TPMF) + { + Return (0x0F) + } + + Return (Zero) + } + ElseIf ((TTDP == One)) + { + If (TPMF) + { + Return (0x0F) + } + + Return (Zero) + } + + Return (Zero) + } + + Method (STRT, 3, Serialized) + { + OperationRegion (TPMR, SystemMemory, FTPM, 0x1000) + Field (TPMR, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + FERR, 32, + Offset (0x0C), + BEGN, 32 + } + + Name (TIMR, Zero) + If ((ToInteger (Arg0) != Zero)){} + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + TIMR = Zero + If ((AMDT == One)) + { + While (((BEGN == One) && (TIMR < 0x0200))) + { + If ((BEGN == One)) + { + Sleep (One) + TIMR++ + } + } + } + ElseIf ((((HSTS & 0x02) | (HSTS & One) + ) == 0x03)) + { + HCMD = One + } + Else + { + FERR = One + BEGN = Zero + } + + Return (Zero) + } + + } + + Return (One) + } + + Method (CRYF, 3, Serialized) + { + If ((ToInteger (Arg0) != One)){} + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + Name (TPMV, Package (0x02) + { + One, + Package (0x02) + { + One, + 0x20 + } + }) + If ((_STA () == Zero)) + { + Return (Package (0x01) + { + Zero + }) + } + + Return (TPMV) /* \_SB_.TPM_.CRYF.TPMV */ + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + } +} + + + +Scope (_SB.TPM) +{ + OperationRegion (TSMI, SystemIO, SMIA, 0x02) + Field (TSMI, WordAcc, NoLock, Preserve) + { + SMI, 16 + } + + OperationRegion (ATNV, SystemMemory, PPIM, PPIL) + Field (ATNV, AnyAcc, NoLock, Preserve) + { + RQST, 32, + RCNT, 32, + ERRO, 32, + FLAG, 32, + MISC, 32, + OPTN, 32, + SRSP, 32 + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */)) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (0x02) + { + 0xFF, 0x01 // .. + }) + } + Case (One) + { + If ((PPIV == Zero)) + { + Return ("1.2") + } + Else + { + Return ("1.3") + } + } + Case (0x02) + { + RQST = DerefOf (Arg3 [Zero]) + SRSP = Zero + FLAG = 0x02 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Case (0x03) + { + Name (PPI1, Package (0x02) + { + Zero, + Zero + }) + PPI1 [One] = RQST /* \_SB_.TPM_.RQST */ + Return (PPI1) /* \_SB_.TPM_._DSM.PPI1 */ + } + Case (0x04) + { + Return (TRST) /* \TRST */ + } + Case (0x05) + { + Name (PPI2, Package (0x03) + { + Zero, + Zero, + Zero + }) + SRSP = Zero + FLAG = 0x05 + SMI = OFST /* \OFST */ + PPI2 [One] = RCNT /* \_SB_.TPM_.RCNT */ + PPI2 [0x02] = ERRO /* \_SB_.TPM_.ERRO */ + Return (PPI2) /* \_SB_.TPM_._DSM.PPI2 */ + } + Case (0x06) + { + Return (0x03) + } + Case (0x07) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x07 + OPTN = Zero + If ((RQST == 0x17)) + { + ToInteger (DerefOf (Arg3 [One]), OPTN) /* \_SB_.TPM_.OPTN */ + } + + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Case (0x08) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x08 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Default + { + } + + } + } + ElseIf ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d"))) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x09 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Default + { + } + + } + } + + If ((Arg0 == ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8"))) + { + Return (CRYF (Arg1, Arg2, Arg3)) + } + + If ((Arg0 == ToUUID ("6bbf6cab-5463-4714-b7cd-f0203c0368d4"))) + { + Return (STRT (Arg1, Arg2, Arg3)) + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Method (TPTS, 1, Serialized) + { + Switch (ToInteger (Arg0)) + { + Case (0x04) + { + RQST = Zero + FLAG = 0x09 + SRSP = Zero + SMI = OFST /* \OFST */ + } + Case (0x05) + { + RQST = Zero + FLAG = 0x09 + SRSP = Zero + SMI = OFST /* \OFST */ + } + + } + } +} diff --git a/src/ec/hp/it8987e/chip.h b/src/ec/hp/it8987e/chip.h new file mode 100644 index 0000000..1bc9949 --- /dev/null +++ b/src/ec/hp/it8987e/chip.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _EC_HP_IT8987E_CHIP_H +#define _EC_HP_IT8987E_CHIP_H + +#include <device/device.h> + +struct chip_operations; +extern struct chip_operations ec_quanta_it8987e_ops; + +struct ec_quanta_it8987e_config { +}; + +#endif /* _EC_HP_IT8987E_CHIP_H */ diff --git a/src/ec/hp/it8987e/ec.c b/src/ec/hp/it8987e/ec.c new file mode 100644 index 0000000..db6fe3c --- /dev/null +++ b/src/ec/hp/it8987e/ec.c @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> + +#include "ec.h" +#include "chip.h" + +/* helper functions from drivers/pc80/keyboard.c */ +static int input_buffer_empty(u16 status_reg) +{ + u32 timeout; + for (timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(status_reg) & KBD_IBF); + timeout--) { + udelay(1000); + } + + if (!timeout) { + printk(BIOS_WARNING, "EC-IT8987E Unexpected input buffer full\n"); + printk(BIOS_WARNING, " Status (0x%x): 0x%x\n", status_reg, inb(status_reg)); + } + return !!timeout; +} + + +static int output_buffer_full(u16 status_reg) +{ + u32 timeout; + for (timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(status_reg) + & KBD_OBF) == 0); timeout--) { + udelay(1000); + } + + if (!timeout) { + printk(BIOS_INFO, "EC-IT8987E output buffer result timeout\n"); + printk(BIOS_INFO, " Status (0x%x): 0x%x\n", status_reg, inb(status_reg)); + } + return !!timeout; +} + + + +/* The IT8987E 60/64 EC registers are the same command/status IB/OB KBC pair. + * Check status from 64 port before each command. + * + * Ex. Get panel ID command C43/D77 + * Check IBF empty. Then Write 0x43(CMD) to 0x64 Port + * Check IBF empty. Then Write 0x77(DATA) to 0x60 Port + * Check OBF set. Then Get Data(0x03:panel ID) from 0x60 + * Different commands return may or may not respond and may have multiple + * bytes. Keep it simple for nor + */ + +u8 ec_kbc_read_ob(void) +{ + if (!output_buffer_full(KBD_STATUS)) return 0; + return inb(KBD_DATA); +} + +void ec_kbc_write_cmd(u8 cmd) +{ + if (!input_buffer_empty(KBD_STATUS)) return; + outb(cmd, KBD_COMMAND); +} + +void ec_kbc_write_ib(u8 data) +{ + if (!input_buffer_empty(KBD_STATUS)) return; + outb(data, KBD_DATA); +} + + +/* + * These functions are for accessing the IT8987E device RAM space via 0x66/0x68 + */ + +u8 ec_read_ob(void) +{ + if (!output_buffer_full(EC_SC)) return 0; + return inb(EC_DATA); +} + +void ec_write_cmd(u8 cmd) +{ + if (!input_buffer_empty(EC_SC)) return; + outb(cmd, EC_SC); +} + +void ec_write_ib(u8 data) +{ + if (!input_buffer_empty(EC_SC)) return; + outb(data, EC_DATA); +} + +u8 ec_read(u16 addr) +{ + ec_write_cmd(RD_EC); + ec_write_ib(addr); + return ec_read_ob(); +} + +void ec_write(u16 addr, u8 data) +{ + ec_write_cmd(WR_EC); + ec_write_ib(addr); + ec_write_ib(data); +} + +#ifndef __PRE_RAM__ + +u8 ec_it8987e_get_event(void) +{ + u8 cmd = 0; + u8 status = inb(EC_SC); + if (status & SCI_EVT) { + ec_write_cmd(QR_EC); + cmd = ec_read_ob(); + } else if (status & SMI_EVT) { + ec_kbc_write_cmd(EC_KBD_SMI_EVENT); + cmd = ec_kbc_read_ob(); + } + return cmd; +} + +void ec_it8987e_enable_wake_events(void) +{ + /* + * Set the bit in ECRAM that will enable the Lid switch as a wake source + */ + u8 reg8 = ec_read(EC_WAKE_SRC_ENABLE); + ec_write(EC_WAKE_SRC_ENABLE, reg8 | EC_LID_WAKE_ENABLE); +} + +#ifndef __SMM__ +static void it8987e_init(struct device *dev) +{ + if (!dev->enabled) + return; + + printk(BIOS_DEBUG, "Quanta IT8987E: Initializing keyboard.\n"); + pc_keyboard_init(NO_AUX_DEVICE); +} + +static struct device_operations ops = { + .init = it8987e_init, + .read_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, 0, 0, 0, } +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations ec_quanta_it8987e_ops = { + CHIP_NAME("QUANTA IT8987E EC") + .enable_dev = enable_dev +}; +#endif /* ! __SMM__ */ +#endif /* ! __PRE_RAM__ */ diff --git a/src/ec/hp/it8987e/ec.h b/src/ec/hp/it8987e/ec.h new file mode 100644 index 0000000..f87b2c0 --- /dev/null +++ b/src/ec/hp/it8987e/ec.h @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Modified by Matt Parnell <mparnell(a)gmail.com> to support ITL 8987E + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * EC communication interface for QUANTA IT8987E Embedded Controller. + */ + +#ifndef _EC_HP_IT8987E_EC_H +#define _EC_HP_IT8987E_EC_H + +#define EC_IO 0x100 /* Mainboard specific. Could be Kconfig option */ +#define EC_IO_HIGH EC_IO + 1 +#define EC_IO_LOW EC_IO + 2 +#define EC_IO_DATA EC_IO + 3 + +/* Wait 400ms for keyboard controller ansswers */ +#define KBC_TIMEOUT_IN_MS 400 + +// 60h/64h Command Interface +#define KBD_DATA 0x60 +#define KBD_COMMAND 0x64 +#define KBD_STATUS 0x64 +#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) + +#define EC_KBD_SMI_EVENT 0xCD +#define EC_KBD_CMD_UNMUTE 0xE8 +#define EC_KBD_CMD_MUTE 0xE9 + +u8 ec_kbc_read_ob(void); +void ec_kbc_write_cmd(u8 cmd); +void ec_kbc_write_ib(u8 data); + +// 62h/66h Command Interface +#define EC_DATA 0x62 +#define EC_SC 0x66 // Status & Control Register +#define SMI_EVT (1 << 6) // 1: SMI event was triggered +#define SCI_EVT (1 << 5) // 1: SCI event was triggered + +// EC Commands (defined in ec_function_spec v3.12) +#define RD_EC 0x80 +#define WR_EC 0x81 +#define QR_EC 0x84 + +#define EC_CMD_EXIT_BOOT_BLOCK 0x85 +#define EC_CMD_NOTIFY_ACPI_ENTER 0x86 +#define EC_CMD_NOTIFY_ACPI_EXIT 0x87 +#define EC_CMD_WARM_RESET 0x8C + +// ECRAM Offsets +#define EC_PERIPH_CNTL_3 0x0D +#define EC_USB_S3_EN 0x26 +#define EC_PERIPH_STAT_3 0x35 +#define EC_THERM_0 0x78 +#define EC_WAKE_SRC_ENABLE 0xBF +#define EC_FW_VER 0xE8 // 2 Bytes +#define EC_IF_MIN_VER 0xEB +#define EC_STATUS_REG 0xEC +#define EC_IF_MAJ_VER 0xEF +#define EC_MBAT_STATUS 0x0138 + + +// EC 0.83b added status bits: +// BIT0=EC in RO mode +// BIT1=Recovery Key Sequence Detected +#define EC_IN_RO_MODE 0x1 +#define EC_IN_RECOVERY_MODE 0x3 + +// EC 0.86a added enable bit: +#define EC_LID_WAKE_ENABLE 0x4 + +u8 ec_read_ob(void); +void ec_write_cmd(u8 cmd); +void ec_write_ib(u8 data); + +u8 ec_read(u16 addr); +void ec_write(u16 addr, u8 data); +u8 ec_it8987e_get_event(void); +void ec_it8987e_enable_wake_events(void); + +#endif /* _EC_HP_IT8987E_EC_H */ diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig new file mode 100644 index 0000000..00542d7 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig @@ -0,0 +1,59 @@ +config BOARD_HP_SPECTRE_AE000 + select SYSTEM_TYPE_LAPTOP + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select SOC_INTEL_KABYLAKE + select MAINBOARD_USES_FSP2_0 + select SPD_READ_BY_WORD + select MAINBOARD_HAS_LPC_TPM + select NO_POST # This platform does not have any way to see POST codes + +if BOARD_HP_SPECTRE_AE000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_VENDOR + string + default "HP" + +config MAINBOARD_FAMILY + string + default "HP Spectre x360" + +config MAINBOARD_PART_NUMBER + string + default "13t-ae000" + +config MAINBOARD_DIR + string + default "hp/hp_spectre_x360_13_convertible" + +config DEVICETREE + string + default "devicetree.cb" + +config FMDFILE + string + default "" + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_ID + string + default "8086,0406" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +endif diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name new file mode 100644 index 0000000..9f089a5 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_SPECTRE_AE000 + bool "Spectre x360 13t-ae000" diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc b/src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc new file mode 100644 index 0000000..35f0f6c --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += ramstage.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl new file mode 100644 index 0000000..489bdcd --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope (EC0) + +Device (ADP1) +{ + Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + Local0 = \_SB_.PCI0.LPCB.EC0.SW2S + } + Else + { + Local0 = 1 + } + + Return (Local0) + } + + Method (_PCL, 0, NotSerialized) // _PCL: Power Consumer List + { + Return (_SB) /* \_SB_ */ + } +} + +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D") /* Lid Device */) // _HID: Hardware ID + Method (_LID, 0, NotSerialized) // _LID: Lid Status + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If ((\_SB_.PCI0.LPCB.EC0.ECLS == 1)) + { + Local0 = 0 + } + Else + { + Local0 = 1 + } + } + Else + { + Local0 = 1 + } + + /* \_SB_.PCI0.LPCB.EC0.ULID (1) */ + Return (Local0) + } +} + +Device (PWRB) +{ + Name (_HID, EisaId ("PNP0C0C") /* Power Button Device */) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl new file mode 100644 index 0000000..94ce92c --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl @@ -0,0 +1,252 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2013 Google Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; version 2 of +* the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +Device (BAT0) +{ + Name (FRST, 1) + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, 1) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (PBIF, Package (0x0D) + { + 1, + 0xFFFFFFFF, + 0xFFFFFFFF, + 1, + 0xFFFFFFFF, + 0xFA, + 0x96, + 0x0A, + 0x19, + "BAT0", + " ", + " ", + " " + }) + Name (PBST, Package (0x04) + { + 0, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0x2710 + }) + Name (BAST, 0) + Name (B1ST, 0x0F) + Name (B1WT, 0) + Name (FABL, 0xFFFFFFFF) + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If (\_SB_.PCI0.LPCB.EC0.MBTS) + { + B1ST = 0x1F + } + Else + { + B1ST = 0x0F + } + } + Else + { + B1ST = 0x0F + } + + Return (B1ST) /* \_SB_.BAT0.B1ST */ + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If (\_SB_.PCI0.LPCB.EC0.MBTS) + { + UPBI () + } + Else + { + IVBI () + } + } + Else + { + IVBI () + } + + Return (PBIF) /* \_SB_.BAT0.PBIF */ + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If (\_SB_.PCI0.LPCB.EC0.MBTS) + { + UPBS () + } + Else + { + IVBS () + } + } + Else + { + IVBS () + } + + Return (PBST) /* \_SB_.BAT0.PBST */ + } + + Method (UPBI, 0, NotSerialized) + { + Local5 = \_SB_.PCI0.LPCB.EC0.BFCC /* \_SB_.PCI0.LPCB.EC0_.BFCC */ + If ((Local5 && !(Local5 & 0x8000))) + { + Local5 >>= 0x05 + Local5 <<= 0x05 + PBIF [1] = Local5 + PBIF [0x02] = Local5 + Local2 = (Local5 / 0x64) + Local2 += 1 + If ((\_SB_.PCI0.LPCB.EC0.BADC < 0x0C80)) + { + Local4 = (Local2 * 0x0E) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x09) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x0B) + } + ElseIf ((SMA4 == 1)) + { + Local4 = (Local2 * 0x0A) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x05) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x08) + } + Else + { + Local4 = (Local2 * 0x0C) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x07) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x0A) + } + + FABL = (Local4 + 0x02) + } + + Local0 = \_SB_.PCI0.LPCB.EC0.BVLB /* \_SB_.PCI0.LPCB.EC0_.BVLB */ + Local1 = \_SB_.PCI0.LPCB.EC0.BVHB /* \_SB_.PCI0.LPCB.EC0_.BVHB */ + Local1 <<= 0x08 + Local0 |= Local1 + PBIF [0x04] = Local0 + Sleep (0x32) + PBIF [0x0B] = "LION" + PBIF [0x09] = "Primary" + UPUM () + PBIF [0] = 1 + } + + Method (UPUM, 0, NotSerialized) + { + Local0 = Buffer (0x0A) + { + /* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00 // .. + } + Local6 = Buffer (0x05) + { + 0x36, 0x35, 0x35, 0x33, 0x35 // 65535 + } + Local7 = Buffer (0x05) + { + 0x31, 0x32, 0x33, 0x32, 0x31 // 12321 + } + PBIF [0x0C] = "HP" + } + + Method (UPBS, 0, NotSerialized) + { + If ((BRTM == 1)) + { + Local0 = \_SB_.PCI0.LPCB.EC0.MCUR /* \_SB_.PCI0.LPCB.EC0_.MCUR */ + If ((Local0 & 0x8000)) + { + If ((Local0 == 0xFFFF)) + { + PBST [1] = 0xFFFFFFFF + } + Else + { + Local1 = ~Local0 + Local1++ + Local3 = (Local1 & 0xFFFF) + PBST [1] = Local3 + } + } + Else + { + PBST [1] = Local0 + } + } + Else + { + PBST [1] = 0xFFFFFFFF + } + + Local5 = \_SB_.PCI0.LPCB.EC0.MBRM /* \_SB_.PCI0.LPCB.EC0_.MBRM */ + If (!(Local5 & 0x8000)) + { + Local5 >>= 0x05 + Local5 <<= 0x05 + If ((Local5 != DerefOf (PBST [0x02]))) + { + PBST [0x02] = Local5 + } + } + + If ((!\_SB_.PCI0.LPCB.EC0.SW2S && (\_SB_.PCI0.LPCB.EC0.BACR == 1))) + { + PBST [0x02] = FABL /* \_SB_.BAT0.FABL */ + } + + PBST [0x03] = \_SB_.PCI0.LPCB.EC0.MBCV /* \_SB_.PCI0.LPCB.EC0_.MBCV */ + PBST [0] = \_SB_.PCI0.LPCB.EC0.MBST /* \_SB_.PCI0.LPCB.EC0_.MBST */ + } + + Method (IVBI, 0, NotSerialized) + { + PBIF [1] = 0xFFFFFFFF + PBIF [0x02] = 0xFFFFFFFF + PBIF [0x04] = 0xFFFFFFFF + PBIF [0x09] = "Bad" + PBIF [0x0A] = "Bad" + PBIF [0x0B] = "Bad" + PBIF [0x0C] = "Bad" + } + + Method (IVBS, 0, NotSerialized) + { + PBST [0] = 0 + PBST [1] = 0xFFFFFFFF + PBST [0x02] = 0xFFFFFFFF + PBST [0x03] = 0x2710 + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl new file mode 100644 index 0000000..a417560 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl @@ -0,0 +1,393 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID + Name (_UID, 1) // _UID: Unique ID + Name (_GPE, 0x17) + Name (PHOT, 1) + + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + OperationRegion (ERAM, EmbeddedControl, 0, 0xFF) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + SMPR, 8, + SMST, 8, + SMAD, 8, + SMCM, 8, + SMD0, 256, + BCNT, 8, + SMAA, 8, + Offset (0x40), + SW2S, 1, + , 2, + ACCC, 1, + TRPM, 1, + Offset (0x41), + W7OS, 1, + QWOS, 1, + , 1, + SUSE, 1, + RFLG, 1, + Offset (0x43), + , 1, + , 1, + ACPS, 1, + ACKY, 1, + GFXT, 1, + Offset (0x44), + , 7, + DSMB, 1, + Offset (0x47), + TNT2, 8, + TNT3, 8, + Offset (0x4C), + STRM, 8, + Offset (0x4E), + LIDE, 1, + Offset (0x4F), + ACID, 8, + , 2, + PTHM, 1, + , 1, + BSEV, 1, + DPTL, 1, + Offset (0x52), + ECLS, 1, + Offset (0x55), + EC45, 8, + Offset (0x58), + RTMP, 8, + TNT1, 8, + Offset (0x5F), + , 1, + Offset (0x61), + SHPM, 8, + Offset (0x67), + , 1, + , 1, + GC6R, 1, + IGC6, 1, + , 2, + PVSE, 1, + PVSS, 1, + , 3, + PLGS, 1, + , 3, + TPDF, 1, + , 4, + BCTF, 1, + BMNF, 1, + BTVD, 1, + BF10, 1, + Offset (0x6C), + GWKR, 8, + Offset (0x70), + BADC, 16, + BFCC, 16, + BVLB, 8, + BVHB, 8, + BDVO, 8, + Offset (0x7F), + ECTB, 1, + Offset (0x82), + MBST, 8, + MCUR, 16, + MBRM, 16, + MBCV, 16, + Offset (0x8B), + LEDM, 3, + Offset (0x8D), + , 5, + MBFC, 1, + Offset (0x92), + SPSV, 8, + Offset (0x94), + GSSU, 1, + GSMS, 1, + Offset (0x95), + MMST, 4, + DMST, 4, + Offset (0xA0), + QBHK, 8, + Offset (0xA2), + QBBB, 8, + Offset (0xA4), + MBTS, 1, + , 6, + BACR, 1, + Offset (0xA6), + MBDC, 8, + Offset (0xA8), + ENWD, 1, + TMPR, 1, + Offset (0xAA), + , 1, + SMSZ, 1, + , 5, + RCDS, 1, + Offset (0xAD), + SADP, 8, + Offset (0xB2), + RPM1, 8, + RPM2, 8, + Offset (0xBA), + CLOW, 8, + CMAX, 8, + Offset (0xC1), + DPPC, 8, + Offset (0xC6), + , 1, + CVTS, 1, + Offset (0xCE), + NVDX, 8, + ECDX, 8, + EBPL, 1, + Offset (0xD2), + , 7, + DLYE, 1, + Offset (0xD4), + PSHD, 8, + PSLD, 8, + DBPL, 8, + STSP, 8, + Offset (0xDA), + PSIN, 8, + PSKB, 1, + PSTP, 1, + , 1, + PWOL, 1, + RTCE, 1, + Offset (0xE0), + DLYT, 8, + DLY2, 8, + Offset (0xE6), + SFHK, 8, + Offset (0xE9), + DTMT, 8, + PL12, 8, + ETMT, 8, + Offset (0xF2), + ZPDD, 1, + , 6, + ENPA, 1, + Offset (0xF4), + SFAN, 8, + Offset (0xF9), + , 7, + FTHM, 1 + } + + Name (ECOK, 0) + Name (BATO, 0) + Name (BATN, 0) + Name (BATF, 0xC0) + Name (TMEE, 0) + Name (TMDE, 0) + + Method (BPOL, 1, NotSerialized) + { + DBPL = Arg0 + EBPL = 1 + } + + Method (BPOM, 0, NotSerialized) + { + DBPL = 0 + EBPL = 0 + } + + Method (GBAS, 0, NotSerialized) + { + If ((ECOK == 1)) + { + BATF = 0 + Local0 = MBTS /* \_SB_.PCI0.LPCB.EC0_.MBTS */ + Local1 = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */ + Local0 <<= 0x06 + Local1 <<= 1 + If (((BATO & 0x40) != Local0)) + { + BATF |= 0x40 + } + + If (((BATO & 0x02) != Local1)) + { + BATF |= 0x02 + } + + BATO = 0 + BATO = (Local0 | Local1) + } + } + + Method (_Q09, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + BPOM () + GBAS () + Notify (BAT0, 0x80) // Status Change + Notify (BAT0, 0x81) // Information Change + Notify (ADP1, 0x80) // Status Change + } + + Method (_Q0D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "_Q0D : Switch Display (Fn+F4)" + /*\_SB_.PCI0.GFX0.GHDS (0)*/ /*Todo: fixme? where is this guy defined? */ + Sleep (0xC8) + } + + Method (_Q20, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + GBAS () + If ((0x40 & BATF)) + { + Notify (BAT0, 0x81) // Information Change + } + + Notify (BAT0, 0x80) // Status Change + If ((0x02 & BATF)) + { + Notify (ADP1, 0x80) // Status Change + PWRS = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */ + } + + PNOT () + } + } + + Method (_Q22, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + BACR = 0 + Notify (BAT0, 0x80) // Status Change + } + } + + Method (_Q2A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + Notify (BAT0, 0x80) // Status Change + } + + Method (_Q33, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Local0 = ^^RTC.RTMN /* \_SB_.PCI0.LPCB.RTC_.RTMN */ + FromBCD (Local0, Local0) + Local1 = ^^RTC.RTHR /* \_SB_.PCI0.LPCB.RTC_.RTHR */ + FromBCD (Local1, Local1) + Local2 = ^^RTC.RTDY /* \_SB_.PCI0.LPCB.RTC_.RTDY */ + Local3 = ^^RTC.RTSE /* \_SB_.PCI0.LPCB.RTC_.RTSE */ + FromBCD (Local3, Local3) + If ((ECOK == 1)) + { + PSIN = 0xFF + Sleep (1) + PSLD = Local0 + PSHD = Local1 + PSIN = 0x1C + Sleep (1) + PSLD = Local2 + PSHD = Local3 + PSIN = 0x1D + } + } + + Method (_Q34, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + If ((ENWD == 1)) + { + TMPR = 1 + } + } + } + + Method (_Q46, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + If ((CVTS == 1)) + { + Local0 = 0x03 + Local0 <<= 0x10 + Local0 |= 0x03 + Notify (VBPA, 0xCC) // Hardware-Specific + } + + If ((CVTS == 0)) + { + Local0 = 0x02 + Local0 <<= 0x10 + Local0 |= 0x02 + Notify (VBPA, 0xCD) // Hardware-Specific + } + } + } + + /* _Q80 _Q82 _Q83 thermal zone methods removed */ + + Method (_Q84, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((PHOT == 1)) + { + PHOT = 0x02 + } + } + + Method (_Q85, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (B0D4, 0x90) // Device-Specific + } + + Method (_Q86, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((PHOT == 1)) + { + PHOT = 0x03 + } + } + + Method (_Q8A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + If (LIDE) + { + Debug = "_Q8A : LID Switch Event" + LIDE = 0 + Sleep (0x14) + Notify (LID0, 0x80) // Status Change + } + } + } + +/* TODO: revisit _Q8E _Q8F and wtf is _QE4 for? ? */ + +#include "ac.asl" +#include "battery.asl" +#include "kb.asl" +#include "mainboard.asl" +/*#include "tpm.asl"*/ +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl new file mode 100644 index 0000000..296cdba --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is \_SB.PCI0.LPCB + +Device (PS2K) +{ + Name (_CID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _CID: Compatible ID + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + If ((OSYS >= 0x07DC)) + { + Return ("HPQ8001") + } + Else + { + Return ("PNP0303") + } + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQ (Edge, ActiveHigh, Exclusive, ) + {1} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + FixedIO ( + 0x0060, // Address + 0x01, // Length + ) + FixedIO ( + 0x0064, // Address + 0x01, // Length + ) + IRQNoFlags () + {1} + } + EndDependentFn () + }) + + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + If (One) + { + Return (Package (0x02) + { + 0x3D, + 0x03 + }) + } + Else + { + Return (Package (0x02) + { + 0x1F, + 0x03 + }) + } + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + KBWK = Arg0 + } +} + +Device (PS2M) +{ + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + Return ("*SYN326A") + } + + Method (_CID, 0, NotSerialized) // _CID: Compatible ID + { + Return (Package (0x03) + { + 0x001E2E4F, + 0x02002E4F, + 0x130FD041 + }) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQ (Edge, ActiveHigh, Exclusive, ) + {12} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + IRQNoFlags () + {12} + } + EndDependentFn () + }) + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + If (One) + { + Return (Package (0x02) + { + 0x3D, + 0x03 + }) + } + Else + { + Return (Package (0x02) + { + 0x1F, + 0x03 + }) + } + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + TPWK = Arg0 + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl new file mode 100644 index 0000000..3c7189b --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl @@ -0,0 +1,282 @@ + /* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope (EC0) + +Device (RTC) +{ + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + + OperationRegion (CMS0, SystemCMOS, 0, 0x40) + Field (CMS0, ByteAcc, NoLock, Preserve) + { + RTSE, 8, + RTSA, 8, + RTMN, 8, + RTMA, 8, + RTHR, 8, + RTHA, 8, + RTDY, 8, + RTDE, 8 + } +} + +Scope (\_SB.PCI0.LPCB.RTC) +{ + OperationRegion (CMS0, SystemCMOS, 0, 0x40) + Field (CMS0, ByteAcc, NoLock, Preserve) + { + RTSE, 8, + RTSA, 8, + RTMN, 8, + RTMA, 8, + RTHR, 8, + RTHA, 8, + RTDY, 8, + RTDE, 8 + } +} + +Device (VBPA) +{ + Name (_HID, "INT33D6" /* Intel Virtual Buttons Device */) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((OSYS >= 0x07DD)) + { + Return (0x0F) + } + Else + { + Return (0) + } + } + + Name (VBST, 0) + Method (VBDL, 0, NotSerialized) + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If ((\_SB_.PCI0.LPCB.EC0.CVTS == 0)) + { + VBST = 0x40 + } + Else + { + VBST = 0 + } + } + } + + Method (VGBS, 0, NotSerialized) + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If ((\_SB_.PCI0.LPCB.EC0.CVTS == 0)) + { + VBST = 0x40 + } + Else + { + VBST = 0 + } + } + + Return (VBST) /* \_SB_.VBPA.VBST */ + } +} + +Device (CIND) +{ + Name (_HID, "INT33D3" /* Intel GPIO Buttons */) // _HID: Hardware ID + Name (_CID, "PNP0C60" /* Display Sensor Device */) // _CID: Compatible ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((OSYS >= 0x07DD)) + { + Return (0x0B) + } + Else + { + Return (0) + } + } +} + +Device (GFX0) +{ + Name (_ADR, 0x00020000) // _ADR: Address +} + +Device (B0D4) +{ +Method (PCIC, 1, Serialized) + { + If ((ECR1 == One)) + { + If ((Arg0 == PCIG)) + { + Return (One) + } + } + + Return (Zero) + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If (PCIC (Arg0)) + { + Return (PCID (Arg0, Arg1, Arg2, Arg3)) + } + + Return (Buffer (1) + { + 0x00 // . + }) + } + + Name (_ADR, 0x00040000) // _ADR: Address +} + +Device (ISP0) +{ + Name (_ADR, 0x00050000) // _ADR: Address +} + +Scope (\) +{ + Name (PCIG, ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */) + Name (KBWK, 0) + Name (TPWK, 0) + + Field (GNVS, AnyAcc, Lock, Preserve) + { + ECR1, 8 + } + + OperationRegion (EXBU, SystemMemory, 0x2F822018, 0x3008) + Field (EXBU, AnyAcc, Lock, Preserve) + { + AEAX, 32, + AEBX, 32, + AECX, 32, + AEDX, 32, + AREF, 32, + DAB0, 8, + DAB1, 8, + DAB2, 8, + DAB3, 8, + WBUF, 1024, + TJMX, 8, + FNKY, 8, + CAME, 8, + VTDT, 8, + DPMD, 8, + WLVD, 16, + WLDD, 16, + WLSV, 16, + WLSS, 16, + BTVD, 16, + BTDD, 16, + WWVD, 16, + WWDD, 16, + WMVD, 16, + WMDD, 16, + GPVD, 16, + GPDD, 16, + SMA4, 8, + PMEE, 8, + WSD0, 8, + WSD1, 8, + WSD2, 8, + WSD3, 8, + WAR7, 8, + DBCM, 8, + CPUP, 64, + GPUP, 32, + SYSP, 64, + FANP, 32, + BATP, 32, + HDDP, 32, + CPUT, 8, + GPUT, 8, + SYST, 8, + FANT, 8, + BATT, 8, + TTST, 8, + RTCF, 8, + BODD, 8, + BRTM, 8, + NOCD, 8, + PWVD, 16, + PWDD, 16, + PWSV, 16, + PWSS, 16, + Offset (0x400), + SBUF, 2048 + } + + Method (PCID, 4, Serialized) + { + If ((Arg0 == PCIG)) + { + If ((Arg1 >= 0x03)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (0x02) + { + 0x01, 0x03 // .. + }) + } + + If ((Arg2 == 0x08)) + { + Return (One) + } + + If ((Arg2 == 0x09)) + { + Return (Package (0x05) + { + 0xC350, + Ones, + Ones, + 0xC350, + Ones + }) + } + } + } + + Return (Buffer (One) + { + 0x00 // . + }) + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl new file mode 100644 index 0000000..e912e04 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) +{ + Name (_HID, EisaId("PNP0A05")) + Name (_UID, 0) + Name (_ADR, 0) + +#ifdef SIO_EC_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_UID, 0) + Name (_ADR, 0) + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + } + EndDependentFn () + }) + } +#endif + +#ifdef SIO_ENABLE_PS2M + Device (PS2M) // Mouse + { + Name (_HID, EISAID("PNP0F13")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + } + EndDependentFn () + }) + } +#endif + +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl new file mode 100644 index 0000000..d24d05f --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl @@ -0,0 +1,446 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (_SB.TPM) +{ + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + If (TCMF) + { + Return (0x01013469) + } + ElseIf ((TTDP == Zero)) + { + Return (0x310CD041) + } + Else + { + Return ("MSFT0101") + } + } + + Method (_STR, 0, NotSerialized) // _STR: Description String + { + If ((TTDP == Zero)) + { + Return (Unicode ("TPM 1.2 Device")) + } + Else + { + Return (Unicode ("TPM 2.0 Device")) + } + } + + Name (_UID, One) // _UID: Unique ID + Name (CRST, ResourceTemplate () + { + Memory32Fixed (ReadOnly, + 0x00000000, // Address Base + 0x00001000, // Address Length + _Y31) + Memory32Fixed (ReadOnly, + 0xFED70000, // Address Base + 0x00001000, // Address Length + _Y32) + }) + Name (CRSD, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + _Y33) + }) + Name (CRSI, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + _Y34) + }) + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + If ((AMDT == One)) + { + CreateDWordField (CRST, \_SB.TPM._Y31._BAS, MTFB) // _BAS: Base Address + CreateDWordField (CRST, \_SB.TPM._Y31._LEN, LTFB) // _LEN: Length + MTFB = TPMB /* \TPMB */ + LTFB = 0x1000 + CreateDWordField (CRST, \_SB.TPM._Y32._BAS, MTFC) // _BAS: Base Address + CreateDWordField (CRST, \_SB.TPM._Y32._LEN, LTFC) // _LEN: Length + MTFC = TPMC /* \TPMC */ + LTFC = 0x1000 + Return (CRST) /* \_SB_.TPM_.CRST */ + } + Else + { + If ((DTPT == One)) + { + CreateDWordField (CRSD, \_SB.TPM._Y33._BAS, MTFE) // _BAS: Base Address + CreateDWordField (CRSD, \_SB.TPM._Y33._LEN, LTFE) // _LEN: Length + MTFE = 0xFED40000 + LTFE = 0x0880 + Return (CRSD) /* \_SB_.TPM_.CRSD */ + } + ElseIf ((TTPF == One)) + { + CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFD) // _BAS: Base Address + CreateDWordField (CRSI, \_SB.TPM._Y34._LEN, LTFD) // _LEN: Length + MTFD = 0xFED40000 + LTFD = 0x5000 + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + ElseIf ((TTPF == Zero)) + { + CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFF) // _BAS: Base Address + MTFF = TPMM /* \TPMM */ + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + MTFE = Zero + LTFE = Zero + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + OperationRegion (TMMB, SystemMemory, 0xFED40000, 0x5000) + Field (TMMB, ByteAcc, Lock, Preserve) + { + Offset (0x04), + LCST, 32, + Offset (0x40), + CREQ, 32, + CSTS, 32, + Offset (0x4C), + SCMD, 32 + } + + OperationRegion (CRBD, SystemMemory, TPMM, 0x48) + Field (CRBD, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + HERR, 32, + Offset (0x40), + HCMD, 32, + HSTS, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((TTDP == Zero)) + { + If (TPMF) + { + Return (0x0F) + } + + Return (Zero) + } + ElseIf ((TTDP == One)) + { + If (TPMF) + { + Return (0x0F) + } + + Return (Zero) + } + + Return (Zero) + } + + Method (STRT, 3, Serialized) + { + OperationRegion (TPMR, SystemMemory, FTPM, 0x1000) + Field (TPMR, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + FERR, 32, + Offset (0x0C), + BEGN, 32 + } + + Name (TIMR, Zero) + If ((ToInteger (Arg0) != Zero)){} + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + TIMR = Zero + If ((AMDT == One)) + { + While (((BEGN == One) && (TIMR < 0x0200))) + { + If ((BEGN == One)) + { + Sleep (One) + TIMR++ + } + } + } + ElseIf ((((HSTS & 0x02) | (HSTS & One) + ) == 0x03)) + { + HCMD = One + } + Else + { + FERR = One + BEGN = Zero + } + + Return (Zero) + } + + } + + Return (One) + } + + Method (CRYF, 3, Serialized) + { + If ((ToInteger (Arg0) != One)){} + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + Name (TPMV, Package (0x02) + { + One, + Package (0x02) + { + One, + 0x20 + } + }) + If ((_STA () == Zero)) + { + Return (Package (0x01) + { + Zero + }) + } + + Return (TPMV) /* \_SB_.TPM_.CRYF.TPMV */ + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + } +} + + + +Scope (_SB.TPM) +{ + OperationRegion (TSMI, SystemIO, SMIA, 0x02) + Field (TSMI, WordAcc, NoLock, Preserve) + { + SMI, 16 + } + + OperationRegion (ATNV, SystemMemory, PPIM, PPIL) + Field (ATNV, AnyAcc, NoLock, Preserve) + { + RQST, 32, + RCNT, 32, + ERRO, 32, + FLAG, 32, + MISC, 32, + OPTN, 32, + SRSP, 32 + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */)) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (0x02) + { + 0xFF, 0x01 // .. + }) + } + Case (One) + { + If ((PPIV == Zero)) + { + Return ("1.2") + } + Else + { + Return ("1.3") + } + } + Case (0x02) + { + RQST = DerefOf (Arg3 [Zero]) + SRSP = Zero + FLAG = 0x02 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Case (0x03) + { + Name (PPI1, Package (0x02) + { + Zero, + Zero + }) + PPI1 [One] = RQST /* \_SB_.TPM_.RQST */ + Return (PPI1) /* \_SB_.TPM_._DSM.PPI1 */ + } + Case (0x04) + { + Return (TRST) /* \TRST */ + } + Case (0x05) + { + Name (PPI2, Package (0x03) + { + Zero, + Zero, + Zero + }) + SRSP = Zero + FLAG = 0x05 + SMI = OFST /* \OFST */ + PPI2 [One] = RCNT /* \_SB_.TPM_.RCNT */ + PPI2 [0x02] = ERRO /* \_SB_.TPM_.ERRO */ + Return (PPI2) /* \_SB_.TPM_._DSM.PPI2 */ + } + Case (0x06) + { + Return (0x03) + } + Case (0x07) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x07 + OPTN = Zero + If ((RQST == 0x17)) + { + ToInteger (DerefOf (Arg3 [One]), OPTN) /* \_SB_.TPM_.OPTN */ + } + + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Case (0x08) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x08 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Default + { + } + + } + } + ElseIf ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d"))) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x09 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Default + { + } + + } + } + + If ((Arg0 == ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8"))) + { + Return (CRYF (Arg1, Arg2, Arg3)) + } + + If ((Arg0 == ToUUID ("6bbf6cab-5463-4714-b7cd-f0203c0368d4"))) + { + Return (STRT (Arg1, Arg2, Arg3)) + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Method (TPTS, 1, Serialized) + { + Switch (ToInteger (Arg0)) + { + Case (0x04) + { + RQST = Zero + FLAG = 0x09 + SRSP = Zero + SMI = OFST /* \OFST */ + } + Case (0x05) + { + RQST = Zero + FLAG = 0x09 + SRSP = Zero + SMI = OFST /* \OFST */ + } + + } + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c b/src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt b/src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt new file mode 100644 index 0000000..62be952 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt @@ -0,0 +1,10 @@ +Vendor name: HP +Board name: Spectre 13t-ae000 +Board serial: DAOX33MBAFO +Board URL: https://support.hp.com/us-en/product/HP-Spectre-13-ae000-x360-Convertible-P… +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2017 diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb b/src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb new file mode 100644 index 0000000..2bf6b15 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb @@ -0,0 +1,221 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # Set the Thermal Control Circuit (TCC) activaction value to 95C + # even though FSP integration guide says to set it to 100C for SKL-U + # (offset at 0), because when the TCC activates at 100C, the CPU + # will have already shut itself down from overheating protection. + register "tcc_offset" = "5" # TCC of 95C + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + +# these are probably very wrong + # Enable EC Port 0x68/0x6C + register "gen1_dec" = "0x00040069" + + # EC range is 0x800-0x9ff + register "gen2_dec" = "0x00fc0901" + + # EC range is 0x1610-0x161F + register "gen3_dec" = "0x0001C1611" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" # do we actually need this with only nvme? + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + register "SataPortsEnable[1]" = "0" + register "SataPortsEnable[2]" = "0" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataSpeedLimit" = "2" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "SaGv" = "3" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + # EC/KBC requires continuous mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm | + #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + .ac_loadline = 1500, + .dc_loadline = 1430, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + .ac_loadline = 570, + .dc_loadline = 483, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, + }" + + # Enable Root Ports 5 and 9 + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[8]" = "1" + + # NVMe for port 9 settings + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpClkSrcNumber[8]" = "1" + + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port Left + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # UHD Graphics 620 + device pci 04.0 on end # Thermal Subsystem DSP + device pci 13.0 on end # Intel Sensor Hub + device pci 14.0 on end # USB 3 Controller + device pci 14.2 on end # Thermal Subsystem DSP + device pci 15.0 on end # I2C Controller + device pci 1c.0 on end # PCIe Root Port 1 + device pci 1c.1 on end # PCIe Root Port 2 + device pci 1c.4 on end # PCIe Root Port 5 + device pci 1d.0 on end # PCIe Root Port 9 + device pci 1e.0 off end # UART + device pci 1e.2 off end # SPI + device pci 1f.0 on end # ISA Bridge + device pci 1f.2 on end # Memory Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + end +end diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl b/src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl new file mode 100644 index 0000000..d36c960 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x01072009 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/gpio.h b/src/mainboard/hp/spectre_x360_13t_ae000/gpio.h new file mode 100644 index 0000000..42a6287 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/gpio.h @@ -0,0 +1,202 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* ------- GPIO group GPP_A ------- */ +/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x18), +/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c19), +/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c1a), +/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c1b), +/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c1c), +/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x1d), +/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x1e), +/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x82080102, 0x1f), +/* CLKRUN# */_PAD_CFG_STRUCT(GPP_A8, 0x44000702, 0x20), +/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1021), +/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1022), +/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000300, 0x23), +/* ISH_GP6 */_PAD_CFG_STRUCT(GPP_A12, 0x44000b02, 0x24), +/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x25), +/* GPIO */_PAD_CFG_STRUCT(GPP_A14, 0x44000300, 0x26), +/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3027), +/* GPIO */_PAD_CFG_STRUCT(GPP_A16, 0x44000300, 0x28), +/* GPIO */_PAD_CFG_STRUCT(GPP_A17, 0x44000100, 0x29), +/* ISH_GP0 */_PAD_CFG_STRUCT(GPP_A18, 0x44000700, 0x2a), +/* ISH_GP1 */_PAD_CFG_STRUCT(GPP_A19, 0x44000700, 0x2b), +/* ISH_GP2 */_PAD_CFG_STRUCT(GPP_A20, 0x44000700, 0x2c), +/* ISH_GP3 */_PAD_CFG_STRUCT(GPP_A21, 0x44000700, 0x2d), +/* ISH_GP4 */_PAD_CFG_STRUCT(GPP_A22, 0x44000700, 0x2e), +/* ISH_GP5 */_PAD_CFG_STRUCT(GPP_A23, 0x44000502, 0x3f), +/* ------- GPIO Group GPP_B -------*/ +/* GPIO */_PAD_CFG_STRUCT(GPP_B0, 0x44000300, 0x30), +/* GPIO */_PAD_CFG_STRUCT(GPP_B1, 0x44000300, 0x31), +/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x32), +/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000300, 0x33), +/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x34), +/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x35), +/* GPIO */_PAD_CFG_STRUCT(GPP_B6, 0x44000300, 0x36), +/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x37), +/* GPIO */_PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x38), +/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x39), +/* SRCCLKREQ5# */_PAD_CFG_STRUCT(GPP_B10, 0x44000700, 0x3a), +/* GPIO */_PAD_CFG_STRUCT(GPP_B11, 0x44000300, 0x3b), +/* GPIO */_PAD_CFG_STRUCT(GPP_B12, 0x44000300, 0x3c), +/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x3d), +/* SPKR */_PAD_CFG_STRUCT(GPP_B14, 0x44000700, 0x103e), +/* GSPI0_CS# */_PAD_CFG_STRUCT(GPP_B15, 0x44000700, 0x3f), +/* GSPI0_CLK */_PAD_CFG_STRUCT(GPP_B16, 0x84000700, 0x40), +/* GSPI0_MISO */_PAD_CFG_STRUCT(GPP_B17, 0x44000700, 0x41), +/* GSPI0_MOSI */_PAD_CFG_STRUCT(GPP_B18, 0x84000700, 0x42), +/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x43), +/* GPIO */_PAD_CFG_STRUCT(GPP_B20, 0x44000300, 0x1044), +/* GPIO */_PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x1045), +/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1046), +/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000300, 0x47), +/* ------- GPIO Group GPP_C ------- */ +/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x48), +/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1049), +/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x104a), +/* GPIO */_PAD_CFG_STRUCT(GPP_C3, 0x44000201, 0x4b), +/* GPIO */_PAD_CFG_STRUCT(GPP_C4, 0x44000201, 0x4c), +/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x4d), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), +/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000700, 0x50), +/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x51), +/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x52), +/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x53), +/* GPIO */_PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x54), +/* GPIO */_PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x55), +/* GPIO */_PAD_CFG_STRUCT(GPP_C14, 0x44000300, 0x56), +/* GPIO */_PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x57), +/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x58), +/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x59), +/* GPIO */_PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x5a), +/* GPIO */_PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x5b), +/* GPIO */_PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x5c), +/* GPIO */_PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x5d), +/* GPIO */_PAD_CFG_STRUCT(GPP_C22, 0x82880102, 0x105e), +/* GPIO */_PAD_CFG_STRUCT(GPP_C23, 0x80880102, 0x5f), +/* ------- GPIO Group GPP_D ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPP_D0, 0x44000300, 0x60), +/* GPIO */_PAD_CFG_STRUCT(GPP_D1, 0x44000300, 0x61), +/* GPIO */_PAD_CFG_STRUCT(GPP_D2, 0x44000300, 0x62), +/* GPIO */_PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x63), +/* GPIO */_PAD_CFG_STRUCT(GPP_D4, 0x44000300, 0x64), +/* ISH_I2C0_SDA */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x65), +/* ISH_I2C0_SCL */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x66), +/* ISH_I2C1_SDA */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x67), +/* ISH_I2C1_SCL */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x68), +/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x82000102, 0x69), +/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000200, 0x6a), +/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x6b), +/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000200, 0x6c), +/* GPIO */_PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x6d), +/* GPIO */_PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x6e), +/* GPIO */_PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x6f), +/* GPIO */_PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x70), +/* GPIO */_PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x71), +/* GPIO */_PAD_CFG_STRUCT(GPP_D18, 0x44000300, 0x72), +/* GPIO */_PAD_CFG_STRUCT(GPP_D19, 0x44000300, 0x73), +/* GPIO */_PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x74), +/* GPIO */_PAD_CFG_STRUCT(GPP_D21, 0x44000300, 0x75), +/* GPIO */_PAD_CFG_STRUCT(GPP_D22, 0x44000300, 0x76), +/* GPIO */_PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x77), +/* ------- GPIO Group GPP_E ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x84000102, 0x18), +/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x84000102, 0x19), +/* SATAXPCIE2 */_PAD_CFG_STRUCT(GPP_E2, 0x84000500, 0x1a), +/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x1b), +/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x84000200, 0x101c), +/* GPIO */_PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x1d), +/* GPIO */_PAD_CFG_STRUCT(GPP_E6, 0x44000300, 0x1e), +/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x1f), +/* GPIO */_PAD_CFG_STRUCT(GPP_E8, 0x44000300, 0x20), +/* GPIO */_PAD_CFG_STRUCT(GPP_E9, 0x44000300, 0x21), +/* GPIO */_PAD_CFG_STRUCT(GPP_E10, 0x44000201, 0x22), +/* GPIO */_PAD_CFG_STRUCT(GPP_E11, 0x80100102, 0x23), +/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x84000201, 0x24), +/* DDPB_HPD0 */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x25), +/* DDPC_HPD1 */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x26), +/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880300, 0x27), +/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000300, 0x28), +/* EDP_HPD */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x29), +/* DDPB_CTRLCLK */_PAD_CFG_STRUCT(GPP_E18, 0x44000702, 0x2a), +/* DDPB_CTRLDATA */_PAD_CFG_STRUCT(GPP_E19, 0x44000702, 0x102b), +/* DDPC_CTRLCLK */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x2c), +/* DDPC_CTRLDATA */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x102d), +/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000300, 0x2e), +/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x102f), +/* ------- GPIO Group GPD ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPD0, 0x4000201, 0x50), +/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000700, 0x51), +/* GPIO */_PAD_CFG_STRUCT(GPD2, 0x4000200, 0x52), +/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3053), +/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x54), +/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x55), +/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x56), +/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x57), +/* GPIO */_PAD_CFG_STRUCT(GPD8, 0x44000300, 0x58), +/* GPIO */_PAD_CFG_STRUCT(GPD9, 0x44000300, 0x59), +/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x44000700, 0x5a), +/* GPIO */_PAD_CFG_STRUCT(GPD11, 0x44000300, 0x5b), +/* ------- GPIO Group GPP_F ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x30), +/* GPIO */_PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x31), +/* GPIO */_PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x32), +/* GPIO */_PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x33), +/* GPIO */_PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x34), +/* GPIO */_PAD_CFG_STRUCT(GPP_F5, 0x44000300, 0x35), +/* GPIO */_PAD_CFG_STRUCT(GPP_F6, 0x44000300, 0x36), +/* GPIO */_PAD_CFG_STRUCT(GPP_F7, 0x44000300, 0x37), +/* GPIO */_PAD_CFG_STRUCT(GPP_F8, 0x44000100, 0x38), +/* GPIO */_PAD_CFG_STRUCT(GPP_F9, 0x44000100, 0x39), +/* I2C5_SDA */_PAD_CFG_STRUCT(GPP_F10, 0x44000702, 0x3a), +/* I2C5_SCL */_PAD_CFG_STRUCT(GPP_F11, 0x44000702, 0x3b), +/* GPIO */_PAD_CFG_STRUCT(GPP_F12, 0x44000300, 0x3c), +/* GPIO */_PAD_CFG_STRUCT(GPP_F13, 0x44000300, 0x3d), +/* GPIO */_PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x3e), +/* GPIO */_PAD_CFG_STRUCT(GPP_F15, 0x44000300, 0x3f), +/* GPIO */_PAD_CFG_STRUCT(GPP_F16, 0x44000300, 0x40), +/* GPIO */_PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x41), +/* GPIO */_PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x42), +/* GPIO */_PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x43), +/* GPIO */_PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x44), +/* GPIO */_PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x45), +/* GPIO */_PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x46), +/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000300, 0x47), +/* ------- GPIO Group GPP_G ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPP_G0, 0x44000102, 0x48), +/* GPIO */_PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x49), +/* GPIO */_PAD_CFG_STRUCT(GPP_G2, 0x44000100, 0x4a), +/* GPIO */_PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x4b), +/* GPIO */_PAD_CFG_STRUCT(GPP_G4, 0x44000100, 0x4c), +/* GPIO */_PAD_CFG_STRUCT(GPP_G5, 0x44000100, 0x4d), +/* GPIO */_PAD_CFG_STRUCT(GPP_G6, 0x44000100, 0x4e), +/* GPIO */_PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x4f), +}; + +#endif + +#endif diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c new file mode 100644 index 0000000..c0de990 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki <naresh.solanki(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <chip.h> +#include <console/console.h> +#include <device/azalia_device.h> +#include <soc/intel/common/hda_verb.h> +#include <soc/pci_devs.h> + +#include "hda_verb.h" + +static void codecs_init(u8 *base, u32 codec_mask) +{ + int i; + + /* Can support up to 4 codecs */ + for (i = 3; i >= 0; i--) { + if (codec_mask & (1 << i)) + hda_codec_init(base, i, cim_verb_data_size, + cim_verb_data); + } + + if (pc_beep_verbs_size) + hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs); +} + +static void mb_hda_codec_init(void *unused) +{ + static struct soc_intel_skylake_config *config; + u8 *base; + struct resource *res; + u32 codec_mask; + struct device *dev; + + dev = SA_DEV_ROOT; + /* Check if HDA is enabled, else return */ + if (dev == NULL || dev->chip_info == NULL) + return; + + config = dev->chip_info; + + /* + * IoBufferOwnership 0:HD-A Link, 1:Shared HD-A Link and I2S Port, + * 3:I2S Ports. In HDA mode where codec need to be programmed with + * verb table + */ + if (config->IoBufferOwnership == 3) + return; + + /* Find base address */ + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + if (dev == NULL) + return; + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + base = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "HDA: base = %p\n", base); + + codec_mask = hda_codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); + codecs_init(base, codec_mask); + } +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mb_hda_codec_init, NULL); diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h new file mode 100644 index 0000000..510a9ce --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0295, /* Codec Vendor / Device ID: Realtek */ + 0x103c83b9, /* Subsystem ID */ + 0x0000000d, /* Number of NID entries */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x103c83b9 */ + AZALIA_SUBVENDOR(0x0, 0x103c83b9), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) */ + AZALIA_PIN_CFG(0x0, 0x12, 0xb7a60130), + + /* Pin Complex (NID 0x13) */ + AZALIA_PIN_CFG(0x0, 0x13, 0x40000000), + + /* Pin Complex (NID 0x14) */ + AZALIA_PIN_CFG(0x0, 0x14, 0x411111f0), + + /* Pin Complex (NID 0x16) */ + AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), + + /* Pin Complex (NID 0x17) */ + AZALIA_PIN_CFG(0x0, 0x17, 0x90170110), + + /* Pin Complex (NID 0x18) */ + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) */ + AZALIA_PIN_CFG(0x0, 0x19, 0x03a11040), + + /* Pin Complex (NID 0x1A) */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), + + /* Pin Complex (NID 0x1B) */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), + + /* Pin Complex (NID 0x1D) */ + AZALIA_PIN_CFG(0x0, 0x1D, 0x40600001), + + /* Pin Complex (NID 0x1E) */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), + + /* Pin Complex (NID 0x21) */ + AZALIA_PIN_CFG(0x0, 0x21, 0x03211020), +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c b/src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c new file mode 100644 index 0000000..462b995 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <smbios.h> +#include <string.h> +#include <cbfs.h> + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t serial_len; + + cbfs_file_data(&cbfs_region, &file); + + serial_len = region_device_sz(&cbfs_region); + if (serial_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, 0, + serial_len) == serial_len) { + serial_number[serial_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, + MAX_SERIAL_LENGTH); + + return serial_number; +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c b/src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c new file mode 100644 index 0000000..94f8071 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/romstage.c b/src/mainboard/hp/spectre_x360_13t_ae000/romstage.c new file mode 100644 index 0000000..faf4090 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/romstage.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50 }, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 Gerrit-Change-Number: 34946 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Parnell <mparnell(a)gmail.com> Gerrit-MessageType: newchange

6 57

Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support
by Christian Walter (Code Review) June 8, 2024

June 8, 2024

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44578 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support ...................................................................... mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support Add initial support for another CFL variant. Quite hacky right now - but seems to boot Linux with Tianocore. Right now I need to enable, but hidden, the two additional NICs. Not sure where this comes from - maybe GPIOs. Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/mainboard/supermicro/x11-lga1151v2-series/Kconfig M src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/Makefile.inc A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/variants.h A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb 8 files changed, 460 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/44578/1 diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig index ed29b16..4029fce 100644 --- a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig @@ -25,6 +25,7 @@ config MAINBOARD_PART_NUMBER string default "X11SCH-F" if BOARD_SUPERMICRO_X11SCH_F + default "X11SCH-L4NF" if BOARD_SUPERMICRO_X11SCH_L4NF config MAINBOARD_DIR string @@ -33,10 +34,12 @@ config VARIANT_DIR string default "x11sch-f" if BOARD_SUPERMICRO_X11SCH_F + default "x11sch-l4nf" if BOARD_SUPERMICRO_X11SCH_L4NF config MAINBOARD_PART_NUMBER string default "X11SCH-F" if BOARD_SUPERMICRO_X11SCH_F + default "X11SCH-L4NF" if BOARD_SUPERMICRO_X11SCH_L4NF config MAX_CPUS int diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name index 8ab4f1e..d25b19f 100644 --- a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name +++ b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name @@ -1,3 +1,8 @@ config BOARD_SUPERMICRO_X11SCH_F bool "X11SCH-F" select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151V2_SERIES + +config BOARD_SUPERMICRO_X11SCH_L4NF + bool "X11SCH-L4NF" + select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151V2_SERIES + diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/Makefile.inc b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/Makefile.inc new file mode 100644 index 0000000..8914639 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt new file mode 100644 index 0000000..a66959a --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Vendor name: Supermicro +Board name: X11SCH-L4NF +Board URL: https://www.supermicro.com/en/products/motherboard/X11SCH-F +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c new file mode 100644 index 0000000..b2a72f5 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c @@ -0,0 +1,296 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "include/variant/gpio.h" +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_ALERT1# */ + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO0 */ + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_IO1 */ + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO2 */ + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO3 */ + _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_CS0# */ + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_ALERT0# */ + _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_CLK */ + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* CLKOUT_LPC1 */ + _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SUSWARN#/SUSPWRDNACK */ + _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_RESET# */ + _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSACK# */ + PAD_CFG_GPO(GPP_A16, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_A17, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, DEEP, OFF, ACPI), /* GPIO */ + /* GPP_A19 - RESERVED */ + _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A21, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, DEEP, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPO(GPP_B0, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_B3, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B5, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_B7, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B8, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B9, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B10, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B11, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S0# */ + _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* PLTRST# */ + _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SPKR */ + PAD_CFG_GPO(GPP_B15, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B16, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B17, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_B20, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B21, 1, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, DEEP, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* PCHHOT# */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ + _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPIO */ + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C12, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C13, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_C15, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C0_SDA */ + _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C0_SCL */ + _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C1_SDA */ + _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C1_SCL */ + /* GPP_C20 - RESERVED */ + PAD_CFG_GPO(GPP_C21, 1, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + + /* ------- GPIO Group GPP_D ------- */ + _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_D1, 1, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, DEEP, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_D5, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D6, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D7, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D8, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D9, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D10, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D11, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D12, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D13, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D14, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D16, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D17, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D18, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D19, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D21, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D22, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D23, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPO(GPP_G0, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G1, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G2, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G3, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G4, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G5, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G6, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G7, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group AZA ------- */ + + /* ------- GPIO Group VGPIO_0 ------- */ + + /* ------- GPIO Group VGPIO_1 ------- */ + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + PAD_CFG_GPO(GPD0, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ACPRESENT */ + _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* LAN_WAKE# */ + _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PRWBTN# */ + _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S3# */ + _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S4# */ + _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_A# */ + _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSCLK */ + PAD_CFG_GPO(GPD9, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S5# */ + PAD_CFG_GPO(GPD11, 0, DEEP), /* GPIO */ + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_K ------- */ + _PAD_CFG_STRUCT(GPP_K0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_K4, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K5, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K6, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K7, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K8, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_K9, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K10, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K11, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K13, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K14, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_K15, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K16, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_K18, 1, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SMI# */ + PAD_CFG_GPO(GPP_K20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K21, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H1, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H4, 0, DEEP), /* GPIO */ + /* GPP_H5 - RESERVED */ + PAD_CFG_GPO(GPP_H6, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H7, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H8, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H9, 0, DEEP), /* GPIO */ + /* GPP_H10 - RESERVED */ + /* GPP_H11 - RESERVED */ + PAD_CFG_GPO(GPP_H12, 1, PLTRST), /* GPIO */ + /* GPP_H13 - RESERVED */ + /* GPP_H14 - RESERVED */ + _PAD_CFG_STRUCT(GPP_H15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + /* GPP_H16 - RESERVED */ + /* GPP_H17 - RESERVED */ + _PAD_CFG_STRUCT(GPP_H18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_H19, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H20, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H21, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H22, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H23, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAXPCIE1 */ + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_E4, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_E7, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATALED# */ + _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC0# */ + _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC1# */ + _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC2# */ + _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC3# */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, DEEP, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, DEEP, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SCLOCK */ + _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SLOAD */ + _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SDATAOUT1 */ + _PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SDATAOUT0 */ + PAD_CFG_GPO(GPP_F14, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC4# */ + _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC5# */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F18, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F19, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F22, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F23, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group SPI ------- */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD0 */ + _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD1 */ + _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD2 */ + _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_HPD3 */ + _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* EDP_HPD */ + _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* DDPB_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPC_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPC_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), /* DDPD_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), /* DDPD_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG0 */ + _PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG1 */ + _PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG2 */ + _PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* M2_SKT2_CFG3 */ + + /* ------- GPIO Group GPP_J ------- */ + _PAD_CFG_STRUCT(GPP_J0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* CNV_PA_BLANKING */ + _PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* n/a */ + _PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ + _PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ + PAD_CFG_GPI_TRIG_OWN(GPP_J4, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J5, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_J7, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_J8, 1, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_J9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_J10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_J11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ +}; + +/* Early pad configuration in romstage. */ +const struct pad_config early_gpio_table[] = { + /* GPP_B0 - Toggle SMBus mux to read DIMM SPDs */ + PAD_CFG_GPO(GPP_B0, 1, DEEP), +}; + +const struct pad_config *get_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *get_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/gpio.h new file mode 100644 index 0000000..018a08f --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef X11SCH_F_GPIO_H +#define X11SCH_F_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> +#include <intelblocks/gpio_defs.h> + +const struct pad_config *get_gpio_table(size_t *num); +const struct pad_config *get_early_gpio_table(size_t *num); + +#endif /* X11SCH_F__GPIO_H */ diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/variants.h b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/variants.h new file mode 100644 index 0000000..b7ade58 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/variants.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/cnl_memcfg_init.h> + +/* Return memory configuration structure */ +const struct cnl_mb_cfg *variant_memcfg_config(void); diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb new file mode 100644 index 0000000..9f936f5 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb @@ -0,0 +1,128 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[21]" = "1" + register "PcieRpEnable[22]" = "1" + register "PcieRpEnable[23]" = "1" + + register "PcieClkSrcUsage[0]" = "0x80" + register "PcieClkSrcUsage[1]" = "0x80" + register "PcieClkSrcUsage[2]" = "0x80" + register "PcieClkSrcUsage[3]" = "0x80" + register "PcieClkSrcUsage[4]" = "0x80" + register "PcieClkSrcUsage[5]" = "0x80" + register "PcieClkSrcUsage[6]" = "0x80" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieClkSrcUsage[8]" = "0x80" + register "PcieClkSrcUsage[9]" = "0x80" + register "PcieClkSrcUsage[10]" = "0x80" + register "PcieClkSrcUsage[11]" = "0x80" + register "PcieClkSrcUsage[12]" = "0x80" + register "PcieClkSrcUsage[13]" = "0x80" + register "PcieClkSrcUsage[14]" = "0x80" + register "PcieClkSrcUsage[15]" = "0x80" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[6]" = "6" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[9]" = "9" + register "PcieClkSrcClkReq[10]" = "10" + register "PcieClkSrcClkReq[11]" = "11" + register "PcieClkSrcClkReq[12]" = "12" + register "PcieClkSrcClkReq[13]" = "13" + register "PcieClkSrcClkReq[14]" = "14" + register "PcieClkSrcClkReq[15]" = "15" + + register "gen1_dec" = "0x000c0ca1" # IPMI KCS + + # USB Config 2.0/3.0 + + # USB OC0 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" + + # USB OC1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" + + # USB OC2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" + + # USB OC3 + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" + + # USB OC4 + register "usb2_ports[7]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC4)" + + # USB OC5 + register "usb2_ports[8]" = "USB2_PORT_MID(OC5)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC5)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC5)" + + # USB KCS + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + # USB OC6/7 - not connected + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # HECI + register "HeciEnabled" = "1" + # SPS doesn't support all command issued by FSP... + register "DisableHeciRetry" = "1" + + # Internal GFX + register "InternalGfx" = "1" + + # Disable S0ix + register "s0ix_enable" = "0" + + device domain 0 on + device pci 1b.0 hidden end # PCIe Bridge + device pci 1b.4 on end # onboard Ethernet + device pci 1b.5 on end # onboard Ethernet + device pci 1b.6 hidden end # onboard Ethernet + device pci 1b.7 hidden end # onboard Ethernet + device pci 1c.0 on end # PCIe Bridge + device pci 1c.1 on end # Aspeed Graphics + device pci 1c.4 on end # NVMe PCIE x4 + device pci 1d.0 on end # PCIE x4 + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/44578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Gerrit-Change-Number: 44578 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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