November 2021 - coreboot-gerrit

Change in coreboot[master]: soc/mediatek/mt8195: add apusys init flow
by Yu-Ping Wu (Code Review) Nov. 1, 2021

Nov. 1, 2021

Attention is currently required from: flora.fu(a)mediatek.com. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58794 ) Change subject: soc/mediatek/mt8195: add apusys init flow ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5053d5e1f1c2286c9dce280ff83e8b8611b573b9 Gerrit-Change-Number: 58794 Gerrit-PatchSet: 1 Gerrit-Owner: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Comment-Date: Mon, 01 Nov 2021 09:45:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC
by Hung-Te Lin (Code Review) Nov. 1, 2021

Nov. 1, 2021

Attention is currently required from: Rex-BC Chen, Paul Menzel, Yu-Ping Wu, Felix Held. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58640 ) Change subject: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58640/comment/bc6ec4a7_6abcefab PS2, Line 10: > And that is big problem, and has to be improved. The commit you referenced should have had a more elaborate commit message. Then can you find a really good example that is providing all information asked here? Even the Intel one is probably not good enough: https://review.coreboot.org/c/coreboot/+/44857 Although, they do have a good example of having data sheet name and chapter in the file comments. @Rex can you follow the comment style in CL:44875 and update the files? /* * This file is created based on XXX Datasheet * Document number: 621483 * Chapter number: 2, 3, 4, 27, 28 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Gerrit-Change-Number: 58640 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Nov 2021 09:26:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC
by Rex-BC Chen (Code Review) Nov. 1, 2021

Nov. 1, 2021

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu, Felix Held. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58640 ) Change subject: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58640/comment/6853e634_6a3e9fe4 PS2, Line 10: > Rex, could you add a short paragraph explaining the similarities and differences between mt8186 and […] Done File src/soc/mediatek/mt8186/include/soc/timer.h: https://review.coreboot.org/c/coreboot/+/58640/comment/cb5c7d4d_98071ff2 PS3, Line 9: TIE_0_EN = 1 << 3, : COMP_15_EN = 1 << 10, : COMP_20_EN = 1 << 11, : COMP_25_EN = 1 << 12, > Rex, if these constants are always the same for platforms using v2 timer, please move them into time […] I think I would move these to v2 on upcoming patches. This is just a init patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/58640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Gerrit-Change-Number: 58640 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Nov 2021 09:26:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC
by Rex-BC Chen (Code Review) Nov. 1, 2021

Nov. 1, 2021

Attention is currently required from: Hung-Te Lin, Paul Menzel, Felix Held. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58640 ) Change subject: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Gerrit-Change-Number: 58640 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Nov 2021 09:22:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC
by Rex-BC Chen (Code Review) Nov. 1, 2021

Nov. 1, 2021

Attention is currently required from: Hung-Te Lin, Paul Menzel, Rex-BC Chen, Felix Held. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58640 to look at the new patch set (#4). Change subject: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC ...................................................................... soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC Add new folder and basic drivers for Mediatek SoC 'MT8186'. Difference of modules including in this patch between MT8186 and existing SoCs: Timer: Similar to MT8195, MT8186 uses v2 timer. EMI/PLL/SPI: Different from existing SoCs. TEST=boot from SPI-NOR and show uart log on MT8186 EVB BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 --- A src/soc/mediatek/mt8186/Kconfig A src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/bootblock.c A src/soc/mediatek/mt8186/emi.c A src/soc/mediatek/mt8186/include/soc/addressmap.h A src/soc/mediatek/mt8186/include/soc/emi.h A src/soc/mediatek/mt8186/include/soc/memlayout.ld A src/soc/mediatek/mt8186/include/soc/pll.h A src/soc/mediatek/mt8186/include/soc/spi.h A src/soc/mediatek/mt8186/include/soc/timer.h A src/soc/mediatek/mt8186/soc.c A src/soc/mediatek/mt8186/spi.c 12 files changed, 300 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/58640/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Gerrit-Change-Number: 58640 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/corsola: Add MediaTek MT8186 reference board
by Rex-BC Chen (Code Review) Nov. 1, 2021

Nov. 1, 2021

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58648 to look at the new patch set (#3). Change subject: mb/google/corsola: Add MediaTek MT8186 reference board ...................................................................... mb/google/corsola: Add MediaTek MT8186 reference board Add mainboard folder and drivers for new reference board 'Corsola'. TEST=build pass BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I2d701c03c97d3253effb6e93a2d55dcf6cf02db6 --- A src/mainboard/google/corsola/Kconfig A src/mainboard/google/corsola/Kconfig.name A src/mainboard/google/corsola/Makefile.inc A src/mainboard/google/corsola/board_info.txt A src/mainboard/google/corsola/bootblock.c A src/mainboard/google/corsola/chromeos.c A src/mainboard/google/corsola/chromeos.fmd A src/mainboard/google/corsola/devicetree.cb A src/mainboard/google/corsola/mainboard.c A src/mainboard/google/corsola/memlayout.ld A src/mainboard/google/corsola/reset.c A src/mainboard/google/corsola/romstage.c 12 files changed, 161 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/58648/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d701c03c97d3253effb6e93a2d55dcf6cf02db6 Gerrit-Change-Number: 58648 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: DO-NOT-SUBMIT: MT8186 Corsola review ToT
by Rex-BC Chen (Code Review) Nov. 1, 2021

Nov. 1, 2021

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58639 to look at the new patch set (#6). Change subject: DO-NOT-SUBMIT: MT8186 Corsola review ToT ...................................................................... DO-NOT-SUBMIT: MT8186 Corsola review ToT Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I53f304822c426417bb58037daa536bfb8dda1db3 --- M README.md 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/58639/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53f304822c426417bb58037daa536bfb8dda1db3 Gerrit-Change-Number: 58639 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: add apusys init flow
by flora.fu＠mediatek.com (Code Review) Nov. 1, 2021

Nov. 1, 2021

flora.fu(a)mediatek.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58794 ) Change subject: soc/mediatek/mt8195: add apusys init flow ...................................................................... soc/mediatek/mt8195: add apusys init flow Setup APU mbox's functional configuration registers. BUG=b:203145462 BRANCH=cherry TEST=boot asurada correctly Signed-off-by: Flora Fu <flora.fu(a)mediatek.com> Change-Id: I5053d5e1f1c2286c9dce280ff83e8b8611b573b9 --- M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/apusys.c M src/soc/mediatek/mt8195/include/soc/addressmap.h A src/soc/mediatek/mt8195/include/soc/apusys.h M src/soc/mediatek/mt8195/soc.c 5 files changed, 66 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/58794/1 diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 5d444c7..f99fa33 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -22,6 +22,7 @@ verstage-y += ../common/uart.c verstage-y += ../common/wdt.c +ramstage-y += apusys.c romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c romstage-y += ../common/clkbuf.c diff --git a/src/soc/mediatek/mt8195/apusys.c b/src/soc/mediatek/mt8195/apusys.c new file mode 100644 index 0000000..bc3c4ab --- /dev/null +++ b/src/soc/mediatek/mt8195/apusys.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/apusys.h> + +/* MBOX Functional Configuration */ +DEFINE_BITFIELD(LOCK, 0, 0) +DEFINE_BITFIELD(NO_MPU, 16, 16) + +static void dump_apusys_reg(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mt8195_apu_mbox); i++) { + printk(BIOS_INFO, "APU_MBOX %p = %#x\n", + (void *)&mt8195_apu_mbox[i]->mbox_func_cfg, + read32(&mt8195_apu_mbox[i]->mbox_func_cfg)); + } +} + +void apusys_init(void) +{ + int i; + + /* Setup MBOX MPU for non secure access */ + for (i = 0; i < ARRAY_SIZE(mt8195_apu_mbox); i++) + SET32_BITFIELDS(&mt8195_apu_mbox[i]->mbox_func_cfg, NO_MPU, 1, LOCK, 1); + + dump_apusys_reg(); +} diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h index 88b545a..cbe704c 100644 --- a/src/soc/mediatek/mt8195/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h @@ -80,6 +80,7 @@ IOCFG_RB_BASE = IO_PHYS + 0x01EB0000, IOCFG_TL_BASE = IO_PHYS + 0x01F40000, MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, + APU_MBOX_BASE = IO_PHYS + 0x09000000, DISP_OVL0_BASE = IO_PHYS + 0x0C000000, DISP_RDMA0_BASE = IO_PHYS + 0x0C002000, DISP_COLOR0_BASE = IO_PHYS + 0x0C003000, diff --git a/src/soc/mediatek/mt8195/include/soc/apusys.h b/src/soc/mediatek/mt8195/include/soc/apusys.h new file mode 100644 index 0000000..287e0f8 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/apusys.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_APUSYS_H +#define SOC_MEDIATEK_MT8195_APUSYS_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8195_apu_mbox_regs { + u32 mbox_in[8]; + u32 mbox_out[8]; + u32 mbox_reserved1[28]; + u32 mbox_func_cfg; + u32 mbox0_reserved2[19]; +}; + +check_member(mt8195_apu_mbox_regs, mbox_func_cfg, 0x0b0); + +static struct mt8195_apu_mbox_regs * const mt8195_apu_mbox[] = { + (void *)APU_MBOX_BASE, + (void *)(APU_MBOX_BASE + 0x100), + (void *)(APU_MBOX_BASE + 0x200), + (void *)(APU_MBOX_BASE + 0x300), + (void *)(APU_MBOX_BASE + 0x400), + (void *)(APU_MBOX_BASE + 0x500), + (void *)(APU_MBOX_BASE + 0x600), + (void *)(APU_MBOX_BASE + 0x700), +}; + +void apusys_init(void); +#endif /* SOC_MEDIATEK_MT8195_APUSYS_H */ diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c index 20bd226..80ca3d9 100644 --- a/src/soc/mediatek/mt8195/soc.c +++ b/src/soc/mediatek/mt8195/soc.c @@ -2,6 +2,7 @@ #include <bootmem.h> #include <device/device.h> +#include <soc/apusys.h> #include <soc/devapc.h> #include <soc/dfd.h> #include <soc/emi.h> @@ -28,6 +29,7 @@ { mtk_mmu_disable_l2c_sram(); dapc_init(); + apusys_init(); mcupm_init(); sspm_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/58794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5053d5e1f1c2286c9dce280ff83e8b8611b573b9 Gerrit-Change-Number: 58794 Gerrit-PatchSet: 1 Gerrit-Owner: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC
by Yu-Ping Wu (Code Review) Nov. 1, 2021

Nov. 1, 2021

Attention is currently required from: Hung-Te Lin, Paul Menzel, Rex-BC Chen, Felix Held. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58640 ) Change subject: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC ...................................................................... Patch Set 3: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58640/comment/1baaa0fe_312710e1 PS2, Line 10: > And that is big problem, and has to be improved. […] Rex, could you add a short paragraph explaining the similarities and differences between mt8186 and existing SoCs (mt8183/mt8192)? Example for the timer: Similar to MT8195, MT8186 uses v2 timer. File src/soc/mediatek/mt8186/include/soc/timer.h: https://review.coreboot.org/c/coreboot/+/58640/comment/4159d080_268b94d4 PS3, Line 9: TIE_0_EN = 1 << 3, : COMP_15_EN = 1 << 10, : COMP_20_EN = 1 << 11, : COMP_25_EN = 1 << 12, Rex, if these constants are always the same for platforms using v2 timer, please move them into timer_v2.h. If these happen to the same as in mt8195, we should keep them here. -- To view, visit https://review.coreboot.org/c/coreboot/+/58640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Gerrit-Change-Number: 58640 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Nov 2021 09:10:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brask: disabled autonomous GPIO power management
by David Wu (Code Review) Nov. 1, 2021

Nov. 1, 2021

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58793 ) Change subject: mb/google/brya/var/brask: disabled autonomous GPIO power management ...................................................................... mb/google/brya/var/brask: disabled autonomous GPIO power management Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=None TEST=emerge-brask coreboot Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Id9fab5f7d3be74f855e8116ec8f0f24ecc05e0b0 --- M src/mainboard/google/brya/variants/brask/overridetree.cb 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/58793/1 diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index 3805666..b20fc99 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -1,4 +1,15 @@ chip soc/intel/alderlake + # This disabled autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + device domain 0 on device ref dtt on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/58793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9fab5f7d3be74f855e8116ec8f0f24ecc05e0b0 Gerrit-Change-Number: 58793 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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