October 2021 - coreboot-gerrit

Change in coreboot[master]: soc/intel/common/tcss: Optimize Type-C DP flow
by Furquan Shaikh (Code Review) Sept. 30, 2021

Sept. 30, 2021

Attention is currently required from: Tim Wawrzynczak, Derek Huang, Curtis Chen, Brandon Breitenstein. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57139 ) Change subject: soc/intel/common/tcss: Optimize Type-C DP flow ...................................................................... Patch Set 20: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50 Gerrit-Change-Number: 57139 Gerrit-PatchSet: 20 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Curtis Chen <curtis.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 00:10:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/google/chromeec: Register USB-C mux operations
by Furquan Shaikh (Code Review) Sept. 30, 2021

Sept. 30, 2021

Attention is currently required from: Tim Wawrzynczak, Derek Huang. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58061 ) Change subject: src/ec/google/chromeec: Register USB-C mux operations ...................................................................... Patch Set 1: (1 comment) File src/ec/google/chromeec/usbc_mux.c: https://review.coreboot.org/c/coreboot/+/58061/comment/dc6be424_7cee9619 PS1, Line 5: struct static const struct -- To view, visit https://review.coreboot.org/c/coreboot/+/58061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I576c9e4c6c82d6b4055b0a0a9a75c677d4b05220 Gerrit-Change-Number: 58061 Gerrit-PatchSet: 1 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 00:08:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/google/chromeec: Update google_chromeec_usb_pd_get_info()
by Furquan Shaikh (Code Review) Sept. 30, 2021

Sept. 30, 2021

Attention is currently required from: Tim Wawrzynczak, Derek Huang. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58060 ) Change subject: src/ec/google/chromeec: Update google_chromeec_usb_pd_get_info() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b3df4223d5c26ea1c1a52b26f7d49fa4c947de8 Gerrit-Change-Number: 58060 Gerrit-PatchSet: 1 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 00:07:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/google/chromeec: Add new API for USB-C mux handling
by Furquan Shaikh (Code Review) Sept. 30, 2021

Sept. 30, 2021

Attention is currently required from: Tim Wawrzynczak, Derek Huang. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58059 ) Change subject: src/ec/google/chromeec: Add new API for USB-C mux handling ...................................................................... Patch Set 1: (1 comment) File src/ec/google/chromeec/ec.c: https://review.coreboot.org/c/coreboot/+/58059/comment/dd42900c_4e8c7a83 PS1, Line 1585: if (google_chromeec_usb_pd_get_info(port, &ufp, &dbg_acc, &active_cable, &dp_mode) < 0) { > line over 96 characters Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/58059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc27f23214c2d5b91334ae3efe248100329964ba Gerrit-Change-Number: 58059 Gerrit-PatchSet: 1 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 00:07:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/google/chromeec: Add APIs for USB-C DP ALT mode
by Furquan Shaikh (Code Review) Sept. 30, 2021

Sept. 30, 2021

Attention is currently required from: Tim Wawrzynczak, Derek Huang, Brandon Breitenstein, Curtis Chen. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57138 ) Change subject: src/ec/google/chromeec: Add APIs for USB-C DP ALT mode ...................................................................... Patch Set 13: Code-Review+2 (1 comment) File src/ec/google/chromeec/ec.c: https://review.coreboot.org/c/coreboot/+/57138/comment/0d999c2f_5b9a6907 PS13, Line 1675: !(mux_flags & USB_PD_MUX_HPD_LVL) || !(mux_flags & USB_PD_MUX_DP_ENABLED) nit: This can also be written as : ``` while ((mux_flags & hpd_asserted_mask) != hpd_asserted_mask)); ``` where, ``` hpd_asserted_mask = USB_PD_MUX_HPD_LVL | USB_PD_MUX_DP_ENABLED; ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/57138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3 Gerrit-Change-Number: 57138 Gerrit-PatchSet: 13 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 00:06:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/google/chromeec: Update some APIs
by Furquan Shaikh (Code Review) Sept. 30, 2021

Sept. 30, 2021

Attention is currently required from: Tim Wawrzynczak, Derek Huang. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58058 ) Change subject: src/ec/google/chromeec: Update some APIs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6020c4305e30018d4c97d862c16e8d642c951765 Gerrit-Change-Number: 58058 Gerrit-PatchSet: 1 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 00:02:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/arm64: Remove unnecessary interfaces
by Julius Werner (Code Review) Sept. 30, 2021

Sept. 30, 2021

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57819 ) Change subject: arch/arm64: Remove unnecessary interfaces ...................................................................... arch/arm64: Remove unnecessary interfaces <clocks.h> and smp_processor_id() aren't used anywhere anymore. Get rid of them. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I1a8c892b066e6ac0e7cec5316633d44165344e78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57819 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/arch/arm64/include/armv8/arch/cpu.h D src/arch/arm64/include/clocks.h 2 files changed, 0 insertions(+), 26 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index 919456b..15b2065 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -5,8 +5,6 @@ #define asmlinkage -static inline unsigned int smp_processor_id(void) { return 0; } - struct cpu_driver { }; #endif /* __ARCH_CPU_H__ */ diff --git a/src/arch/arm64/include/clocks.h b/src/arch/arm64/include/clocks.h deleted file mode 100644 index dc3080c..0000000 --- a/src/arch/arm64/include/clocks.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* Standard clock speeds */ - -/* - * We define some commonly-used clock speeds to avoid error since long - * numbers are hard to read. - * - * The format of the label is - * CLK_x_yU where: - * x is the integer speed - * y is the fractional part which can be omitted if 0 - * U is the units (blank for Hz, K or M for KHz and MHz) - * - * Please order the items by increasing Hz - */ -enum { - CLK_32768 = 32768, - CLK_20M = 20000000, - CLK_24M = 24000000, - CLK_144M = 144000000, - CLK_216M = 216000000, - CLK_300M = 300000000, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/57819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a8c892b066e6ac0e7cec5316633d44165344e78 Gerrit-Change-Number: 57819 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/gic: Remove unnecessary code
by Julius Werner (Code Review) Sept. 30, 2021

Sept. 30, 2021

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57818 ) Change subject: drivers/gic: Remove unnecessary code ...................................................................... drivers/gic: Remove unnecessary code On AArch64 platforms, GIC initialization is generally the job of Trusted Firmware and shouldn't be necessary in coreboot. Only the ancient T210 platform (which was started before we had decided on using Trusted Firmware) calls this code, and even there they have a comment wondering "do we still need this?". I'm just gonna assume (without testing because that board is ancient and I'm lazy) that they don't, and that the TF GIC initialization[1] is sufficient here. Remove this obsolete driver. [1] https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/… Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I3e9d90039dd27cb3a13f830ba21fc5cc7a70abe2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57818 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- D src/drivers/gic/Kconfig D src/drivers/gic/Makefile.inc D src/drivers/gic/gic.c D src/drivers/gic/gic.h D src/include/gic.h M src/soc/nvidia/tegra210/Kconfig M src/soc/nvidia/tegra210/Makefile.inc D src/soc/nvidia/tegra210/gic.c M src/soc/nvidia/tegra210/ramstage.c 9 files changed, 0 insertions(+), 260 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/drivers/gic/Kconfig b/src/drivers/gic/Kconfig deleted file mode 100644 index 193311f..0000000 --- a/src/drivers/gic/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -config GIC - def_bool n - help - This option enables GIC support, the ARM generic interrupt controller. diff --git a/src/drivers/gic/Makefile.inc b/src/drivers/gic/Makefile.inc deleted file mode 100644 index 51e3e19..0000000 --- a/src/drivers/gic/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_GIC) += gic.c diff --git a/src/drivers/gic/gic.c b/src/drivers/gic/gic.c deleted file mode 100644 index 610c0b8..0000000 --- a/src/drivers/gic/gic.c +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/cpu.h> -#include <device/mmio.h> -#include <console/console.h> -#include <gic.h> -#include <stddef.h> -#include "gic.h" - -enum { - ENABLE_GRP0 = 0x1 << 0, - ENABLE_GRP1 = 0x1 << 1, - FIQ_BYP_DIS_GRP0 = 0x1 << 5, - IRQ_BYP_DIS_GRP0 = 0x1 << 6, - FIQ_BYP_DIS_GRP1 = 0x1 << 7, - IRQ_BYP_DIS_GRP1 = 0x1 << 8, -}; - -struct gic { - struct gicd_mmio *gicd; - struct gicc_mmio *gicc; - size_t num_interrupts; - unsigned int version; - unsigned int security_extensions; -}; - -static struct gic *gic_get(void) -{ - static struct gic gic; - - if (gic.gicd == NULL) { - uint32_t typer; - - gic.gicd = gicd_base(); - gic.gicc = gicc_base(); - typer = read32(&gic.gicd->typer); - gic.num_interrupts = 32 * ((typer & 0x1f) + 1); - gic.security_extensions = !!(typer & (1 << 10)); - gic.version = (read32(&gic.gicd->icpidr2) & 0xf0) >> 4; - - printk(BIOS_DEBUG, "GICv%d - %zu ints %s GICD=%p GICC=%p\n", - gic.version, gic.num_interrupts, - gic.security_extensions ? "SecExtn" : "", - gic.gicd, gic.gicc); - } - - return &gic; -} - -static inline uint32_t gic_read(uint32_t *base) -{ - return read32(base); -} - -static inline void gic_write(uint32_t *base, uint32_t val) -{ - write32(base, val); -} - -static void gic_write_regs(uint32_t *base, size_t num_regs, uint32_t val) -{ - size_t i; - - for (i = 0; i < num_regs; i++) - gic_write(base++, val); -} - -static void gic_write_banked_regs(uint32_t *base, size_t interrupts_per_reg, - uint32_t val) -{ - /* 1st 32 interrupts are banked per CPU. */ - gic_write_regs(base, 32 / interrupts_per_reg, val); -} - -void gic_init(void) -{ - struct gic *gic; - struct gicd_mmio *gicd; - struct gicc_mmio *gicc; - uint32_t cpu_mask; - - gic = gic_get(); - gicd = gic->gicd; - gicc = gic->gicc; - - /* Enable Group 0 and Group 1 in GICD -- banked regs. */ - gic_write(&gicd->ctlr, ENABLE_GRP0 | ENABLE_GRP1); - - /* Enable Group 0 and Group 1 in GICC and enable all priroity levels. */ - gic_write(&gicc->ctlr, ENABLE_GRP0 | ENABLE_GRP1); - gic_write(&gicc->pmr, 1 << 7); - - cpu_mask = 1 << smp_processor_id(); - cpu_mask |= cpu_mask << 8; - cpu_mask |= cpu_mask << 16; - - /* Only write banked registers for secondary CPUs. */ - if (smp_processor_id()) { - gic_write_banked_regs(&gicd->itargetsr[0], 4, cpu_mask); - /* Put interrupts into Group 1. */ - gic_write_banked_regs(&gicd->igroupr[0], 32, ~0x0); - /* Allow Non-secure access to everything. */ - gic_write_banked_regs(&gicd->nsacr[0], 16, ~0x0); - return; - } - - /* All interrupts routed to processors that execute this function. */ - gic_write_regs(&gicd->itargetsr[0], gic->num_interrupts / 4, cpu_mask); - /* Put all interrupts into Gropup 1. */ - gic_write_regs(&gicd->igroupr[0], gic->num_interrupts / 32, ~0x0); - /* Allow Non-secure access to everything. */ - gic_write_regs(&gicd->nsacr[0], gic->num_interrupts / 16, ~0x0); -} - -void gic_disable(void) -{ - struct gic *gic; - struct gicc_mmio *gicc; - - gic = gic_get(); - gicc = gic->gicc; - - /* Disable secure, non-secure interrupts. */ - uint32_t val = gic_read(&gicc->ctlr); - val &= ~(ENABLE_GRP0 | ENABLE_GRP1); - /* - * Enable the IRQ/FIQ BypassDisable bits to bypass the IRQs. - * So the CPU can wake up from power gating state when the GIC - * was disabled. - */ - val |= FIQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP0 | - FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; - gic_write(&gicc->ctlr, val); -} - -void gic_enable(void) -{ - struct gic *gic; - struct gicc_mmio *gicc; - - gic = gic_get(); - gicc = gic->gicc; - - /* Enable secure, non-secure interrupts. */ - uint32_t val = gic_read(&gicc->ctlr); - val |= (ENABLE_GRP0 | ENABLE_GRP1); - gic_write(&gicc->ctlr, val); -} diff --git a/src/drivers/gic/gic.h b/src/drivers/gic/gic.h deleted file mode 100644 index 03fed63..0000000 --- a/src/drivers/gic/gic.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef DRIVERS_GIC_H -#define DRIVERS_GIC_H - -#include <stdint.h> - -#define NR(start, end) (((end) - (start)) / sizeof(uint32_t)) - -struct gicd_mmio { - uint32_t ctlr; /* 0x000 - 0x003 */ - uint32_t typer; /* 0x004 - 0x007 */ - uint32_t iidr; /* 0x008 - 0x00b */ - uint32_t reserved_1[NR(0xc, 0x80)]; /* 0x00c - 0x07f */ - uint32_t igroupr[NR(0x80, 0x100)]; /* 0x080 - 0x0ff */ - uint32_t isenabler[NR(0x100, 0x180)]; /* 0x100 - 0x17f */ - uint32_t icenabler[NR(0x180, 0x200)]; /* 0x180 - 0x1ff */ - uint32_t ispendr[NR(0x200, 0x280)]; /* 0x200 - 0x27f */ - uint32_t icpendr[NR(0x280, 0x300)]; /* 0x280 - 0x2ff */ - uint32_t isactiver[NR(0x300, 0x380)]; /* 0x300 - 0x37f */ - uint32_t icactiver[NR(0x380, 0x400)]; /* 0x380 - 0x3ff */ - uint32_t ipriorityr[NR(0x400, 0x7fc)]; /* 0x400 - 0x7fb */ - uint32_t reserved_2[NR(0x7fc, 0x800)]; /* 0x7fc - 0x7ff */ - uint32_t itargetsr[NR(0x800, 0xbfc)]; /* 0x800 - 0xbfb */ - uint32_t reserved_3[NR(0xbfc, 0xc00)]; /* 0xbfc - 0x2ff */ - uint32_t icfgr[NR(0xc00, 0xd00)]; /* 0xc00 - 0xcff */ - uint32_t reserved_4[NR(0xd00, 0xe00)]; /* 0xd00 - 0xdff */ - uint32_t nsacr[NR(0xe00, 0xf00)]; /* 0xe00 - 0xeff */ - uint32_t sgir; /* 0xf00 - 0xf03 */ - uint32_t reserved_5[NR(0xf04, 0xf10)]; /* 0xf04 - 0xf0f */ - uint32_t cpendsgir[NR(0xf10, 0xf20)]; /* 0xf10 - 0xf1f */ - uint32_t spendsgir[NR(0xf20, 0xf30)]; /* 0xf20 - 0xf2f */ - uint32_t reserved_6[NR(0xf30, 0xfe8)]; /* 0xf30 - 0xfe7 */ - uint32_t icpidr2; /* 0xfe8 - 0xfeb */ - uint32_t reserved_7[NR(0xfec, 0x1000)]; /* 0xfec - 0xfff */ -}; - -struct gicc_mmio { - uint32_t ctlr; /* 0x000 - 0x003 */ - uint32_t pmr; /* 0x004 - 0x007 */ - uint32_t bpr; /* 0x008 - 0x00b */ - uint32_t iar; /* 0x00c - 0x00f */ - uint32_t eoir; /* 0x010 - 0x013 */ - uint32_t rpr; /* 0x014 - 0x017 */ - uint32_t hppir; /* 0x018 - 0x01b */ - uint32_t apbr; /* 0x01c - 0x01f */ - uint32_t aiar; /* 0x020 - 0x023 */ - uint32_t aeoir; /* 0x024 - 0x027 */ - uint32_t ahppir; /* 0x028 - 0x02b */ - uint32_t resered_1[NR(0x2c, 0xd0)]; /* 0x02c - 0x0cf */ - uint32_t apr[NR(0xd0, 0xe0)]; /* 0x0d0 - 0x0df */ - uint32_t nsapr[NR(0xe0, 0xf0)]; /* 0x0e0 - 0x0ef */ - uint32_t resered_2[NR(0xf0, 0xfc)]; /* 0x0f0 - 0x0fb */ - uint32_t iidr; /* 0x0fc - 0x0ff */ - uint32_t reserved_3[NR(0x100, 0x1000)]; /* 0x100 - 0xfff */ - uint32_t dir; /* 0x1000 - 0x1003 */ -}; - -#undef NR - -#endif /* DRIVERS_GIC_H */ diff --git a/src/include/gic.h b/src/include/gic.h deleted file mode 100644 index a4201bb..0000000 --- a/src/include/gic.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef GIC_H -#define GIC_H - -#if CONFIG(GIC) - -/* Initialize the GIC on the currently processor, including GICD and GICC. */ -void gic_init(void); -void gic_disable(void); -void gic_enable(void); - -/* Return a pointer to the base of the GIC distributor mmio region. */ -void *gicd_base(void); - -/* Return a pointer to the base of the GIC CPU mmio region. */ -void *gicc_base(void); - -#else /* CONFIG_GIC */ - -static inline void gic_init(void) {} -static inline void gic_disable(void) {} - -#endif /* CONFIG_GIC */ - -#endif /* GIC_H */ diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 32748f3..4fcbaff 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -6,7 +6,6 @@ select ARCH_VERSTAGE_ARMV4 select ARCH_ROMSTAGE_ARMV4 select ARCH_RAMSTAGE_ARMV8_64 - select GIC select HAVE_UART_SPECIAL select ARM64_USE_ARM_TRUSTED_FIRMWARE select GENERIC_GPIO_LIB diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index e213751..f76ab34 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -79,7 +79,6 @@ ramstage-y += ape.c ramstage-y += power.c ramstage-y += dma.c -ramstage-y += gic.c ramstage-y += monotonic_timer.c ramstage-y += padconfig.c ramstage-y += funitcfg.c diff --git a/src/soc/nvidia/tegra210/gic.c b/src/soc/nvidia/tegra210/gic.c deleted file mode 100644 index f02ce53..0000000 --- a/src/soc/nvidia/tegra210/gic.c +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <gic.h> -#include <soc/addressmap.h> - -void *gicd_base(void) -{ - return (void *)(uintptr_t)TEGRA_GICD_BASE; -} - -void *gicc_base(void) -{ - return (void *)(uintptr_t)TEGRA_GICC_BASE; -} diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index c470e6b..50249b7 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -5,7 +5,6 @@ #include <cbmem.h> #include <console/console.h> #include <device/mmio.h> -#include <gic.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/mmu_operations.h> @@ -41,9 +40,6 @@ void ramstage_entry(void); void ramstage_entry(void) { - /* TODO: Is this still needed? */ - gic_init(); - /* TODO: Move arch timer setup to BL31? */ arm64_arch_timer_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/57818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e9d90039dd27cb3a13f830ba21fc5cc7a70abe2 Gerrit-Change-Number: 57818 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/gic: Remove unnecessary code
by Julius Werner (Code Review) Sept. 30, 2021

Sept. 30, 2021

Attention is currently required from: Felix Held. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57818 ) Change subject: drivers/gic: Remove unnecessary code ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > if you think that it's safe to remove the GIC code, I'm ok with that. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e9d90039dd27cb3a13f830ba21fc5cc7a70abe2 Gerrit-Change-Number: 57818 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 01 Oct 2021 00:01:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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