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Change in coreboot[master]: mb/kontron/986lcd-m: Select FIXED_UART_FOR_CONSOLE
by Paul Menzel (Code Review) Aug. 7, 2023
by Paul Menzel (Code Review) Aug. 7, 2023
Aug. 7, 2023
Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39124 )
Change subject: mb/kontron/986lcd-m: Select FIXED_UART_FOR_CONSOLE
......................................................................
mb/kontron/986lcd-m: Select FIXED_UART_FOR_CONSOLE
The serial port base address is hardcoded for this mainboard, so
deactivate the Kconfig dialog for `TTYS0_BASE`.
Change-Id: Ic989e4c4fde8ce03c6941c44f71dc72840fc77c3
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M src/mainboard/kontron/986lcd-m/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/39124/1
diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig
index dfc7c3c..204d404 100644
--- a/src/mainboard/kontron/986lcd-m/Kconfig
+++ b/src/mainboard/kontron/986lcd-m/Kconfig
@@ -9,6 +9,7 @@
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_WINBOND_W83627THG
select SUPERIO_NUVOTON_COMMON_HWM # Nuvoton is a Winbond spin-off
+ select FIXED_UART_FOR_CONSOLE
select HAVE_ACPI_TABLES
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
--
To view, visit https://review.coreboot.org/c/coreboot/+/39124
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic989e4c4fde8ce03c6941c44f71dc72840fc77c3
Gerrit-Change-Number: 39124
Gerrit-PatchSet: 1
Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-MessageType: newchange
4
4
Change in ...coreboot[master]: WIP: google/krane: Add Panel TV101WUM-NL6 support.
by Kaka Ni (Code Review) Aug. 7, 2023
by Kaka Ni (Code Review) Aug. 7, 2023
Aug. 7, 2023
Kaka Ni has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32512
Change subject: WIP: google/krane: Add Panel TV101WUM-NL6 support.
......................................................................
WIP: google/krane: Add Panel TV101WUM-NL6 support.
Add panel TV101WUM-NL6 for Krane.
The edid info and init command are from:
https://crrev.com/c/1565758
Change-Id: Ieb6b2be6c2c571c09c781f4370d8c52612421823
Signed-off-by: Kaka Ni <nigang(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/kukui/Makefile.inc
M src/mainboard/google/kukui/display.c
M src/mainboard/google/kukui/display.h
A src/mainboard/google/kukui/panel_krane.c
4 files changed, 423 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/32512/1
diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc
index ef52031..9576b7d 100644
--- a/src/mainboard/google/kukui/Makefile.inc
+++ b/src/mainboard/google/kukui/Makefile.inc
@@ -24,6 +24,7 @@
ramstage-y += chromeos.c
ramstage-y += display.c
ramstage-y += panel_kukui.c
+ramstage-y += panel_krane.c
ramstage-y += mainboard.c
ramstage-y += memlayout.ld
ramstage-y += reset.c
diff --git a/src/mainboard/google/kukui/display.c b/src/mainboard/google/kukui/display.c
index 5ec6ccd..b0a5026 100644
--- a/src/mainboard/google/kukui/display.c
+++ b/src/mainboard/google/kukui/display.c
@@ -97,6 +97,8 @@
{
if (CONFIG(BOARD_GOOGLE_KUKUI))
return &kukui_display_intf;
+ else if (CONFIG(BOARD_GOOGLE_KRANE))
+ return &krane_display_intf;
else
return NULL;
}
diff --git a/src/mainboard/google/kukui/display.h b/src/mainboard/google/kukui/display.h
index 33cc997..52420db 100644
--- a/src/mainboard/google/kukui/display.h
+++ b/src/mainboard/google/kukui/display.h
@@ -33,9 +33,18 @@
PANEL_KUKUI_UNINITIALIZED
};
+enum krane_panel_id {
+ PANEL_KRANE_FIRST = 0,
+ PANEL_KRANE_BOE_TV101WUM_NL6,
+ PANEL_KRANE_UNKNOWN,
+ PANEL_KRANE_COUNT,
+ PANEL_KRANE_UNINITIALIZED
+};
+
union panel_id {
enum kukui_panel_id kukui_panel;
+ enum krane_panel_id krane_panel;
int value;
};
@@ -90,6 +99,7 @@
* Panel Interface for boards
*/
extern struct board_display_intf kukui_display_intf;
+extern struct board_display_intf krane_display_intf;
#endif
diff --git a/src/mainboard/google/kukui/panel_krane.c b/src/mainboard/google/kukui/panel_krane.c
new file mode 100644
index 0000000..5c338c8
--- /dev/null
+++ b/src/mainboard/google/kukui/panel_krane.c
@@ -0,0 +1,410 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Huaqin Telecom Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <edid.h>
+#include <gpio.h>
+#include <soc/auxadc.h>
+#include <soc/ddp.h>
+#include <soc/dsi.h>
+#include <soc/gpio.h>
+#include <boardid.h>
+
+#include "display.h"
+#include "gpio.h"
+
+static struct edid krane_boe_tv101wum_nl6_edid = {
+ .panel_bits_per_color = 8,
+ .panel_bits_per_pixel = 24,
+ .mode = {
+ .name = "1200x1920@60Hz",
+ .pixel_clock = 159420,
+ .lvds_dual_channel = 0,
+ .refresh = 60,
+ .ha = 1200, .hbl = 164, .hso = 80, .hspw = 24, .hborder = 0,
+ .va = 1920, .vbl = 28, .vso = 10, .vspw = 4, .vborder = 0,
+ .phsync = '-', .pvsync = '-',
+ .x_mm = 135, .y_mm = 216,
+ },
+};
+
+struct lcm_init_table boe_tv101wum_nl6_init_cmd[] = {
+ {INIT_DCS_CMD, 1, { 0x10 } },
+ {DELAY_CMD, 34, {} },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0xE5 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x52 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x88 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x03 } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x8B } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x1A } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x0F } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x01 } },
+ {INIT_DCS_CMD, 2, { 0xE0, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xE1, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xDC, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xDD, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xD2, 0x03 } },
+ {INIT_DCS_CMD, 2, { 0xD3, 0x03 } },
+ {INIT_DCS_CMD, 2, { 0xE6, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xE7, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0x09 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0x09 } },
+ {INIT_DCS_CMD, 2, { 0xD8, 0x0A } },
+ {INIT_DCS_CMD, 2, { 0xD9, 0x0A } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0x0B } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0x0B } },
+ {INIT_DCS_CMD, 2, { 0xD6, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xD7, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xD4, 0x06 } },
+ {INIT_DCS_CMD, 2, { 0xD5, 0x06 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xDE, 0x08 } },
+ {INIT_DCS_CMD, 2, { 0xDF, 0x08 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x0D } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0x17 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0x31 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0x1C } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0x2C } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0x33 } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0x31 } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0x2E } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xCF, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xD0, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xD2, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xD3, 0x0D } },
+ {INIT_DCS_CMD, 2, { 0xD4, 0x17 } },
+ {INIT_DCS_CMD, 2, { 0xD5, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xD6, 0x31 } },
+ {INIT_DCS_CMD, 2, { 0xD7, 0x3F } },
+ {INIT_DCS_CMD, 2, { 0xD8, 0x3F } },
+ {INIT_DCS_CMD, 2, { 0xD9, 0x3F } },
+ {INIT_DCS_CMD, 2, { 0xDA, 0x3F } },
+ {INIT_DCS_CMD, 2, { 0xDB, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xDC, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xDD, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xDE, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xDF, 0x2E } },
+ {INIT_DCS_CMD, 2, { 0xE0, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xE1, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xE2, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x03 } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0x0B } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xE7, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0x2A } },
+ {INIT_DCS_CMD, 2, { 0xDE, 0x2A } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x43 } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xE4, 0xC0 } },
+ {INIT_DCS_CMD, 2, { 0xE5, 0x0D } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x06 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0xA5 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0xA5 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0x0F } },
+ {INIT_DCS_CMD, 2, { 0xD5, 0x32 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x0F } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x25 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4E } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x72 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x97 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xDC } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x22 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xA4 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x2B } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xA9 } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x25 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x61 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x97 } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB2 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xCD } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xD9 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE7 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF4 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x08 } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x11 } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x24 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4F } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x72 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x98 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xDC } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x23 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xA6 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x2C } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x30 } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xAA } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x62 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x9B } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB5 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xCF } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xDB } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE8 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF5 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x09 } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x24 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x3B } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4F } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x73 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x99 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xE0 } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xAD } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x36 } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x3A } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xAE } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x2A } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x66 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x9E } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB8 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xD1 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xDD } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE9 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF6 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x0A } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x0F } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x25 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4E } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x72 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x97 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xDC } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x22 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xA4 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x2B } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xA9 } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x25 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x61 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x97 } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB2 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xCD } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xD9 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE7 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF4 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x0B } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x11 } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x24 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4F } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x72 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x98 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xDC } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x23 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xA6 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x2C } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x30 } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xAA } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x62 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x9B } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB5 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xCF } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xDB } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE8 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF5 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x24 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x3B } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4F } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x73 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x99 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xE0 } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xAD } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x36 } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x3A } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xAE } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x2A } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x66 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x9E } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB8 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xD1 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xDD } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE9 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF6 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x08 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x68 } },
+ {DELAY_CMD, 10, {} },
+ {INIT_DCS_CMD, 1, { 0x11 } },
+ {DELAY_CMD, 120, {} },
+ {INIT_DCS_CMD, 1, { 0x29 } },
+ {DELAY_CMD, 20, {} },
+
+};
+
+struct panel_info krane_panel_info[] = {
+ PANEL(PANEL_KRANE_BOE_TV101WUM_NL6,
+ 74000,
+ krane_boe_tv101wum_nl6_edid,
+ boe_tv101wum_nl6_init_cmd),
+ {{PANEL_KRANE_UNKNOWN}, "PANEL_KRANE_UNKNOWN",
+ 0, NULL, NULL, 0},
+};
+
+
+static union panel_id krane_get_panel_id(struct board_display_intf *intf)
+{
+
+ return (union panel_id)PANEL_KRANE_BOE_TV101WUM_NL6;
+};
+
+static bool krane_is_panel_id_valid(union panel_id id)
+{
+ if (id.value < PANEL_KRANE_UNKNOWN)
+ return true;
+ return false;
+};
+
+static int krane_backlight(struct board_display_intf *intf)
+{
+ configure_backlight();
+ return 0;
+};
+
+static int krane_power(struct board_display_intf *intf)
+{
+
+ if (board_id() < 2) {
+ /* board from p1 */
+ gpio_output(GPIO(LCM_RST), 0);
+ udelay(100);
+ gpio_output(GPIO(LCM_RST), 1);
+ mdelay(20);
+ } else {
+ /* board from p2 */
+ gpio_output(GPIO(LCM_RST), 0);
+ udelay(1500);
+ gpio_output(GPIO(SIM2_SRST), 1);
+ mdelay(5);
+ gpio_output(GPIO(PERIPHERAL_EN9), 1);
+ gpio_output(GPIO(MISC_BSI_CK_3), 1);
+ mdelay(100);
+ gpio_output(GPIO(LCM_RST), 1);
+ mdelay(10);
+ }
+
+ return 0;
+
+};
+
+struct board_display_intf krane_display_intf = {
+ .board = "krane",
+ .all_panel_info = krane_panel_info,
+ .all_panel_info_size = ARRAY_SIZE(krane_panel_info),
+ .cur_panel_info = NULL,
+ .get_panel_id = &krane_get_panel_id,
+ .is_panel_id_valid = &krane_is_panel_id_valid,
+ .backlight = &krane_backlight,
+ .power = &krane_power,
+};
--
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6
15
Change in ...coreboot[master]: util/lint: check correctness of Change-Id line
by Idwer Vollering (Code Review) Aug. 7, 2023
by Idwer Vollering (Code Review) Aug. 7, 2023
Aug. 7, 2023
Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33884
Change subject: util/lint: check correctness of Change-Id line
......................................................................
util/lint: check correctness of Change-Id line
Change-Id: I67b9f134500bb596ae5790b68fe9f27e2fa2cfb4
Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>
---
A util/lint/lint-extended-024-change-id
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/33884/1
diff --git a/util/lint/lint-extended-024-change-id b/util/lint/lint-extended-024-change-id
new file mode 100755
index 0000000..1989ed4
--- /dev/null
+++ b/util/lint/lint-extended-024-change-id
@@ -0,0 +1,10 @@
+#!/bin/sh
+if [ "$(git log -n 1 | grep -c '[[:space:]]\+Change-Id: ')" -lt 1 ]
+then
+ echo "Change-Id line is missing";
+fi
+
+if [ "$(git log -n 1 | grep -c '[[:space:]]\+Change-Id: ')" -gt 1 ]
+then
+ echo "Found more than one Change-Id line";
+fi
--
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Gerrit-Change-Id: I67b9f134500bb596ae5790b68fe9f27e2fa2cfb4
Gerrit-Change-Number: 33884
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Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com>
Gerrit-MessageType: newchange
7
18
Change in coreboot[master]: cpu/intel/speedstep: Add comment to clarify define
by Patrick Rudolph (Code Review) Aug. 7, 2023
by Patrick Rudolph (Code Review) Aug. 7, 2023
Aug. 7, 2023
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34360 )
Change subject: cpu/intel/speedstep: Add comment to clarify define
......................................................................
cpu/intel/speedstep: Add comment to clarify define
Add a comment to clarify that the define must match the define in
southbridge headers.
Change-Id: Ie0e97b170c81e3bca38975d6a3fe9a368c70e622
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/include/cpu/intel/speedstep.h
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/34360/1
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index 05d83ed..660e5ae 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -25,6 +25,7 @@
/* MWAIT coordination I/O base address. This must match
* the \_PR_.CP00 PM base address.
+ * PMB0_BASE - 0x10 should match PMBASE for legacy C-state emulation.
*/
#define PMB0_BASE 0x510
--
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Gerrit-Branch: master
Gerrit-Change-Id: Ie0e97b170c81e3bca38975d6a3fe9a368c70e622
Gerrit-Change-Number: 34360
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
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5
4
Change in coreboot[master]: coreinfo/coreinfo.c: Provide information of time format
by Name of user not set (Code Review) Aug. 7, 2023
by Name of user not set (Code Review) Aug. 7, 2023
Aug. 7, 2023
Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35847 )
Change subject: coreinfo/coreinfo.c: Provide information of time format
......................................................................
coreinfo/coreinfo.c: Provide information of time format
Specify Coordinated Universal Time (UTC) time format while print date and time
in the coreinfo payload.
Change-Id: I359cef7697daf5d92d2c9fb58bf75c5b1345e982
Signed-off-by: Sourabh Kashyap <sourabhka(a)hcl.com>
---
M payloads/coreinfo/coreinfo.c
1 file changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/35847/1
diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c
index 53985b2..ea4d424 100644
--- a/payloads/coreinfo/coreinfo.c
+++ b/payloads/coreinfo/coreinfo.c
@@ -124,8 +124,10 @@
rtc_read_clock(&tm);
- mvwprintw(menuwin, 1, 57, "%02d/%02d/%04d - %02d:%02d:%02d",
- tm.tm_mon + 1, tm.tm_mday, 1900 + tm.tm_year, tm.tm_hour,
+ mvwprintw(menuwin, 1, 53, "%02d/%02d/%04d", tm.tm_mon + 1,
+ tm.tm_mday, 1900 + tm.tm_year);
+ mvwprintw(menuwin, 1, 63, " - UTC ");
+ mvwprintw(menuwin, 1, 70, "%02d:%02d:%02d", tm.tm_hour,
tm.tm_min, tm.tm_sec);
}
#endif
--
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Gerrit-Change-Id: I359cef7697daf5d92d2c9fb58bf75c5b1345e982
Gerrit-Change-Number: 35847
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4
10
Change in coreboot[master]: soc/intel/(fsp_)baytrail: Initialize SPI before console init
by Arthur Heymans (Code Review) Aug. 7, 2023
by Arthur Heymans (Code Review) Aug. 7, 2023
Aug. 7, 2023
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36407 )
Change subject: soc/intel/(fsp_)baytrail: Initialize SPI before console init
......................................................................
soc/intel/(fsp_)baytrail: Initialize SPI before console init
This makes the spi flash console function during romstage. It was
tested with the FSP baytrail codepath but it's a safe assumption that
the same fix also applies for the google mrc.bin codepath.
Tested on Intel Minnowboard Turbot.
Change-Id: If6ef0eeea902ab76d398d0218ee943e482f69b43
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/fsp_baytrail/romstage/romstage.c
2 files changed, 5 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/36407/1
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 7c129e2..e06c39e 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -165,10 +165,10 @@
if (CONFIG(ENABLE_BUILTIN_COM1))
byt_config_com1_and_enable();
- console_init();
-
spi_init();
+ console_init();
+
set_max_freq();
punit_init();
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index f347591..78aa9fc 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -171,9 +171,11 @@
byt_config_com1_and_enable();
post_code(0x43);
- console_init();
spi_init();
+
+ console_init();
+
baytrail_rtc_init();
/* Call into mainboard. */
--
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Gerrit-Change-Id: If6ef0eeea902ab76d398d0218ee943e482f69b43
Gerrit-Change-Number: 36407
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4
3
Change in coreboot[master]: arch/acpi.h: Avoid explicitly assign values to enum names
by Name of user not set (Code Review) Aug. 7, 2023
by Name of user not set (Code Review) Aug. 7, 2023
Aug. 7, 2023
Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36430 )
Change subject: arch/acpi.h: Avoid explicitly assign values to enum names
......................................................................
arch/acpi.h: Avoid explicitly assign values to enum names
Compiler by default assign values starting from the initial integral constant.
Change-Id: I1a5aa9762051780b67013f67f101112fc7a0bf6e
Signed-off-by: Himanshu Sahdev <himanshusah(a)hcl.com>
---
M src/arch/x86/include/arch/acpi.h
1 file changed, 19 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/36430/1
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 479067f..a9bd9f6 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -302,10 +302,10 @@
enum dev_scope_type {
SCOPE_PCI_ENDPOINT = 1,
- SCOPE_PCI_SUB = 2,
- SCOPE_IOAPIC = 3,
- SCOPE_MSI_HPET = 4,
- SCOPE_ACPI_NAMESPACE_DEVICE = 5
+ SCOPE_PCI_SUB,
+ SCOPE_IOAPIC,
+ SCOPE_MSI_HPET,
+ SCOPE_ACPI_NAMESPACE_DEVICE
};
typedef struct dev_scope {
@@ -321,11 +321,11 @@
} __packed dev_scope_t;
enum dmar_type {
- DMAR_DRHD = 0,
- DMAR_RMRR = 1,
- DMAR_ATSR = 2,
- DMAR_RHSA = 3,
- DMAR_ANDD = 4
+ DMAR_DRHD,
+ DMAR_RMRR,
+ DMAR_ATSR,
+ DMAR_RHSA,
+ DMAR_ANDD
};
enum {
@@ -599,15 +599,15 @@
/* FADT Preferred Power Management Profile */
enum acpi_preferred_pm_profiles {
- PM_UNSPECIFIED = 0,
- PM_DESKTOP = 1,
- PM_MOBILE = 2,
- PM_WORKSTATION = 3,
- PM_ENTERPRISE_SERVER = 4,
- PM_SOHO_SERVER = 5,
- PM_APPLIANCE_PC = 6,
- PM_PERFORMANCE_SERVER = 7,
- PM_TABLET = 8, /* ACPI 5.0 & greater */
+ PM_UNSPECIFIED,
+ PM_DESKTOP,
+ PM_MOBILE,
+ PM_WORKSTATION3,
+ PM_ENTERPRISE_SERVER4,
+ PM_SOHO_SERVER,
+ PM_APPLIANCE_PC,
+ PM_PERFORMANCE_SERVER,
+ PM_TABLET, /* ACPI 5.0 & greater */
};
/* FACS (Firmware ACPI Control Structure) */
@@ -780,7 +780,7 @@
};
enum acpi_ipmi_interface_type {
- IPMI_INTERFACE_RESERVED = 0,
+ IPMI_INTERFACE_RESERVED,
IPMI_INTERFACE_KCS,
IPMI_INTERFACE_SMIC,
IPMI_INTERFACE_BT,
--
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Gerrit-Change-Id: I1a5aa9762051780b67013f67f101112fc7a0bf6e
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4
7
Change in coreboot[master]: arch/riscv: Fix cpu capabilities detection function
by Xiang Wang (Code Review) Aug. 7, 2023
by Xiang Wang (Code Review) Aug. 7, 2023
Aug. 7, 2023
Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36944 )
Change subject: arch/riscv: Fix cpu capabilities detection function
......................................................................
arch/riscv: Fix cpu capabilities detection function
On some platforms, misa may not be implemented. On such a platform,
reading misa will get zero. At this time, soc is required to
implement a non-standard method to detect the soc function.
This modification add interfaces for non-standard function.
The MXL field of misa is always at the highest two bits, whether it
is a 32-bit 64-bit or a 128-bit machine. Therefore, this modification
fixes the use of a fixed offset to detect the machine length.
Change-Id: Id24f77bf21ef0c7c300faa477d67294d093eeecc
Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org>
---
M src/arch/riscv/Makefile.inc
A src/arch/riscv/cpu.c
M src/arch/riscv/include/arch/cpu.h
3 files changed, 87 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/36944/1
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 0038523..0679be73 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -60,6 +60,7 @@
bootblock-y += trap_util.S
bootblock-y += trap_handler.c
bootblock-y += fp_asm.S
+bootblock-y += cpu.c
bootblock-y += misaligned.c
bootblock-y += sbi.c
bootblock-y += mcall.c
@@ -100,6 +101,7 @@
romstage-y += boot.c
romstage-y += romstage.c
romstage-y += misc.c
+romstage-y += cpu.c
romstage-$(ARCH_RISCV_PMP) += pmp.c
romstage-y += smp.c
romstage-y += \
@@ -137,6 +139,7 @@
ramstage-y += trap_util.S
ramstage-y += trap_handler.c
ramstage-y += fp_asm.S
+ramstage-y += cpu.c
ramstage-y += misaligned.c
ramstage-y += sbi.c
ramstage-y += virtual_memory.c
diff --git a/src/arch/riscv/cpu.c b/src/arch/riscv/cpu.c
new file mode 100644
index 0000000..69556f3
--- /dev/null
+++ b/src/arch/riscv/cpu.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+
+
+__weak int soc_supports_extension(char ext)
+{
+ return 0;
+}
+
+__weak int soc_machine_xlen(void)
+{
+ return -1;
+}
diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h
index c62199e..72a8a69 100644
--- a/src/arch/riscv/include/arch/cpu.h
+++ b/src/arch/riscv/include/arch/cpu.h
@@ -18,6 +18,7 @@
#include <arch/encoding.h>
#include <device/device.h>
+#include <commonlib/compiler.h>
#define asmlinkage
@@ -42,15 +43,68 @@
uint8_t riscv_model;
};
+/* If the SOC does not implement misa, the read misa will be zero.
+ * Such SOC requires a non-standard mechanism to detect ISA extensions.
+ * If the soc does not implement misa, implement this function.
+ * */
+int soc_supports_extension(char ext);
+
static inline int supports_extension(char ext)
{
- return read_csr(misa) & (1 << (ext - 'A'));
+ uintptr_t isa = read_csr(misa);
+ if (isa)
+ return isa & (1 << (ext - 'A'));
+ else
+ return soc_supports_extension(ext);
}
+/* If the SOC does not implement misa, the read misa will be zero.
+ * Such SOC requires a non-standard mechanism to detect machine XLEN.
+ * If the soc does not implement misa, implement this function.
+ * */
+int soc_machine_xlen(void);
+
static inline int machine_xlen(void)
{
- int mxl = (read_csr(misa) >> (__riscv_xlen - 2)) & 3;
- return (1 << mxl) * 16;
+ int r;
+ asm (
+ "csrr t0, misa\n\t"
+ "bnez t0, 1f\n\t"
+ "call soc_machine_xlen\n\t"
+ "j 2f\n"
+ "1:\n\t"
+ "srli t1, t0, 30\n\t"
+ "srli t1, t1, 32\n\t"
+ "srli t1, t1, 32\n\t"
+ "srli t1, t1, 32\n\t"
+ "andi t1, t1, 3\n\t"
+ "li t2, 3\n\t"
+ "bne t1, t2, 1f\n\t"
+ "li %0, 128\n\t"
+ "j 2f\n"
+ "1:\n\t"
+ "srli t1, t0, 30\n\t"
+ "srli t1, t1, 32\n\t"
+ "andi t1, t1, 3\n\t"
+ "li t2, 2\n\t"
+ "bne t1, t2, 1f\n\t"
+ "li %0, 64\n\t"
+ "j 2f\n"
+ "1:\n\t"
+ "srli t1, t0, 30\n\t"
+ "andi t1, t1, 3\n\t"
+ "li t2, 1\n\t"
+ "bne t1, t2, 1f\n\t"
+ "li %0, 32\n\t"
+ "j 2f\n"
+ "1:\n\t"
+ "li %0, -1\n"
+ "2:"
+ : "=r"(r)
+ :
+ : "t0", "t1", "t2", "ra"
+ );
+ return r;
}
struct cpu_info *cpu_info(void);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id24f77bf21ef0c7c300faa477d67294d093eeecc
Gerrit-Change-Number: 36944
Gerrit-PatchSet: 1
Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org>
Gerrit-MessageType: newchange
2
11
Change in coreboot[master]: arch/riscv: Add soc interface to get mtime frequency
by Xiang Wang (Code Review) Aug. 7, 2023
by Xiang Wang (Code Review) Aug. 7, 2023
Aug. 7, 2023
Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37549 )
Change subject: arch/riscv: Add soc interface to get mtime frequency
......................................................................
arch/riscv: Add soc interface to get mtime frequency
The mtime clock is not microseconds, but is determined by the
specific platform. So timer_monotonic_get needs to know the
frequency of mtime.
Change-Id: I7d11d3ae73bc5dc81f2239829e1c5c7b4624800e
Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org>
---
M src/arch/riscv/arch_timer.c
M src/arch/riscv/include/mcall.h
M src/mainboard/emulation/qemu-riscv/Makefile.inc
M src/mainboard/emulation/qemu-riscv/clint.c
M src/mainboard/emulation/spike-riscv/Makefile.inc
M src/mainboard/emulation/spike-riscv/clint.c
M src/soc/sifive/fu540/clint.c
7 files changed, 25 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/37549/1
diff --git a/src/arch/riscv/arch_timer.c b/src/arch/riscv/arch_timer.c
index 55b1f72..1353abd 100644
--- a/src/arch/riscv/arch_timer.c
+++ b/src/arch/riscv/arch_timer.c
@@ -24,5 +24,6 @@
{
if (HLS()->time == NULL)
die("time not set in HLS");
- mono_time_set_usecs(mt, (long)read64((void *)(HLS()->time)));
+ long time = (long)read64((void *)(HLS()->time));
+ mono_time_set_usecs(mt, time / (mtime_frequency() / 1000000));
}
diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h
index d7d67ce..24b46a7 100644
--- a/src/arch/riscv/include/mcall.h
+++ b/src/arch/riscv/include/mcall.h
@@ -93,6 +93,12 @@
*/
void set_msip(int hartid, int val);
+/*
+ * This function is used to get frequency of mtime,
+ * need be implement by SoC code
+ */
+long mtime_frequency(void);
+
#endif // __ASSEMBLER__
#endif
diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc
index eb99544..2ca75fd 100644
--- a/src/mainboard/emulation/qemu-riscv/Makefile.inc
+++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc
@@ -19,6 +19,7 @@
romstage-y += romstage.c
romstage-y += uart.c
romstage-y += rom_media.c
+romstage-y += clint.c
ramstage-y += uart.c
ramstage-y += rom_media.c
diff --git a/src/mainboard/emulation/qemu-riscv/clint.c b/src/mainboard/emulation/qemu-riscv/clint.c
index 367d48d..96d0f1d 100644
--- a/src/mainboard/emulation/qemu-riscv/clint.c
+++ b/src/mainboard/emulation/qemu-riscv/clint.c
@@ -23,3 +23,8 @@
HLS()->time = (uint64_t *)(QEMU_VIRT_CLINT + 0xbff8);
HLS()->timecmp = (uint64_t *)(QEMU_VIRT_CLINT + 0x4000 + 8 * hart_id);
}
+
+long mtime_frequency(void)
+{
+ return 1000000;
+}
diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc
index 38977b6..bfeaf58 100644
--- a/src/mainboard/emulation/spike-riscv/Makefile.inc
+++ b/src/mainboard/emulation/spike-riscv/Makefile.inc
@@ -18,6 +18,7 @@
romstage-y += romstage.c
romstage-y += uart.c
romstage-y += rom_media.c
+romstage-y += clint.c
ramstage-y += uart.c
ramstage-y += rom_media.c
ramstage-y += clint.c
diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c
index 7ad3f5a..4c2b8fa 100644
--- a/src/mainboard/emulation/spike-riscv/clint.c
+++ b/src/mainboard/emulation/spike-riscv/clint.c
@@ -24,3 +24,8 @@
HLS()->time = (uint64_t *)(SPIKE_CLINT_BASE + 0xbff8);
HLS()->timecmp = (uint64_t *)(SPIKE_CLINT_BASE + 0x4000 + 8 * hart_id);
}
+
+long mtime_frequency(void)
+{
+ return 1000000;
+}
diff --git a/src/soc/sifive/fu540/clint.c b/src/soc/sifive/fu540/clint.c
index 699273e..09ec719 100644
--- a/src/soc/sifive/fu540/clint.c
+++ b/src/soc/sifive/fu540/clint.c
@@ -29,3 +29,8 @@
{
write32((void *)(FU540_CLINT + 4 * (uintptr_t)hartid), !!val);
}
+
+long mtime_frequency(void)
+{
+ return 1000000;
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7d11d3ae73bc5dc81f2239829e1c5c7b4624800e
Gerrit-Change-Number: 37549
Gerrit-PatchSet: 1
Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org>
Gerrit-MessageType: newchange
2
6
Change in coreboot[master]: Inicial device tree for Microtech etabpro Platform Intel GLK Tablet w...
by Miroslaw Kocur (Code Review) Aug. 7, 2023
by Miroslaw Kocur (Code Review) Aug. 7, 2023
Aug. 7, 2023
Miroslaw Kocur has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39277 )
Change subject: Inicial device tree for Microtech etabpro Platform Intel GLK Tablet with the stylus and attachable keyboard
......................................................................
Inicial device tree for Microtech etabpro
Platform Intel GLK
Tablet with the stylus and attachable keyboard
Not working so far
Changes:
- clean code
Change-Id: Ib9d755902f28b51823e16c228ee5d4fc13849798
Signed-off-by: mirek190 <mirek190(a)gmail.com>
---
A src/mainboard/microtech/Kconfig
A src/mainboard/microtech/Kconfig.name
A src/mainboard/microtech/etabpro/Kconfig
A src/mainboard/microtech/etabpro/Kconfig.name
A src/mainboard/microtech/etabpro/Makefile.inc
A src/mainboard/microtech/etabpro/board_info.txt
A src/mainboard/microtech/etabpro/bootblock.c
A src/mainboard/microtech/etabpro/devicetree.cb
A src/mainboard/microtech/etabpro/dptf.asl
A src/mainboard/microtech/etabpro/dsdt.asl
A src/mainboard/microtech/etabpro/etab.fmd
A src/mainboard/microtech/etabpro/gpio.c
A src/mainboard/microtech/etabpro/gpio.h
A src/mainboard/microtech/etabpro/mainboard.c
A src/mainboard/microtech/etabpro/memory.c
A src/mainboard/microtech/etabpro/romstage.c
A src/mainboard/microtech/etabpro/touchpad.asl
A src/mainboard/microtech/etabpro/touchpanel.asl
A src/mainboard/microtech/etabpro/variants.h
19 files changed, 1,561 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/39277/1
diff --git a/src/mainboard/microtech/Kconfig b/src/mainboard/microtech/Kconfig
new file mode 100644
index 0000000..a757136
--- /dev/null
+++ b/src/mainboard/microtech/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_MICROTECH
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/microtech/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/microtech/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "MCROTECH"
+
+endif # VENDOR_MICROTECH
diff --git a/src/mainboard/microtech/Kconfig.name b/src/mainboard/microtech/Kconfig.name
new file mode 100644
index 0000000..bc37123
--- /dev/null
+++ b/src/mainboard/microtech/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_MICROTECH
+ bool "MICROTECH"
diff --git a/src/mainboard/microtech/etabpro/Kconfig b/src/mainboard/microtech/etabpro/Kconfig
new file mode 100644
index 0000000..6c91dff
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/Kconfig
@@ -0,0 +1,66 @@
+if BOARD_MICROTECH_ETABPRO
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SOC_INTEL_GLK
+ select BOARD_ROMSIZE_KB_8192
+ select DRIVERS_I2C_GENERIC
+ select DRIVERS_I2C_HID
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_LPSS_UART_FOR_CONSOLE
+ select MAINBOARD_HAS_LPC_TPM
+# Blobs
+# select NEED_IFWI
+# select HAVE_IFD_BIN
+# config for GLK INTEL_EC
+# Not sure is VBOOT_NO_BOARD_SUPPORT is needed to work coreboot on GLK. Without it we got error if I choose GLK INTEL_EC...
+ select EC_ACPI
+# select VBOOT_NO_BOARD_SUPPORT
+
+
+config IFWI_FILE
+ string
+ default "3rdparty/blobs/mainboard/microtech/etabpro/ifwi.bin"
+
+config IFD_BIN_PATH
+ string
+ default "3rdparty/blobs/mainboard/microtech/etabpro/ifd.bin"
+
+config BASEBOARD_GLKRVP_LAPTOP
+ def_bool y
+ select SYSTEM_TYPE_LAPTOP
+
+#config VBOOT
+# select HAS_RECOVERY_MRC_CACHE
+# select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
+
+config FMDFILE
+ string
+ default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/etab.fmd"
+
+config MAINBOARD_DIR
+ string
+ default "microtech/etabpro"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "etabpro"
+
+config MAINBOARD_FAMILY
+ string
+ default "Intel_GLK"
+
+config MAX_CPUS
+ int
+ default 2
+
+config UART_FOR_CONSOLE
+ int
+ default 2
+
+config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE
+ bool
+ default y
+
+endif # BOARD_MICROTECH_ETABPRO
diff --git a/src/mainboard/microtech/etabpro/Kconfig.name b/src/mainboard/microtech/etabpro/Kconfig.name
new file mode 100644
index 0000000..ab1d1e7
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_MICROTECH_ETABPRO
+ bool "etabpro"
diff --git a/src/mainboard/microtech/etabpro/Makefile.inc b/src/mainboard/microtech/etabpro/Makefile.inc
new file mode 100644
index 0000000..3fafe9c
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += bootblock.c
+
+ramstage-y += mainboard.c
+
+bootblock-y += gpio.c
+romstage-y += memory.c
+ramstage-y += gpio.c
+
+smm-y += gpio.c
+
diff --git a/src/mainboard/microtech/etabpro/board_info.txt b/src/mainboard/microtech/etabpro/board_info.txt
new file mode 100644
index 0000000..983b2df
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Microtech
+Board name: etabpro glk board 8 MB bios rom
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/microtech/etabpro/bootblock.c b/src/mainboard/microtech/etabpro/bootblock.c
new file mode 100644
index 0000000..f0a641c
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/bootblock.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "variants.h"
+#include <bootblock_common.h>
+#include <intelblocks/lpc_lib.h>
+#include <soc/gpio.h>
+
+void bootblock_mainboard_init(void)
+{
+ const struct pad_config *pads;
+ size_t num;
+
+ lpc_configure_pads();
+ pads = variant_early_gpio_table(&num);
+ gpio_configure_pads(pads, num);
+}
diff --git a/src/mainboard/microtech/etabpro/devicetree.cb b/src/mainboard/microtech/etabpro/devicetree.cb
new file mode 100644
index 0000000..e132f14
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/devicetree.cb
@@ -0,0 +1,285 @@
+chip soc/intel/apollolake
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ register "pcie_rp_clkreq_pin[2]" = "3" # wifi/bt
+ # Disable unused clkreq of PCIe root ports
+ register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
+
+ # Set de-emphasis to disabled for PCIE WiFI (Thunderpeak)
+ # as it is required for detection
+ register "pcie_rp_deemphasis_enable[2]" = "0"
+ # Set de-emphasis to default (enabled) for remaining ports
+ register "pcie_rp_deemphasis_enable[0]" = "1"
+ register "pcie_rp_deemphasis_enable[1]" = "1"
+ register "pcie_rp_deemphasis_enable[3]" = "1"
+ register "pcie_rp_deemphasis_enable[4]" = "1"
+ register "pcie_rp_deemphasis_enable[5]" = "1"
+
+ # GPIO for PERST_0 (WLAN_PE_RST)
+ register "prt0_gpio" = "GPIO_164"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route, i.e., if this route changes then the affected GPE
+ # offset bits also need to be changed. This sets the PMC register
+ # GPE_CFG fields.
+ # DW1 is used by:
+ # - GPIO_63 - H1_PCH_INT_ODL
+ # DW2 is used by:
+ # - GPIO_141 - EC_PCH_WAKE_ODL
+ # - GPIO_142 - TRACKPAD_INT2_1V8_ODL
+ # - GPIO_144 - PEN_EJECT_ODL
+ # DW3 is used by:
+ # - GPIO_117 - LTE_WAKE_ODL
+ # - GPIO_119 - WLAN_PCIE_WAKE_ODL
+ register "gpe0_dw1" = "PMC_GPE_NW_63_32"
+ register "gpe0_dw2" = "PMC_GPE_N_95_64"
+ register "gpe0_dw3" = "PMC_GPE_N_63_32"
+
+ # PL1 override 10000 mW: Due to error in the energy calculation for
+ # current VR solution. Experiments show that SoC TDP max (6W) can
+ # be reached when RAPL PL1 is set to 10W.
+ register "tdp_pl1_override_mw" = "10000"
+ # Set RAPL PL2 to 15W.
+ register "tdp_pl2_override_mw" = "15000"
+
+ # Minimum SLP S3 assertion width 28ms.
+ register "slp_s3_assertion_width_usecs" = "28000"
+
+ # Enable lpss s0ix
+ register "lpss_s0ix_enable" = "1"
+
+ # Enable DPTF
+ register "dptf_enable" = "1"
+
+ # Enable Audio Clock and Power gating
+ register "hdaudio_clk_gate_enable" = "1"
+ register "hdaudio_pwr_gate_enable" = "1"
+ register "hdaudio_bios_config_lockdown" = "1"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| I2C0 | Digitizer |
+ #| I2C5 | Audio |
+ #| I2C6 | Trackpad |
+ #| I2C7 | Touchscreen |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 152,
+ .fall_time_ns = 30,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 104,
+ .fall_time_ns = 52,
+ },
+ .i2c[6] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 114,
+ .fall_time_ns = 164,
+ .data_hold_time_ns = 350,
+ },
+ .i2c[7] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 76,
+ .fall_time_ns = 164,
+ },
+ }"
+
+ register "pnp_settings" = "PNP_PERF_POWER"
+
+ device domain 0 on
+ device pci 00.0 on end # - Host Bridge
+ device pci 00.1 on end # - DPTF
+ device pci 00.2 off end # - NPK
+ device pci 02.0 off end # - Gen
+ device pci 03.0 off end # - Iunit
+ chip drivers/intel/wifi
+ register "wake" = "GPE0A_CNVI_PME_STS"
+ device pci 0c.0 on end # - CNVi
+ end
+ device pci 0d.0 off end # - P2SB
+ device pci 0d.1 off end # - PMC
+ device pci 0d.2 off end # - Fast SPI
+ device pci 0d.3 off end # - Shared SRAM
+ device pci 0e.0 on
+ chip drivers/generic/max98357a
+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)"
+ register "sdmode_delay" = "5"
+ device generic 0 on end
+ end
+ end # - Audio
+ device pci 0f.0 on end # - Heci1
+ device pci 0f.1 off end # - Heci2
+ device pci 0f.2 off end # - Heci3
+ device pci 11.0 off end # - ISH
+ device pci 12.0 on end # - SATA
+ device pci 13.0 on
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_DW3_11"
+ device pci 00.0 on end
+ end
+ end # - PCIe-A 0 Onboard M2 Slot(Wifi)
+ device pci 13.1 on end # - PCIe-A 1
+ device pci 13.2 on end # - PCIe-A 2
+ device pci 13.3 off end # - PCIe-A 3
+ device pci 14.0 off end # - PCIe-B 0
+ device pci 14.1 off end # - PCIe-B 1
+ device pci 15.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""Root Hub""
+ register "type" = "UPC_TYPE_HUB"
+ device usb 0.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 1)"
+ device usb 2.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-A Port""
+ register "type" = "UPC_TYPE_A"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
+ device usb 2.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)"
+ device usb 2.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-A Port""
+ register "type" = "UPC_TYPE_A"
+ register "group" = "ACPI_PLD_GROUP(2, 2)"
+ device usb 2.3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(2, 1)"
+ device usb 2.4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""SDCard""
+ register "type" = "UPC_TYPE_EXPRESSCARD"
+ device usb 2.5 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""User Facing Camera""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.6 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""World Facing Camera""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.7 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)"
+ device usb 2.8 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 1)"
+ device usb 3.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-A Port""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
+ device usb 3.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-A Port""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(2, 2)"
+ device usb 3.3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(2, 1)"
+ device usb 3.4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""SDCard""
+ register "type" = "UPC_TYPE_EXPRESSCARD"
+ device usb 3.5 on end
+ end
+ end
+ end
+ end # - XHCI
+ device pci 15.1 off end # - XDCI
+ device pci 16.0 on end # - I2C 0
+ device pci 16.1 on end # - I2C 1
+ device pci 16.2 on end # - I2C 2
+ device pci 16.3 on end # - I2C 3
+ device pci 17.0 on end # - I2C 4
+ device pci 17.1 on end # - I2C 5
+ device pci 17.2 on end # - I2C 6
+ device pci 17.3 on end # - I2C 7
+ device pci 18.0 on end # - UART 0
+ device pci 18.1 on end # - UART 1
+ device pci 18.2 on end # - UART 2
+ device pci 18.3 on end # - UART 3
+ device pci 19.0 on
+ chip drivers/spi/acpi
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "compat_string" = ""google,cr50""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_63_IRQ)"
+ device spi 0 on end
+ end
+ end # - GSPI 0
+ device pci 19.1 on end # - SPI 1
+ device pci 19.2 on end # - SPI 2
+ device pci 1a.0 off end # - PWM
+ device pci 1c.0 on end # - eMMC
+ device pci 1e.0 on end # - SDIO
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # - ESPI
+ device pci 1f.1 on end # - SMBUS
+ end
+
+ # FSP provides UPD interface to execute IPC command. PMIC has
+ # I2C_Slave_Address (31:24): 0x5E, Register_Offset (23:16): 0x43,
+ # RegOrValue (15:8): 0x2 and RegAndValue (7:0) 0xF8.
+ # The register is defined as: D[7:3] RSVD, D[2:0] PWROKDELAY.
+ # uint8 RegOrValue, RegAndValue, PmicReadReg
+ # RegOrValue = (UINT8)((PmicPmcIpcCtrl >> 8) & 0Xff);
+ # RegAndValue = (UINT8)(PmicPmcIpcCtrl & 0Xff);
+ # PmicReadReg &= RegAndValue;
+ # PmicReadReg |= RegOrValue;
+ # PmicReadReg value will be programmed into PMIC D[2:0] PWROKDELAY field
+ # and D[7:3] RSVD will not be impacted.
+
+ # Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay
+ # from 100ms to 10ms.
+ # PWROKDELAY[2:0]: 000=2.5ms, 001=5.0ms, 010=10ms, 011=15ms, 100=20ms,
+ # 101=50ms, 110=75ms, 111=100ms (default)
+ register "PmicPmcIpcCtrl" = "0x5e4302f8"
+end
diff --git a/src/mainboard/microtech/etabpro/dptf.asl b/src/mainboard/microtech/etabpro/dptf.asl
new file mode 100644
index 0000000..f61f0b6
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/dptf.asl
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 90
+
+#define DPTF_TSR0_SENSOR_ID 0
+#define DPTF_TSR0_SENSOR_NAME "Battery"
+#define DPTF_TSR0_PASSIVE 48
+#define DPTF_TSR0_CRITICAL 70
+
+#define DPTF_TSR1_SENSOR_ID 1
+#define DPTF_TSR1_SENSOR_NAME "Ambient"
+#define DPTF_TSR1_PASSIVE 60
+#define DPTF_TSR1_CRITICAL 70
+
+#define DPTF_TSR2_SENSOR_ID 2
+#define DPTF_TSR2_SENSOR_NAME "Charger"
+#define DPTF_TSR2_PASSIVE 55
+#define DPTF_TSR2_CRITICAL 100
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 2 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 1600, /* PowerLimitMinimum */
+ 12000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 6000, /* PowerLimitMinimum */
+ 8000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
diff --git a/src/mainboard/microtech/etabpro/dsdt.asl b/src/mainboard/microtech/etabpro/dsdt.asl
new file mode 100644
index 0000000..89a1ac8
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/dsdt.asl
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "gpio.h"
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ /* global NVS and variables */
+ #include <soc/intel/apollolake/acpi/globalnvs.asl>
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/apollolake/acpi/northbridge.asl>
+ #include <soc/intel/apollolake/acpi/southbridge.asl>
+ #include <soc/intel/apollolake/acpi/pch_hda.asl>
+ }
+ }
+
+ /* Dynamic Platform Thermal Framework */
+ Scope (\_SB)
+ {
+ /* Per board variant specific definitions. */
+// #include "dptf.asl"
+ /* Include soc specific DPTF changes */
+// #include <soc/intel/apollolake/acpi/dptf.asl>
+ /* Include common dptf ASL files */
+// #include <soc/intel/common/acpi/dptf/dptf.asl>
+ }
+}
diff --git a/src/mainboard/microtech/etabpro/etab.fmd b/src/mainboard/microtech/etabpro/etab.fmd
new file mode 100644
index 0000000..c71088a
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/etab.fmd
@@ -0,0 +1,35 @@
+FLASH 8M {
+ SI_DESC 0x1000
+ SI_BIOS {
+ IFWI 0x2ff000
+ OBBP {
+ FMAP 0x1000
+ RO_FRID 0x40
+ GBB 0x40000
+ UNIFIED_MRC_CACHE 0x21000 {
+ RECOVERY_MRC_CACHE 0x10000
+ RW_MRC_CACHE 0x10000
+ RW_VAR_MRC_CACHE 0x1000
+ }
+ CONSOLE 0x20000
+ COREBOOT(CBFS)
+ SIGN_CSE 0x2000
+ BIOS_UNUSABLE 0x4000
+ }
+ }
+ RW_SECTION_A 0x70100 {
+ VBLOCK_A 0x10000
+ FW_MAIN_A(CBFS) 0x60000
+ RW_FWID_A 0x100
+ }
+ RW_SECTION_B 0x70100 {
+ VBLOCK_B 0x10000
+ FW_MAIN_B(CBFS) 0x60000
+ RW_FWID_B 0x100
+ }
+ SI_DEVICEEXT 0x101000 {
+ DEVICE_EXTENSION 0x100000
+ UNUSED_HOLE 0x1000
+ }
+}
+
diff --git a/src/mainboard/microtech/etabpro/gpio.c b/src/mainboard/microtech/etabpro/gpio.c
new file mode 100644
index 0000000..71c0d16
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/gpio.c
@@ -0,0 +1,286 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+#include "variants.h"
+#include <gpio.h>
+#include <commonlib/helpers.h>
+
+/*
+ * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
+ * table found in EDS vol 1, but some pins aren't grouped functionally in
+ * the table so those were moved for more logical grouping.
+ */
+static const struct pad_config gpio_table[] = {
+/* NORTHWEST COMMUNITY GPIOS */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_0, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TCK */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_1, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TRST_B */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_2, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TMS */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_3, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDI */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_4, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDO */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_5, UP_20K, DEEP, NF1, IGNORE, ENPU), /* JTAGX */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_6, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PREQ_B */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PRDY_B */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_CLK_VNN */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA0_VNN */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA1_VNN */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA2_VNN */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA3_VNN */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA4_VNN */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA5_VNN */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA6_VNN */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA7_VNN */
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_17, 1, DEEP, UP_20K, TxDRxE, SAME),/*Ec-to-SOC CS Wake */
+ PAD_CFG_GPI_APIC_IOS(GPIO_18, UP_20K, DEEP, LEVEL, NONE, IGNORE, SAME),/* Touch Pad Interrupt */
+ PAD_CFG_GPI_APIC_IOS(GPIO_19, UP_20K, DEEP, EDGE_SINGLE, NONE, TxDRxE, SAME),/*PMIC Interrupt*/
+ PAD_CFG_GPI_APIC_IOS(GPIO_20, UP_20K, DEEP, LEVEL, INVERT, IGNORE, SAME),/* Audio Codec Interrupt*/
+ PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */
+ PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */
+ PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */
+ PAD_CFG_GPO_GPIO_DRIVER(GPIO_24, 1, DEEP, DN_20K),
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_25, 1, DEEP, UP_20K, TxLASTRxE, SAME),/*WWAN /RF_KILL_GPS*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/* NFC Interrupt */
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_27, 1, DEEP, NONE, IGNORE, DISPUPD),/* RF_KILL_WiFi/WiFi_Disable */
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_28, 1, DEEP, UP_20K, TxLASTRxE, DISPUPD),/* RF_KILL_BT/BT_Disable */
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_29, 1, DEEP, UP_20K, HIZCRx0, DISPUPD),/* Codec Power Down: Output/ISH_GPIO_3*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_30, DN_20K, DEEP, NF1), /* ISH_GPIO_4 */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_31, DN_20K, DEEP, NF1), /* ISH_GPIO_5 */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_32, DN_20K, DEEP, NF1), /* ISH_GPIO_6 */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_33, DN_20K, DEEP, NF1), /* ISH_GPIO_7 */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_34, DN_20K, DEEP, NF1), /* ISH_GPIO_8/SUSCLK2 (1.8V) */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_35, UP_20K, DEEP, NF6), /* BSSB_CLK */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_36, UP_20K, DEEP, NF6), /* BSSB_DI */
+ PAD_CFG_GPI_SCI_IOS(GPIO_37, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/*Runtime SCI */
+ PAD_CFG_GPI_SCI_IOS(GPIO_38, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/*Wake SCI */
+ PAD_CFG_GPI_APIC_IOS(GPIO_39, DN_20K, DEEP, LEVEL, NONE, IGNORE, SAME),/* Finger Print Sensor Interrupt (DRDY) */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_40, UP_20K, DEEP, NF6),/*IERR (USB Camera Power Enable)*/
+ PAD_CFG_GPI_SMI_IOS(GPIO_41, UP_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME),/*SOC_EXTSMI_N */
+ PAD_CFG_NF(GPIO_42, DN_20K, DEEP, NF1), /* GP_INTD_DSI_TE1 */
+ PAD_CFG_NF(GPIO_43, DN_20K, DEEP, NF1), /* GP_INTD_DSI_TE2 */
+ PAD_CFG_NF(GPIO_44, UP_20K, DEEP, NF1), /* USB_OC0_B */
+ PAD_CFG_NF(GPIO_45, UP_20K, DEEP, NF1), /* USB_OC1_B */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, UP_20K, DEEP, NF1, HIZCRx1, SAME), /* DSI_I2C_SDA */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_47, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* DSI_I2C_SCL */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, UP_1K, DEEP, NF1), /* PMC_I2C_SDA */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, UP_1K, DEEP, NF1), /* PMC_I2C_SCL */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, UP_2K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C0_SDA - Audio Codec*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, UP_2K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C0_SCL - Audio Codec */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C1_SDA - NFC */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C1_SCL - NFC */
+ PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_54, UP_20K, DEEP, HIZCRx1, ENPU),/*LPSS_I2C2_SDA*/
+ PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_55, UP_20K, DEEP, HIZCRx1, ENPU),/*LPSS_I2C2_SCL*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* I2C3-SDA - DBG (PSS, SINAI2, MIPI) */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*I2C3-SCL - DBG (PSS, SINAI2, MIPI) */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_58, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*I2C4-SDA - Touch Pad*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_59, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*I2C4-SCL - Touch Pad*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-RXD - M.2dGNSS */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-TXD - M.2dGNSS */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_62, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-RTS_B - M.2 dGNSS */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_63, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-CTS_B - M.2 dGNSS */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPSS_UART2_RXD*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),/*LPSS_UART2_TXD*/
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, TxDRxE, DISPUPD),/*RF_KILL_WWAN */
+#if CONFIG(TPM_ON_FAST_SPI)
+ PAD_CFG_GPI_INT(GPIO_67, UP_20K, DEEP, LEVEL),/*SPI TPM Interrupt */
+#endif
+ PAD_CFG_NF(GPIO_68, UP_20K, DEEP, NF1),/*PMC_SPI_FS0*/
+ PAD_CFG_GPI_APIC(GPIO_69, DN_20K, DEEP, EDGE_SINGLE, NONE),/*SIM Detect*/
+ PAD_CFG_NF(GPIO_70, DN_20K, DEEP, NF1),/*PMC_SPI_FS2*/
+ PAD_CFG_NF(GPIO_71, DN_20K, DEEP, NF1),/*PMC_SPI_RXD*/
+ PAD_CFG_NF(GPIO_72, DN_20K, DEEP, NF1),/*PMC_SPI_TXD*/
+ PAD_CFG_NF(GPIO_73, DN_20K, DEEP, NF1),/*PMC_SPI_CLK*/
+ PAD_CFG_NF(GPIO_74, DN_20K, DEEP, NF1),/*THERMTRIP_B*/
+ PAD_CFG_NF_IOSSTATE(GPIO_75, UP_20K, DEEP, NF1, HIZCRx1),/*PROCHOT_B*/
+ PAD_CFG_NF_IOSSTATE(GPIO_211, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC_RST_B*/
+ PAD_CFG_GPI_GPIO_DRIVER(GPIO_212, UP_20K, DEEP),/*Touch Panel Int*/
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 1, DEEP, NONE, HIZCRx0, SAME),/*DNX LED - CSE owned*/
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_214, 1, DEEP, NONE, HIZCRx0, SAME),/*LAN Isolate*/
+/* NORTH COMMUNITY GPIOS */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_76, UP_20K, DEEP, NF1),/*SVID Alert*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_77, UP_20K, DEEP, NF1),/* SVID Data */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_78, UP_20K, DEEP, NF1),/* SVID Clk */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_79, NATIVE, DEEP, NF1),/* Finger Print Sensor */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_80, NATIVE, DEEP, NF1),/* Finger Print Sensor CS */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_81, NONE, DEEP, NF3),/* FST_SPI_CS2_B - TPM */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_82, NATIVE, DEEP, NF1),/* Finger Print Sensor */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_83, NATIVE, DEEP, NF1),/* Finger Print Sensor */
+ PAD_CFG_NF_IOSSTATE(GPIO_84, NONE, DEEP, NF3, HIZCRx1),/* SPI iTouch*/
+ PAD_CFG_NF_IOSSTATE(GPIO_85, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch CS*/
+ PAD_CFG_NF_IOSSTATE(GPIO_86, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/
+ PAD_CFG_NF_IOSSTATE(GPIO_87, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/
+ PAD_CFG_NF_IOSSTATE(GPIO_88, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/
+ PAD_CFG_NF_IOSSTATE(GPIO_89, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_90, NATIVE, DEEP, NF1),/*Function 1: FST SPI Boot Flash CS*/
+ PAD_CFG_GPIO_HI_Z(GPIO_91, NATIVE, DEEP, IGNORE, SAME),/*FST_SPI_CS1_B*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_92, DN_20K, DEEP, NF1),/*FST_SPI_MOSI_IO0*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_93, NATIVE, DEEP, NF1),/*FST_SPI_MISO_IO1*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_94, NATIVE, DEEP, NF1),/*FST_SPI_IO2*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_95, NATIVE, DEEP, NF1),/*FST_SPI_IO3*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_96, NATIVE, DEEP, NF1),/*FST_SPI_CLK*/
+ PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1),/*FST_SPI_CLK_FB*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_98, NONE, DEEP, NF1),/*PMU_PLTRST_B*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_99, UP_20K, DEEP, NF1),/*PMU_PWRBTN_B*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/*PMU_SLP_S0_B*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/*PMU_SLP_S3_B*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/*PMU_SLP_S4_B*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/*SUSPWRDNACK*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_104, UP_20K, DEEP, NF1),/*EMMC_DNX_PWR_EN_B*/
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx0RxDCRx0, SAME),/*x4 Slot-2 Reset*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_106, UP_20K, DEEP, NF1),/*PMU_BATLOW_B*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_107, UP_20K, DEEP, NF1),/*PMU_RESETBUTTON_B*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_108, NONE, DEEP, NF1),/*PMU_SUSCLK*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_109, NONE, DEEP, NF1),/*SUS_STAT_B*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C5_SDA*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C5_SCL*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C6_SDA*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C6_SCL*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*LPSS_I2C7_SDA*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*LPSS_I2C7_SCL*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_116, UP_20K, DEEP, NF1),/*PCIE_WAKE0_B*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_117, UP_20K, DEEP, NF1),/*PCIE_WAKE1_B*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_118, UP_20K, DEEP, NF1),/*PCIE_WAKE2_B*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_119, UP_20K, DEEP, NF1),/*PCIE_WAKE3_B*/
+ PAD_CFG_GPI(GPIO_120, UP_20K, DEEP), /* unused */
+ PAD_CFG_GPI(GPIO_121, UP_20K, DEEP), /* unused */
+ PAD_CFG_GPI(GPIO_122, UP_20K, DEEP), /* unused */
+ PAD_CFG_NF_IOSSTATE(GPIO_123, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ3_B*/
+ PAD_CFG_NF_IOSSTATE(GPIO_124, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SDA*/
+ PAD_CFG_NF_IOSSTATE(GPIO_125, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SCL*/
+ PAD_CFG_NF_IOSSTATE(GPIO_126, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI1_DDC_SDA*/
+ PAD_CFG_NF_IOSSTATE(GPIO_127, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI1_DDC_SCL*/
+ PAD_CFG_NF_IOSSTATE(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_VDDEN*/
+ PAD_CFG_NF_IOSSTATE(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTEN*/
+ PAD_CFG_NF_IOSSTATE(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTCTL*/
+ PAD_CFG_NF_IOSSTATE(GPIO_131, UP_20K, DEEP, NF1, TxDRxE),/*HV_DDI0_HPD*/
+ PAD_CFG_NF_IOSSTATE(GPIO_132, UP_20K, DEEP, NF1, TxDRxE),/*HV_DDI1_HPD*/
+ PAD_CFG_NF_IOSSTATE(GPIO_133, UP_20K, DEEP, NF1, TxDRxE),/*HV_EDP_HPD*/
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_134, 1, DEEP, UP_20K, IGNORE, SAME),/*Slot-1 Power Enable*/
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_135, 1, DEEP, UP_20K, IGNORE, SAME),/*Slot-2 Power Enable*/
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_136, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*DGPU Power Select*/
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_137, 1, DEEP, UP_20K, IGNORE, SAME),/*slot-1 Reset*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_138, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/*SATA_GP0 (DC RTD3 need)*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_139, UP_20K, DEEP, NF2, TxLASTRxE, DISPUPD),/*SATA_GP1 (ZPODD_DEV_DET)*/
+ PAD_CFG_NF(GPIO_140, UP_20K, DEEP, NF5),/*SATA_DEVSLP0 (DC DEV SLP)*/
+ PAD_CFG_NF_IOSSTATE(GPIO_141, UP_20K, DEEP, NF5, HIZCRx1),/*SATA_DEVSLP1 (ZPODD DEV ATN)*/
+ PAD_CFG_NF_IOSSTATE(GPIO_142, UP_20K, DEEP, NF5, HIZCRx1),/*SATA_LED*/
+ PAD_CFG_GPI_APIC_IOS(GPIO_143, NONE, DEEP, LEVEL, NONE, HIZCRx1, SAME),/*DGPU Power Ok*/
+ PAD_CFG_NF_IOSSTATE(GPIO_144, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_VDDEN*/
+ PAD_CFG_NF_IOSSTATE(GPIO_145, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTEN*/
+ PAD_CFG_NF_IOSSTATE(GPIO_146, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTCTL*/
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_157, 1, DEEP, UP_20K, IGNORE, SAME),/*WWAN_Reset/dGPS Reset*/
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_158, 0, DEEP, DN_20K, IGNORE, SAME),/*NFC_DFU*/
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_159, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*NFC reset*/
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_160, 0, DEEP, UP_20K, IGNORE, SAME),/*SD_MODE for spk*/
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, IGNORE, SAME),/*Touch panel reset*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_BCLK*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_WS_SYNC*/
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*Touch Panel Power Enable*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_SDO*/
+
+/* AUDIO COMMUNITY GPIOS*/
+
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, DN_20K, DEEP, NF2, HIZCRx1, SAME),/*AVS_I2S2_BCLK*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, DN_20K, DEEP, NF2, HIZCRx1, SAME),/*AVS_I2S2_WS_SYNC*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, DN_20K, DEEP, NF2, HIZCRx1, SAME),/* AVS_I2S2_SDI*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, DN_20K, DEEP, NF2, HIZCRx1, SAME),/*AVS_I2S2_SD0*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx1, SAME),/*AVS_I2S1_MCLK*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_171, DN_20K, DEEP, NF1),/*AVS_M_CLK_A1*/
+ PAD_CFG_NF_IOSSTATE(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_M_CLK_B1*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_173, DN_20K, DEEP, NF1),/*AVS_M_DATA_1*/
+ PAD_CFG_NF_IOSSTATE(GPIO_174, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_M_CLK_AB2*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, DN_20K, DEEP, NF1, HIZCRx1, ENPD),/*AVS_M_DATA_2*/
+
+/* SCC COMMUNITY GPIOS */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_176, UP_20K, DEEP, NF1),/*SMB_ALERTB*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_177, UP_20K, DEEP, NF1),/*SMB_CLK*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_178, UP_20K, DEEP, NF1),/*SMB_DATA*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_187, DN_20K, DEEP, NF1),/*SDCARD_LVL_WP*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_179, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD),/*SDCARD_CLK*/
+ PAD_CFG_NF(GPIO_180, DN_20K, DEEP, NF1),/*SDCARD_CLK_FB*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_181, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D0*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_182, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D1*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_183, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D2*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_184, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D3*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_185, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_CMD*/
+ PAD_CFG_NF(GPIO_186, NONE, DEEP, NF1),/*SDCARD_CD_B*/
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_188, 0, DEEP, NONE, TxDRxE, SAME),/*SD Card*/
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_210, 1, DEEP, UP_20K, HIZCRx0, DISPUPD),
+ PAD_CFG_NF_IOSSTATE(GPIO_189, DN_20K, DEEP, NF1, HIZCRx0),/*OSC_CLK_OUT_0*/
+ PAD_CFG_NF_IOSSTATE(GPIO_190, DN_20K, DEEP, NF1, HIZCRx0),/*OSC_CLK_OUT_1*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1),/*CNV_BRI_DT*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1),/*CNV_BRI_RSP*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1),/*CNV_RGI_DT*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1),/*CNV_RGI_RSP*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1),/*CNV_RF_RESET_B*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_196, NONE, DEEP, NF1),/*XTAL_CLKREQ*/
+ PAD_CFG_NF(GPIO_197, DN_20K, DEEP, NF1),/*SDIO_CLK_FB*/
+ PAD_CFG_NF_IOSSTATE(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_CLK*/
+ PAD_CFG_NF(GPIO_199, DN_20K, DEEP, NF1),/*EMMC0_CLK_FB*/
+ PAD_CFG_NF_IOSSTATE(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D0*/
+ PAD_CFG_NF_IOSSTATE(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D1*/
+ PAD_CFG_NF_IOSSTATE(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D2*/
+ PAD_CFG_NF_IOSSTATE(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D3*/
+ PAD_CFG_NF_IOSSTATE(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D4*/
+ PAD_CFG_NF_IOSSTATE(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D5*/
+ PAD_CFG_NF_IOSSTATE(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D6*/
+ PAD_CFG_NF_IOSSTATE(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D7*/
+ PAD_CFG_NF_IOSSTATE(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_CMD*/
+ PAD_CFG_NF_IOSSTATE(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_STROBE*/
+};
+
+const struct pad_config * __weak variant_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+/* GPIOs needed prior to ramstage. */
+static const struct pad_config early_gpio_table[] = {
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_177, UP_20K, DEEP, NF1), /* SMB_CLK */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_178, UP_20K, DEEP, NF1), /* SMB_DATA */
+};
+
+const struct pad_config * __weak
+variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
+
+/* GPIO settings before entering sleep. */
+static const struct pad_config sleep_gpio_table[] = {
+#if 0
+ PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */
+ PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */
+#endif
+};
+
+const struct pad_config * __weak
+variant_sleep_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(sleep_gpio_table);
+ return sleep_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+#if 0
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+#endif
+};
+
+const struct cros_gpio * __weak variant_cros_gpios(size_t *num)
+{
+ *num = ARRAY_SIZE(cros_gpios);
+ return cros_gpios;
+}
diff --git a/src/mainboard/microtech/etabpro/gpio.h b/src/mainboard/microtech/etabpro/gpio.h
new file mode 100644
index 0000000..170e87c
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/gpio.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BASEBOARD_GPIO_H
+#define BASEBOARD_GPIO_H
+
+#include <soc/gpio.h>
+
+/*
+ * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
+ * which is North community
+ */
+#if CONFIG(SOC_ESPI)
+#define EC_SCI_GPI GPE0A_ESPI_SCI_STS
+#else
+#define EC_SCI_GPI GPE0_DW1_05
+#endif
+
+/* EC SMI */
+#define EC_SMI_GPI GPIO_41
+
+#define GPE_EC_WAKE GPE0_DW1_06
+
+/* Memory SKU GPIOs. */
+#define MEM_CONFIG3 GPIO_45
+#define MEM_CONFIG2 GPIO_38
+#define MEM_CONFIG1 GPIO_102
+#define MEM_CONFIG0 GPIO_101
+
+#endif /* BASEBOARD_GPIO_H */
diff --git a/src/mainboard/microtech/etabpro/mainboard.c b/src/mainboard/microtech/etabpro/mainboard.c
new file mode 100644
index 0000000..15e81a9
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/mainboard.c
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <arch/acpi.h>
+#include "variants.h"
+#include <console/console.h>
+#include <device/device.h>
+#include <ec/ec.h>
+#include <nhlt.h>
+#include <soc/gpio.h>
+#include <soc/nhlt.h>
+#include "gpio.h"
+
+static void mainboard_init(void *chip_info)
+{
+ const struct pad_config *pads;
+ size_t num;
+
+ pads = variant_gpio_table(&num);
+ gpio_configure_pads(pads, num);
+
+// mainboard_ec_init();
+}
+
+static unsigned long mainboard_write_acpi_tables(
+ struct device *device, unsigned long current, acpi_rsdp_t *rsdp)
+{
+ uintptr_t start_addr;
+ uintptr_t end_addr;
+ struct nhlt *nhlt;
+
+ start_addr = current;
+
+ nhlt = nhlt_init();
+
+ if (nhlt == NULL)
+ return start_addr;
+
+// variant_nhlt_init(nhlt);
+
+ end_addr = nhlt_soc_serialize(nhlt, start_addr);
+
+ if (end_addr != start_addr)
+ acpi_add_table(rsdp, (void *)start_addr);
+
+ return end_addr;
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+ .init = mainboard_init,
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/microtech/etabpro/memory.c b/src/mainboard/microtech/etabpro/memory.c
new file mode 100644
index 0000000..2a4c43e
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/memory.c
@@ -0,0 +1,143 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include "variants.h"
+#include <gpio.h>
+#include <soc/meminit.h>
+#include "gpio.h"
+
+const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = {
+ /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
+ .phys[LP4_PHYS_CH0A] = {
+ /* DQA[0:7] pins of LPDDR4 module. */
+ .dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 },
+ /* DQA[8:15] pins of LPDDR4 module. */
+ .dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 },
+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 },
+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 },
+ },
+ .phys[LP4_PHYS_CH0B] = {
+ /* DQA[0:7] pins of LPDDR4 module. */
+ .dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 },
+ /* DQA[8:15] pins of LPDDR4 module. */
+ .dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 },
+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 },
+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 },
+ },
+ .phys[LP4_PHYS_CH1A] = {
+ /* DQA[0:7] pins of LPDDR4 module. */
+ .dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 },
+ /* DQA[8:15] pins of LPDDR4 module. */
+ .dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 },
+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 },
+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 },
+ },
+ .phys[LP4_PHYS_CH1B] = {
+ /* DQA[0:7] pins of LPDDR4 module. */
+ .dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 },
+ /* DQA[8:15] pins of LPDDR4 module. */
+ .dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 },
+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 },
+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 },
+ },
+};
+
+static const struct lpddr4_sku skus[] = {
+ /*
+ * K4F6E304HB-MGCJ - both logical channels While the parts
+ * are listed at 16Gb there are 2 ranks per channel so indicate
+ * the density as 8Gb per rank.
+ */
+ [0] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .ch0_dual_rank = 1,
+ .ch1_dual_rank = 1,
+ .part_num = "K4F6E304HB-MGCJ",
+ },
+ /* K4F8E304HB-MGCJ - both logical channels */
+ [1] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .part_num = "K4F8E304HB-MGCJ",
+ },
+ /*
+ * MT53B512M32D2NP-062WT:C - both logical channels. While the parts
+ * are listed at 16Gb there are 2 ranks per channel so indicate
+ * the density as 8Gb per rank.
+ */
+ [2] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .ch0_dual_rank = 1,
+ .ch1_dual_rank = 1,
+ .part_num = "MT53B512M32D2NP",
+ .disable_periodic_retraining = 1,
+ },
+ /* MT53B256M32D1NP-062 WT:C - both logical channels */
+ [3] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .part_num = "MT53B256M32D1NP",
+ .disable_periodic_retraining = 1,
+ },
+ /*
+ * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts
+ * are listed at 16Gb there are 2 ranks per channel so indicate the
+ * density as 8Gb per rank.
+ */
+ [4] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .ch0_dual_rank = 1,
+ .ch1_dual_rank = 1,
+ .part_num = "H9HCNNNBPUMLHR",
+ },
+ /* H9HCNNN8KUMLHR-NLE - both logical channels */
+ [5] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .part_num = "H9HCNNN8KUMLHR",
+ },
+};
+
+static const struct lpddr4_cfg lp4cfg = {
+ .skus = skus,
+ .num_skus = ARRAY_SIZE(skus),
+ .swizzle_config = &baseboard_lpddr4_swizzle,
+};
+
+const struct lpddr4_cfg * __weak variant_lpddr4_config(void)
+{
+ return &lp4cfg;
+}
+
+size_t __weak variant_memory_sku(void)
+{
+ return 0;
+}
diff --git a/src/mainboard/microtech/etabpro/romstage.c b/src/mainboard/microtech/etabpro/romstage.c
new file mode 100644
index 0000000..2c42ee6
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/romstage.c
@@ -0,0 +1,238 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include "variants.h"
+#include <string.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+#define BOARD_ID_GLK_RVP1_DDR4 0x5 /* GLK RVP1 - DDR4 */
+#define BOARD_ID_GLK_RVP2_LP4SD 0x7 /* GLK RVP2 - LP4 Solder Down */
+#define BOARD_ID_GLK_RVP2_LP4 0x8 /* RVP2 - LP4 Socket */
+
+/* DDR4 specific swizzling data start */
+
+/* Channel 0 PHY 0 to DUnit DQ mapping */
+static const uint8_t swizzling_ch0_ddr4[] = {
+ 15, 14, 10, 11, 8, 9, 13, 12, 2, 7, 3, 6, 4, 0, 1, 5,
+ 29, 31, 27, 26, 24, 28, 25, 30, 19, 22, 18, 21, 23, 16, 17, 20,
+};
+
+/* Channel 1 PHY 0 to DUnit DQ mapping */
+static const uint8_t swizzling_ch1_ddr4[] = {
+ 1, 0, 4, 5, 7, 2, 6, 3, 24, 25, 28, 30, 26, 27, 31, 29,
+ 21, 20, 17, 16, 23, 22, 19, 18, 8, 12, 11, 15, 10, 9, 13, 14,
+};
+
+/* Channel 1 PHY 1 to DUnit DQ mapping */
+static const uint8_t swizzling_ch2_ddr4[] = {
+ 14, 12, 9, 13, 10, 15, 11, 8, 1, 3, 7, 5, 2, 6, 0, 4,
+ 27, 24, 29, 28, 30, 26, 31, 25, 19, 20, 18, 22, 16, 21, 23, 17,
+};
+
+/* Channel 0 PHY 1 to DUnit DQ mapping */
+static const uint8_t swizzling_ch3_ddr4[] = {
+ 12, 8, 13, 9, 15, 11, 14, 10, 0, 5, 1, 4, 7, 2, 6, 3,
+ 20, 16, 21, 17, 19, 18, 22, 23, 29, 24, 28, 26, 25, 30, 31, 27
+};
+/* DDR4 specific swizzling data end*/
+
+/* LPDD4 specific swizzling data start */
+
+/* Channel 0 PHY 0 to DUnit DQ mapping */
+static const uint8_t swizzling_ch0_lpddr4[] = {
+ 10, 8, 12, 11, 9, 13, 14, 15, 1, 3, 2, 0, 5, 4, 6, 7,
+ 30, 26, 24, 25, 28, 29, 31, 27, 20, 21, 22, 16, 23, 17, 18, 19,
+};
+
+/* Channel 1 PHY 0 to DUnit DQ mapping */
+static const uint8_t swizzling_ch1_lpddr4[] = {
+ 0, 6, 7, 5, 3, 2, 1, 4, 12, 15, 13, 8, 9, 10, 11, 14,
+ 17, 18, 19, 16, 23, 20, 21, 22, 30, 31, 25, 27, 26, 29, 28, 24,
+};
+
+/* Channel 1 PHY 1 to DUnit DQ mapping */
+static const uint8_t swizzling_ch2_lpddr4[] = {
+ 15, 8, 11, 10, 14, 12, 13, 9, 5, 1, 0, 6, 2, 3, 7, 4,
+ 31, 25, 24, 27, 30, 29, 28, 26, 21, 18, 20, 23, 16, 17, 22, 19,
+};
+
+/* Channel 0 PHY 1 to DUnit DQ mapping */
+static const uint8_t swizzling_ch3_lpddr4[] = {
+ 15, 9, 8, 10, 13, 14, 12, 11, 7, 6, 5, 0, 4, 2, 1, 3,
+ 20, 21, 23, 22, 19, 17, 18, 16, 24, 27, 26, 30, 25, 31, 28, 29
+};
+/* LPDD4 specific swizzling data end */
+
+static void fill_lpddr4_params(FSP_M_CONFIG *cfg)
+{
+ cfg->Package = 1;
+ cfg->MemoryDown = 1;
+ cfg->DDR3LPageSize = 0;
+ cfg->DDR3LASR = 0;
+ cfg->ScramblerSupport = 1;
+ cfg->ChannelHashMask = 0x36;
+ cfg->SliceHashMask = 0x9;
+ cfg->InterleavedMode = 2;
+ cfg->ChannelsSlicesEnable = 0;
+ cfg->MinRefRate2xEnable = 0;
+ cfg->DualRankSupportEnable = 0;
+ cfg->DisableFastBoot = 0;
+ cfg->RmtMode = 0;
+ cfg->RmtCheckRun = 0;
+ cfg->RmtMarginCheckScaleHighThreshold = 0;
+ cfg->MemorySizeLimit = 0;
+ cfg->LowMemoryMaxValue = 0;
+ cfg->HighMemoryMaxValue = 0;
+ cfg->Profile = 7;
+ cfg->DIMM0SPDAddress = 0x00;
+ cfg->DIMM1SPDAddress = 0x00;
+ cfg->Ch0_RankEnable = 0x1;
+ cfg->Ch0_DeviceWidth = 0x1;
+ cfg->Ch0_DramDensity = 0x2;
+ cfg->Ch0_Option = 0x3;
+ cfg->Ch0_TristateClk1 = 0;
+ cfg->Ch0_Mode2N = 0;
+ cfg->Ch0_OdtLevels = 0;
+ cfg->Ch1_RankEnable = 0x1;
+ cfg->Ch1_DeviceWidth = 0x1;
+ cfg->Ch1_DramDensity = 0x2;
+ cfg->Ch1_Option = 0x3;
+ cfg->Ch1_TristateClk1 = 0;
+ cfg->Ch1_Mode2N = 0;
+ cfg->Ch1_OdtLevels = 0;
+ cfg->Ch2_RankEnable = 0x1;
+ cfg->Ch2_DeviceWidth = 0x1;
+ cfg->Ch2_DramDensity = 0x2;
+ cfg->Ch2_Option = 0x3;
+ cfg->Ch2_TristateClk1 = 0;
+ cfg->Ch2_Mode2N = 0;
+ cfg->Ch2_OdtLevels = 0;
+ cfg->Ch3_RankEnable = 0x1;
+ cfg->Ch3_DeviceWidth = 0x1;
+ cfg->Ch3_DramDensity = 0x2;
+ cfg->Ch3_Option = 0x3;
+ cfg->Ch3_TristateClk1 = 0;
+ cfg->Ch3_Mode2N = 0;
+ cfg->Ch3_OdtLevels = 0;
+ /* phy0 ch0 */
+ memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0_lpddr4,
+ sizeof(swizzling_ch0_lpddr4));
+ /* phy0 ch1 */
+ memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1_lpddr4,
+ sizeof(swizzling_ch1_lpddr4));
+ /* phy1 ch1 */
+ memcpy(cfg->Ch2_Bit_swizzling, swizzling_ch2_lpddr4,
+ sizeof(swizzling_ch2_lpddr4));
+ /* phy1 ch0 */
+ memcpy(cfg->Ch3_Bit_swizzling, swizzling_ch3_lpddr4,
+ sizeof(swizzling_ch3_lpddr4));
+}
+
+static void fill_ddr4_params(FSP_M_CONFIG *cfg)
+{
+ cfg->Package = 0; /* 0x1:BGA */
+ cfg->MemoryDown = 0;
+ cfg->DDR3LPageSize = 1;
+ cfg->DDR3LASR = 0;
+ cfg->ScramblerSupport = 0;
+ cfg->ChannelHashMask = 0x36;
+ cfg->SliceHashMask = 0x9;
+ cfg->InterleavedMode = 0;
+ cfg->ChannelsSlicesEnable = 0;
+ cfg->MinRefRate2xEnable = 0;
+ cfg->DualRankSupportEnable = 1;
+ cfg->DisableFastBoot = 0;
+ cfg->RmtMode = 0;
+ cfg->RmtCheckRun = 0;
+ cfg->RmtMarginCheckScaleHighThreshold = 0;
+ cfg->MemorySizeLimit = 0;
+ cfg->LowMemoryMaxValue = 0;
+ cfg->HighMemoryMaxValue = 0;
+ cfg->Profile = 11;
+ cfg->DIMM0SPDAddress = 0xA0;
+ cfg->DIMM1SPDAddress = 0xA4;
+ cfg->Ch0_RankEnable = 0x3;
+ cfg->Ch0_DeviceWidth = 0x1;
+ cfg->Ch0_DramDensity = 0x0;
+ cfg->Ch0_Option = 0x3; /* Bank Address Hashing enabled */
+ cfg->Ch0_TristateClk1 = 0;
+ cfg->Ch0_Mode2N = 0;
+ cfg->Ch0_OdtLevels = 0;
+ cfg->Ch1_RankEnable = 0x3;
+ cfg->Ch1_DeviceWidth = 0x1;
+ cfg->Ch1_DramDensity = 0x2;
+ cfg->Ch1_Option = 0x3; /* Bank Address Hashing enabled */
+ cfg->Ch1_TristateClk1 = 0;
+ cfg->Ch1_Mode2N = 0;
+ cfg->Ch1_OdtLevels = 0;
+ cfg->Ch2_RankEnable = 0x0;
+ cfg->Ch2_DeviceWidth = 0x1;
+ cfg->Ch2_DramDensity = 0x2;
+ cfg->Ch2_Option = 0x3; /* Bank Address Hashing enabled */
+ cfg->Ch2_TristateClk1 = 0;
+ cfg->Ch2_Mode2N = 0;
+ cfg->Ch2_OdtLevels = 0;
+ cfg->Ch3_RankEnable = 0x0;
+ cfg->Ch3_DeviceWidth = 0x1;
+ cfg->Ch3_DramDensity = 0x2;
+ cfg->Ch3_Option = 0x3; /* Bank Address Hashing enabled */
+ cfg->Ch3_TristateClk1 = 0;
+ cfg->Ch3_Mode2N = 0;
+ cfg->Ch3_OdtLevels = 0;
+
+ /* phy0 ch0 */
+ memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0_ddr4,
+ sizeof(swizzling_ch0_ddr4));
+ /* phy0 ch1 */
+ memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1_ddr4,
+ sizeof(swizzling_ch1_ddr4));
+ /* phy1 ch1 */
+ memcpy(cfg->Ch2_Bit_swizzling, swizzling_ch2_ddr4,
+ sizeof(swizzling_ch2_ddr4));
+ /* phy1 ch0 */
+ memcpy(cfg->Ch3_Bit_swizzling, swizzling_ch3_ddr4,
+ sizeof(swizzling_ch3_ddr4));
+}
+
+static void fill_memory_params(FSP_M_CONFIG *cfg)
+{
+ uint8_t boardid;
+
+ if (CONFIG(IS_GLK_RVP_1))
+ boardid = BOARD_ID_GLK_RVP1_DDR4;
+ else
+ boardid = BOARD_ID_GLK_RVP2_LP4;
+
+ switch (boardid) {
+ case BOARD_ID_GLK_RVP1_DDR4:
+ fill_ddr4_params(cfg);
+ break;
+ case BOARD_ID_GLK_RVP2_LP4SD:
+ case BOARD_ID_GLK_RVP2_LP4:
+ fill_lpddr4_params(cfg);
+ break;
+ }
+}
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+ FSP_M_CONFIG *cfg = &memupd->FspmConfig;
+ fill_memory_params(cfg);
+}
+
+void mainboard_save_dimm_info(void)
+{
+ save_lpddr4_dimm_info(variant_lpddr4_config(), variant_memory_sku());
+}
diff --git a/src/mainboard/microtech/etabpro/touchpad.asl b/src/mainboard/microtech/etabpro/touchpad.asl
new file mode 100644
index 0000000..6168fbb
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/touchpad.asl
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+ Scope (\_SB.PCI0.I2C4)
+ {
+ Device (TPAD)
+ {
+ Name(_ADR, One)
+ Name (_HID, "ALPS0001")
+ Name (_CID, "PNP0C50")
+ Name (_DDN, "ALPS Touchpad")
+ Name (_UID, 1)
+ Name (ISTP, 1) /* Touchpad */
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x2C, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.PCI0.I2C4", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Level, ActiveLow)
+ {
+ GPIO_18_IRQ
+ }
+ GpioInt (Level, ActiveLow, ExclusiveAndWake, PullUp, 0x0000, "\\_SB.GPO1", 0x00, ResourceConsumer, ,)
+ {
+ 18
+ }
+ })
+
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+ Method(_DSM, 0x4, NotSerialized)
+ {
+ // DSM UUID for HIDI2C - HID driver does not load without DSM
+ If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE")))
+ {
+ // Function 0 : Query Function
+ If(LEqual(Arg2, Zero))
+ {
+ // Revision 1
+ If(LEqual(Arg1, One))
+ {
+ Return (Buffer (One) {0x03})
+ }
+ Else
+ {
+ Return (Buffer (One) {0x00})
+ }
+ } ElseIf (LEqual(Arg2, One)) { // Function 1 : HID Function
+ // HID Descriptor Address (IHV Specific)
+ Return(0x0020)
+ } Else {
+ Return (Buffer (One) {0x00})
+ }
+ } Else {
+ Return (Buffer (One) {0x00})
+ }
+ }
+ }
+}
diff --git a/src/mainboard/microtech/etabpro/touchpanel.asl b/src/mainboard/microtech/etabpro/touchpanel.asl
new file mode 100644
index 0000000..225b891
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/touchpanel.asl
@@ -0,0 +1,71 @@
+
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_SB.PCI0.I2C7) {
+// Touch Panels on I2C7
+// GPIO_212:TCH_PNL_INTR_LS_N North Community, IRQ number 0x75.
+//------------------------
+ Device (TPL1) {
+ Name (HID2, 1)
+ Name (_HID, "WCOM508E") // _HID: Hardware ID
+ Name (_CID, "PNP0C50") // _CID: Compatible ID
+ Name (_S0W, 0x04) // _S0W: S0 Device Wake State
+ Name (SBFB, ResourceTemplate () {
+ I2cSerialBus (
+ 0x000A,
+ ControllerInitiated,
+ 1000000,
+ AddressingMode7Bit,
+ "\\_SB.PCI0.I2C7",
+ 0x00,
+ ResourceConsumer,
+ ,
+ )
+ })
+ //
+ // GLK: Touchpanel Interrupt: GPIO_212: Northwest
+ // Pin 77
+ // Direct IRQ 0x75
+ //
+ Name (SBFG, ResourceTemplate () {
+ GpioInt (Level, ActiveLow, Exclusive, PullUp, 0x0000,
+ "\\_SB.GPO0", 0x00, ResourceConsumer, ,
+ )
+ {
+ 77
+ }
+ })
+ Name (SBFI, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
+ {
+ 0x75,
+ }
+ })
+
+ Method (_INI, 0, NotSerialized) // _INI: Initialize
+ {
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+
+ Method (_CRS, 0, NotSerialized) {
+ Return (ConcatenateResTemplate(SBFB, SBFG))
+ }
+ } // Device (TPL0)
+}
diff --git a/src/mainboard/microtech/etabpro/variants.h b/src/mainboard/microtech/etabpro/variants.h
new file mode 100644
index 0000000..cf91a04
--- /dev/null
+++ b/src/mainboard/microtech/etabpro/variants.h
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BASEBOARD_VARIANTS_H
+#define BASEBOARD_VARIANTS_H
+
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/**
+ * variant_board_id() - Get the board id for the current board variant
+ *
+ * Return: board id on success, -1 on failure/error.
+ */
+int variant_board_id(void);
+
+/* The next set of functions return the gpio table and fill in the number of
+ * entries for each table. */
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct pad_config *variant_sleep_gpio_table(size_t *num);
+
+/* Baseboard default swizzle. Can be reused if swizzle is same. */
+extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle;
+/* Return LPDDR4 configuration structure. */
+const struct lpddr4_cfg *variant_lpddr4_config(void);
+/* Return memory SKU for the board. */
+size_t variant_memory_sku(void);
+
+/* Return ChromeOS gpio table and fill in number of entries. */
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+
+/* Seed the NHLT tables with the board specific information. */
+struct nhlt;
+void variant_nhlt_init(struct nhlt *nhlt);
+
+#endif /* BASEBOARD_VARIANTS_H */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib9d755902f28b51823e16c228ee5d4fc13849798
Gerrit-Change-Number: 39277
Gerrit-PatchSet: 1
Gerrit-Owner: Miroslaw Kocur <mirek190(a)gmail.com>
Gerrit-MessageType: newchange
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