March 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: mb/supermicro/x10slm-f: Add new superio support to board's Kconfig
by Christoph Pomaska (Code Review) Aug. 7, 2023

Aug. 7, 2023

Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34905 ) Change subject: mb/supermicro/x10slm-f: Add new superio support to board's Kconfig ...................................................................... mb/supermicro/x10slm-f: Add new superio support to board's Kconfig Since the superio support code didnt exist when the board was ported, the Kconfig was not modified yet to add support for the BMC-chip. This commit fixes the missing Kconfig entry. Change-Id: I4f89c2ddcc00327e01d0a83fc13cfa862e6abd70 Signed-off-by: Christoph Pomaska <c.pomaska(a)hosting.de> --- M src/mainboard/supermicro/x10slm-f/Kconfig 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/34905/1 diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig index 3945c09..6effff2 100644 --- a/src/mainboard/supermicro/x10slm-f/Kconfig +++ b/src/mainboard/supermicro/x10slm-f/Kconfig @@ -20,15 +20,16 @@ def_bool y select BOARD_ROMSIZE_KB_16384 select CPU_INTEL_HASWELL - select DRIVERS_ASPEED_AST2050 # Supports AST2400 too. + select SOUTHBRIDGE_INTEL_LYNXPOINT select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select NORTHBRIDGE_INTEL_HASWELL select SERIRQ_CONTINUOUS_MODE - select SOUTHBRIDGE_INTEL_LYNXPOINT - select SUPERIO_NUVOTON_NCT6776 + select DRIVERS_ASPEED_AST2050 # Supports AST2400 too. + select SUPERIO_ASPEED_AST2400 # The board's BMC + select SUPERIO_NUVOTON_NCT6776 # the board's superio select SUPERIO_NUVOTON_NCT6776_COM_A config CBFS_SIZE -- To view, visit https://review.coreboot.org/c/coreboot/+/34905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f89c2ddcc00327e01d0a83fc13cfa862e6abd70 Gerrit-Change-Number: 34905 Gerrit-PatchSet: 1 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-MessageType: newchange

9 45

Change in coreboot[master]: soc/intel/common: Add romstage common stage file
by Bernardo Perez Priego (Code Review) Aug. 7, 2023

Aug. 7, 2023

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37628 ) Change subject: soc/intel/common: Add romstage common stage file ...................................................................... soc/intel/common: Add romstage common stage file This patch will ensures all intel soc is using common stage files to make coreboot design flow align across all socs. CPU, SA, PCH, MCH programming sequence might be different between socs but the function call should route from same location across all soc. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c --- M src/cpu/intel/car/romstage.c A src/soc/intel/common/basecode/include/intelbasecode/romstage.h A src/soc/intel/common/basecode/romstage/Makefile.inc A src/soc/intel/common/basecode/romstage/romstage.c 4 files changed, 162 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/37628/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 1f8eb9a..55d3c9d 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -52,9 +52,6 @@ for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; - if (CONFIG(VBOOT_EARLY_EC_SYNC)) - vboot_sync_ec(); - mainboard_romstage_entry(); /* Check the stack. */ @@ -64,9 +61,6 @@ printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); } - if (CONFIG(SMM_TSEG)) - smm_list_regions(); - prepare_and_run_postcar(&early_mtrrs); /* We do not return here. */ } diff --git a/src/soc/intel/common/basecode/include/intelbasecode/romstage.h b/src/soc/intel/common/basecode/include/intelbasecode/romstage.h new file mode 100644 index 0000000..0cebbbf --- /dev/null +++ b/src/soc/intel/common/basecode/include/intelbasecode/romstage.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BASECODE_ROMSTAGE_H +#define SOC_INTEL_COMMON_BASECODE_ROMSTAGE_H + +#include <stddef.h> +#include <stdint.h> +#include <fsp/soc_binding.h> + +struct romstage_ops { + void (*soc_early_init)(void); + void (*soc_init)(void); + void (*pch_early_init)(void); + void (*pch_init)(void); + void (*cpu_early_init)(void); + void (*cpu_init)(void); + bool (*is_s3wake)(void); + void (*soc_mem_init_params)(FSP_M_CONFIG *mupd); +}; + +/* SoC Override function */ +struct romstage_ops *soc_get_ops(void); + +#endif diff --git a/src/soc/intel/common/basecode/romstage/Makefile.inc b/src/soc/intel/common/basecode/romstage/Makefile.inc new file mode 100644 index 0000000..29763fb --- /dev/null +++ b/src/soc/intel/common/basecode/romstage/Makefile.inc @@ -0,0 +1 @@ +romstage-y += romstage.c diff --git a/src/soc/intel/common/basecode/romstage/romstage.c b/src/soc/intel/common/basecode/romstage/romstage.c new file mode 100644 index 0000000..55c4ab5 --- /dev/null +++ b/src/soc/intel/common/basecode/romstage/romstage.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <romstage_common.h> +#include <cpu/x86/pae.h> +#include <intelbasecode/romstage.h> +#include <intelblocks/systemagent.h> +#include <soc/iomap.h> +#include <soc/romstage.h> + +static const struct romstage_ops s_romstage_ops; + +__weak struct romstage_ops *soc_get_ops(void) +{ + return (struct romstage_ops *)&s_romstage_ops; +} + +void romstage_early_init(void) +{ + struct romstage_ops *rs_ops = soc_get_ops(); + + rs_ops->soc_early_init(); + rs_ops->pch_early_init(); + rs_ops->cpu_early_init(); +} + +void romstage_init(void) +{ + struct romstage_ops *rs_ops = soc_get_ops(); + + rs_ops->soc_init(); + rs_ops->pch_init(); + rs_ops->cpu_init(); +} + +void romstage_cmn_soc_early_init(void) +{ + systemagent_early_init(); + heci_init(HECI1_BASE_ADDRESS); +} + +void romstage_cmn_soc_init(void) +{ +} + +void romstage_cmn_pch_early_init(void) +{ +} + +void romstage_cmn_cpu_early_init(void) +{ +} + +void romstage_cmn_pch_init(void) +{ +} + +void romstage_cmn_cpu_init(void) +{ +} + +bool romstage_cmn_is_s3wake(void) +{ + struct chipset_power_state *ps = pmc_get_power_state(); + return pmc_fill_power_state(ps) == ACPI_S3; +} + +void romstage_cmn_soc_mem_init_param(FSP_M_CONFIG *m_cfg) +{ +} + +static const struct romstage_ops s_romstage_ops = { + &romstage_cmn_soc_early_init, + &romstage_cmn_soc_init, + &romstage_cmn_pch_early_init, + &romstage_cmn_pch_init, + &romstage_cmn_cpu_early_init, + &romstage_cmn_cpu_init, + &romstage_cmn_is_s3wake, + &romstage_cmn_mb_mem_init_param, + &romstage_cmn_soc_mem_init_param +}; + +/* + Main romstage function +*/ +asmlinkage void mainboard_romstage_entry(void) +{ + if (CONFIG(VBOOT_EARLY_EC_SYNC)) + vboot_sync_ec(rs_ops->fill_power_state()); + + romstage_early_init(); + romstage_init(); + fsp_memory_init(rs_ops->is_s3wake()); + + if (CONFIG(SMM_TSEG)) + smm_list_regions(); +} + +/* + Callback function for FSP memory initialization +*/ +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + struct romstage_ops *rs_ops = soc_get_ops(); + + FSP_M_CONFIG *m_cfg; + rs_ops->soc_mem_init_params(m_cfg); + mainboard_memory_init_params(m_cfg); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/37628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c Gerrit-Change-Number: 37628 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: [TESTME]lenovo/x220: Attempt to fix broken DRAM init
by Patrick Rudolph (Code Review) Aug. 7, 2023

Aug. 7, 2023

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39043 ) Change subject: [TESTME]lenovo/x220: Attempt to fix broken DRAM init ...................................................................... [TESTME]lenovo/x220: Attempt to fix broken DRAM init Enable power on WWAN as it has SMBUS connected. Might resolv an issue where DRAM init fails as no EEPROM is found on the bus. Untested. Change-Id: Ia7a2ca370124ecf743b000998b56855d5ed8f573 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/ec/lenovo/h8/Makefile.inc M src/mainboard/lenovo/x220/early_init.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/39043/1 diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc index 51c11be..9c8687a 100644 --- a/src/ec/lenovo/h8/Makefile.inc +++ b/src/ec/lenovo/h8/Makefile.inc @@ -18,6 +18,8 @@ ramstage-y += panic.c endif +romstage += wwan.c + ramstage-y += h8.c ramstage-y += bluetooth.c ramstage-y += wwan.c diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index 3429c1b..ae16f0c 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -24,6 +24,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <cpu/x86/msr.h> +#include <ec/lenovo/h8/h8.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { @@ -74,6 +75,18 @@ *pei_data = pei_data_template; } +void mainboard_early_init(int s3_resume) +{ + /* + * The WWAN slot has SMBUS connected. Turn on power to make sure + * SMBUS is usable and DRAM init will succeed. + * ramstage will turn it off, in case it's not needed. + * TODO: Does GPIO42 (SMB_3B_EN) help here? + */ + if (h8_has_wwan()) + h8_wwan_enable(true); +} + void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd (&spd[0], 0x50, id_only); -- To view, visit https://review.coreboot.org/c/coreboot/+/39043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7a2ca370124ecf743b000998b56855d5ed8f573 Gerrit-Change-Number: 39043 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: sb/intel/lynxpoint: Setup gpio in bootblock
by Arthur Heymans (Code Review) Aug. 7, 2023

Aug. 7, 2023

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36712 ) Change subject: sb/intel/lynxpoint: Setup gpio in bootblock ...................................................................... sb/intel/lynxpoint: Setup gpio in bootblock GPIO setup is needed for verstage. verstage can also still happen after romstage so keep the GPIO init there too. Change-Id: I448ca12f5ddab362983429c508e518b7042ef760 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/h81m-hds/Makefile.inc M src/mainboard/google/beltino/Makefile.inc M src/mainboard/google/slippy/Makefile.inc M src/mainboard/intel/baskingridge/Makefile.inc M src/mainboard/supermicro/x10slm-f/Makefile.inc M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/lynxpoint/Makefile.inc M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/pch.h 10 files changed, 22 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/36712/1 diff --git a/src/mainboard/asrock/h81m-hds/Makefile.inc b/src/mainboard/asrock/h81m-hds/Makefile.inc index de18bc5..3fc7ac7 100644 --- a/src/mainboard/asrock/h81m-hds/Makefile.inc +++ b/src/mainboard/asrock/h81m-hds/Makefile.inc @@ -16,4 +16,5 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += gpio.c bootblock-y += bootblock.c diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index 7535350..0ecb31d 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -23,5 +23,7 @@ romstage-y += variants/$(VARIANT_DIR)/led.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index f80dcab..e35f93e 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -23,6 +23,8 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c + subdirs-y += variants/$(VARIANT_DIR) ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index 91a7963..8f12999 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -17,6 +17,7 @@ ramstage-y += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c +bootblock-y += gpio.c romstage-y += gpio.c smm-y += mainboard_smi.c diff --git a/src/mainboard/supermicro/x10slm-f/Makefile.inc b/src/mainboard/supermicro/x10slm-f/Makefile.inc index 301070b..0b4f367 100644 --- a/src/mainboard/supermicro/x10slm-f/Makefile.inc +++ b/src/mainboard/supermicro/x10slm-f/Makefile.inc @@ -15,4 +15,5 @@ ## romstage-y += gpio.c +bootblock-y += gpio.c bootblock-y += bootblock.c diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 5ca7daf..433a310 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -34,6 +34,7 @@ romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index e53ed8d..bacaf74 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -50,6 +50,7 @@ romstage-y += rcba.c pmutil.c ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) +bootblock-y += lp_gpio.c romstage-y += lp_gpio.c ramstage-y += lp_gpio.c smm-y += lp_gpio.c diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 39e6925..abcb35b 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -16,6 +16,7 @@ #include <device/pci_ops.h> #include <cpu/intel/car/bootblock.h> #include "pch.h" +#include "lp_gpio.h" /* * Enable Prefetching and Caching. @@ -33,14 +34,6 @@ pci_write_config8(dev, 0xdc, reg8); } - -static void map_rcba(void) -{ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); -} - static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC. The chipset does this by default, @@ -72,7 +65,7 @@ void bootblock_early_southbridge_init(void) { - map_rcba(); + pch_enable_bars(); enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); @@ -83,3 +76,12 @@ pch_enable_lpc(); mainboard_config_superio(); } + +void bootblock_southbridge_init(void) +{ +#if CONFIG(INTEL_LYNXPOINT_LP) + setup_pch_lp_gpios(mainboard_gpio_map); +#else + setup_pch_gpios(mainboard_gpio_map); +#endif +} diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index b49d3cf..9cf021e 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -45,7 +45,7 @@ return id == PCH_TYPE_LPT_LP; } -static void pch_enable_bars(void) +void pch_enable_bars(void) { /* Setting up Southbridge. In the northbridge code. */ pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 8802be1..561c5b7 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -184,6 +184,7 @@ int early_pch_init(const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); void mainboard_config_superio(void); +void pch_enable_bars(void); #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/36712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I448ca12f5ddab362983429c508e518b7042ef760 Gerrit-Change-Number: 36712 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mb/*/*{haswell}: Link gpio.c and add a const global for lp variant
by Arthur Heymans (Code Review) Aug. 7, 2023

Aug. 7, 2023

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36710 ) Change subject: mb/*/*{haswell}: Link gpio.c and add a const global for lp variant ...................................................................... mb/*/*{haswell}: Link gpio.c and add a const global for lp variant This is similar to how sb/common/intel handles it. The advantage is that the gpio configuration does not need to be passed on that much. Change-Id: I6d07f0d4d3aaf4e8662d6f7dc8238d14a16fd04d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/Makefile.inc M src/mainboard/google/beltino/romstage.c R src/mainboard/google/beltino/variants/mccloud/gpio.c R src/mainboard/google/beltino/variants/monroe/gpio.c R src/mainboard/google/beltino/variants/panther/gpio.c R src/mainboard/google/beltino/variants/tricky/gpio.c R src/mainboard/google/beltino/variants/zako/gpio.c M src/mainboard/google/slippy/Makefile.inc R src/mainboard/google/slippy/variants/falco/gpio.c M src/mainboard/google/slippy/variants/falco/romstage.c R src/mainboard/google/slippy/variants/leon/gpio.c M src/mainboard/google/slippy/variants/leon/romstage.c R src/mainboard/google/slippy/variants/peppy/gpio.c M src/mainboard/google/slippy/variants/peppy/romstage.c R src/mainboard/google/slippy/variants/wolf/gpio.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/intel/baskingridge/Makefile.inc R src/mainboard/intel/baskingridge/gpio.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/lp_gpio.h M src/southbridge/intel/lynxpoint/pch.h 26 files changed, 25 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/36710/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 4c67ba8..7459011 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -134,7 +134,6 @@ struct rcba_config_instruction; struct romstage_params { struct pei_data *pei_data; - const void *gpio_map; const struct rcba_config_instruction *rcba_config; void (*copy_spd)(struct pei_data *); }; diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 34fd7b0..e28ebf4 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -33,7 +33,7 @@ enable_lapic(); - wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); + wake_from_s3 = early_pch_init(params->rcba_config); /* Perform some early chipset initialization required * before RAM initialization can work diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 3deae75..dd4043e 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -92,7 +92,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], }; diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index e1bebc1..7535350 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -21,6 +21,7 @@ smm-y += smihandler.c variants/$(VARIANT_DIR)/led.c romstage-y += variants/$(VARIANT_DIR)/led.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index f206664..5c91bec 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -24,7 +24,6 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> -#include <variant/gpio.h> #include "onboard.h" const struct rcba_config_instruction rcba_config[] = { @@ -128,7 +127,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], }; diff --git a/src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h b/src/mainboard/google/beltino/variants/mccloud/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/mccloud/gpio.c index 116eeeb..47979d2b 100644 --- a/src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/mccloud/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef MCCLOUD_GPIO_H -#define MCCLOUD_GPIO_H - +#include <stdint.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h b/src/mainboard/google/beltino/variants/monroe/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/monroe/gpio.c index 8423e1e..22ef848 100644 --- a/src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/monroe/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef MONROE_GPIO_H -#define MONROE_GPIO_H - +#include <stdint.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/beltino/variants/panther/include/variant/gpio.h b/src/mainboard/google/beltino/variants/panther/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/panther/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/panther/gpio.c index e48f0b4..08142a8 100644 --- a/src/mainboard/google/beltino/variants/panther/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/panther/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef PANTHER_GPIO_H -#define PANTHER_GPIO_H - +#include <stdint.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h b/src/mainboard/google/beltino/variants/tricky/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/tricky/gpio.c index 6980ebb..df5d333 100644 --- a/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/tricky/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef TRICKY_GPIO_H -#define TRICKY_GPIO_H - +#include <stdint.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/beltino/variants/zako/include/variant/gpio.h b/src/mainboard/google/beltino/variants/zako/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/zako/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/zako/gpio.c index dffefd6..e533bf0 100644 --- a/src/mainboard/google/beltino/variants/zako/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/zako/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef ZAKO_GPIO_H -#define ZAKO_GPIO_H - +#include <stdint.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 921f9e7..f80dcab 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -21,6 +21,7 @@ smm-y += smihandler.c romstage-y += variants/$(VARIANT_DIR)/romstage.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h b/src/mainboard/google/slippy/variants/falco/gpio.c similarity index 97% rename from src/mainboard/google/slippy/variants/falco/include/variant/gpio.h rename to src/mainboard/google/slippy/variants/falco/gpio.c index c35b81e..3fdc032 100644 --- a/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/falco/gpio.c @@ -13,10 +13,8 @@ * GNU General Public License for more details. */ -#ifndef FALCO_GPIO_H -#define FALCO_GPIO_H - -struct pch_lp_gpio_map; +#include <stdint.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 1903588..656bf70 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -24,7 +24,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <variant/gpio.h> #include "../../variant.h" const struct rcba_config_instruction rcba_config[] = { @@ -165,7 +164,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .copy_spd = copy_spd, }; diff --git a/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h b/src/mainboard/google/slippy/variants/leon/gpio.c similarity index 97% rename from src/mainboard/google/slippy/variants/leon/include/variant/gpio.h rename to src/mainboard/google/slippy/variants/leon/gpio.c index 7527ff2..5ea78f9 100644 --- a/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/leon/gpio.c @@ -13,10 +13,8 @@ * GNU General Public License for more details. */ -#ifndef LEON_GPIO_H -#define LEON_GPIO_H - -struct pch_lp_gpio_map; +#include <stdint.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 3ef8eec..2eeb86d 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -24,7 +24,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <variant/gpio.h> #include "../../variant.h" const struct rcba_config_instruction rcba_config[] = { @@ -160,7 +159,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .copy_spd = copy_spd, }; diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h b/src/mainboard/google/slippy/variants/peppy/gpio.c similarity index 97% rename from src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h rename to src/mainboard/google/slippy/variants/peppy/gpio.c index 8eb3da9..00e6a54 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/peppy/gpio.c @@ -13,10 +13,8 @@ * GNU General Public License for more details. */ -#ifndef PEPPY_GPIO_H -#define PEPPY_GPIO_H - -struct pch_lp_gpio_map; +#include <stdint.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 71eafc2..048a154 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -25,7 +25,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <variant/gpio.h> #include "../../onboard.h" #include "../../variant.h" @@ -177,7 +176,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .copy_spd = copy_spd, }; diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h b/src/mainboard/google/slippy/variants/wolf/gpio.c similarity index 97% rename from src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h rename to src/mainboard/google/slippy/variants/wolf/gpio.c index 5c72f73..1dbd5ff 100644 --- a/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/wolf/gpio.c @@ -13,10 +13,8 @@ * GNU General Public License for more details. */ -#ifndef WOLF_GPIO_H -#define WOLF_GPIO_H - -struct pch_lp_gpio_map; +#include <stdint.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 7fcf085..cc67c93 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -25,7 +25,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <variant/gpio.h> #include "../../variant.h" const struct rcba_config_instruction rcba_config[] = { @@ -164,7 +163,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .copy_spd = copy_spd, }; diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index e34704d..91a7963 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -17,4 +17,6 @@ ramstage-y += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c +romstage-y += gpio.c + smm-y += mainboard_smi.c diff --git a/src/mainboard/intel/baskingridge/gpio.h b/src/mainboard/intel/baskingridge/gpio.c similarity index 98% rename from src/mainboard/intel/baskingridge/gpio.h rename to src/mainboard/intel/baskingridge/gpio.c index f2be9e3..3a33f09 100644 --- a/src/mainboard/intel/baskingridge/gpio.h +++ b/src/mainboard/intel/baskingridge/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef BASKING_RIDGE_GPIO_H -#define BASKING_RIDGE_GPIO_H - +#include <stdint.h> #include <southbridge/intel/common/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 1a10931..3d03ab3 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -134,7 +134,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .copy_spd = NULL, }; diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 552ebd2..46ec7b2 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -90,7 +90,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = rcba_config, }; diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 25ffdc4..b49d3cf 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -99,17 +99,16 @@ { } -int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config) +int early_pch_init(const struct rcba_config_instruction *rcba_config) { int wake_from_s3; pch_enable_bars(); #if CONFIG(INTEL_LYNXPOINT_LP) - setup_pch_lp_gpios(gpio_map); + setup_pch_lp_gpios(mainboard_gpio_map); #else - setup_pch_gpios(gpio_map); + setup_pch_gpios(mainboard_gpio_map); #endif pch_generic_setup(); diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index 8436243..0464226 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -160,6 +160,8 @@ u8 pirq; } __packed; +extern const struct pch_lp_gpio_map mainboard_gpio_map[]; + /* Configure GPIOs with mainboard provided settings */ void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index d83dd17..8802be1 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -181,8 +181,7 @@ #endif void enable_usb_bar(void); -int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config); +int early_pch_init(const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); void mainboard_config_superio(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/36710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d07f0d4d3aaf4e8662d6f7dc8238d14a16fd04d Gerrit-Change-Number: 36710 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: Documentation: Add cache as ram documentation
by Arthur Heymans (Code Review) Aug. 7, 2023

Aug. 7, 2023

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36126 ) Change subject: Documentation: Add cache as ram documentation ...................................................................... Documentation: Add cache as ram documentation This add documentation around coreboot's history of CAR usage. The history is reconstructed from articles and git/svn history, but should provide a good overview of the challenges and solutions coreboot came up with to deal with early code execution on X86 platforms. The technical details about CAr will come in follow-up patch and are marked as TODO for now. Change-Id: I964d59a6bd210f3d4d06220d2ec7166110ab2cf3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A Documentation/cpu/index.md A Documentation/cpu/x86/car.md M Documentation/index.md 3 files changed, 171 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/36126/1 diff --git a/Documentation/cpu/index.md b/Documentation/cpu/index.md new file mode 100644 index 0000000..d9f063f --- /dev/null +++ b/Documentation/cpu/index.md @@ -0,0 +1,5 @@ +# CPU-specific documentation + +This section contains documentation about coreboot on specific CPU. + +* [A gentle introduction to Cache-as-Ram on X86](x86/car.md) diff --git a/Documentation/cpu/x86/car.md b/Documentation/cpu/x86/car.md new file mode 100644 index 0000000..3d2983e --- /dev/null +++ b/Documentation/cpu/x86/car.md @@ -0,0 +1,165 @@ +# A gentle introduction to Cache-as-Ram on X86 + +This explains a bit of history on CAR in coreboot, how it works +and then finally give a more in depth overview at the steps of +how it is set up on Intel CPUs. + +## Glossary + +- Cache-as-RAM/CAR: Using not memory mapped CPU cache as execution + environment. +- XIP: Execute in place on a memory mapped medium +- SRAM: Static Random Access Memory, here: memory mapped memory + that needs no initialization. +- ROMCC: A C compiler using only the CPU registers. + +## Cache-as-Ram, the basics + +When an X86 platforms boot, it starts in a pretty bare environment. +The first instruction is fetched from the top of the boot medium, +which on most x86 platforms is memory mapped below 4G (in 32bit +protected mode). Not only do they start in 16bit 'real' mode, +most of the hardware starts uninitialized. This includes the dram +controller. Another thing about X86 platforms is that they generally +don't feature SRAM, static RAM. SRAM for this purpose of this text is +a small region of ram that is available without any initialization. +Without RAM this leaves the system with just CPU registers and a +memory mapped boot medium of which code can be executed in place (XIP) +to initialize the hardware. + +For simple dram controllers that environment is just fine and +initializing the dram controller in assembly code without using a +stack is very doable. Modern systems however require complex +initialization procedures and writing that in assembly would be either +too hard or simply impossible. To overcome this limitation a technique +called Cache-as-Ram exists. It allows to use the CPU's Cache-as-Ram. +This in turn makes it possible to write the early initialization code +in a higher level programming language compiled by a regular compiler, +e.g. GCC. Typically only the stack is placed in Cache-as-Ram and the +code is still executed in place, but copying code in the cache as ram +and executing from there is also possible. + +For coreboot this means that with only a very small amount of assembly +code to set up CAR, all the other code can written in C, which +compared to writing assembly tremendously increases development speed +and is much less error prone. + +## A bit of history on Cache-as-Ram in coreboot + +### Linux as a BIOS? The invention of romstage + +When LinuxBIOS, later coreboot, started out, the first naive attempt +to run the Linux kernel instead of the legacy BIOS interface, was to +jump straight to loading the kernel. This did not work at all, since +dram was not working at that point. LinuxBIOS v1 therefore +initialized the memory in assembly before it was able to load the +kernel. This executed in place and would later become romstage. It +turned that Linux needed other devices, like enumerated and have it's +resources allocated, so yet another stage, ramstage, was called into +life, but that's another story. + +### coreboot v2: romcc + +In 2003 AMD's K8 CPU's came out. Those CPU's featured an on die memory +controller and also a new point to point BUS for CPU <-> CPU and +CPU <-> IO controller (northbridge) devices. Writing support for +these in assembly became difficult and a better solution was needed. +This is where ROMCC came to the rescue in 2002. ROMCC is a 25K lines +of code C compiler, written by Eric Biederman, that does not use a +stack but uses CPU registers instead. Besides the 8 general purpose +registers on x86 the MMX and SSE registers, respectively _%mm0_-_%mm7_ +and _%xmm0_-_%xmm7_, can be used to store data. ROMCC also converts +all function calls to static inline functions. This has the +disadvantage that a ROMCC compiled stage must be compiled in one go, +linking is not possible. In practice you will see a lot of '#include +_some_file.c_' which is quite unusual in C, because it makes the +inclusion of files fragile. Given that limited amount +'register-stack', it also imposes restrictions on how many levels of +nested function can be achieved. One last issue with ROMCC is that +no-one really dared touching that code, due to its size and complexity +besides its original author. + +Coreboot used ROMCC in the following way: a bootblock written in both +assembly to enter 32bit protected mode would use ROMCC compiled code +to either jump to 'normal/romstage' or 'fallback/romstage' which in +turn was also compiled with romstage. + +### Cache-as-Ram + +While ROMCC was eventually used for early initialization, prior to +that development attempts were made to use the CPU's cache as RAM. +This would allow to use regular GCC compiled and linked code to +be used. The idea is to set up the CPU's cache to Write Back to a +region, while disable cacheline filling or simply hope that no cache +eviction or invalidation happens. Eric Biederman initially got CAR +working, but with the advent of Intel Hyperthreading on the Pentium 4, +on which CAR setup proved to be a little more difficult and he +developed ROMCC instead. + +Around 2006 a lot was learned from coreboot v2 with its ROMCC usage +and development on coreboot v3 was started. The decision was mode to +not use ROMCC anymore and use Cache Memory for early stages. The +results were good as init object code size is reduced by factor of +four. So the code was smaller and faster at the same time. + +coreboot v4 sort of merged v2 and v3, so it was a mix of ROMCC compiled +romstage and romstage with CAR. + +In 2014 Support for ROMCC compiled romstage was dropped. + +### Intel Apollolake, a new era: POSTCAR_STAGE and C_ENVIRONMENT_BOOTBLOCK + +In 2016 Intel released the ApolloLake architecture. This architecture +is a weird duck in the X86 pool. It is the first Intel CPU to feature +MMC as a boot medium and does not memory map it. It also features to +the main CPU read only SRAM that is mapped right below 4G. The +bootblock is copied to SRAM and executed. Given that the boot medium +is not always memory mapped XIP is not an option. The solution is to +set up CAR in the bootblock and copy the romstage in CAR. We call this +C_ENVIRONMENT_BOOTBLOCK, because it runs GCC compiled code. Granted +XIP is still possible on ApolloLake, but coreboot has to use Intel's +blob, FSP-M, and it is linked to run in CAR, so a blob actually forced +a nice feature in coreboot! + +Another issue arises with this setup. With romstage running from the +read only boot medium, you can continue executing code (albeit without +stack) to tear down the CAR and start executing code from 'real' RAM. +On ApolloLake with romstage executing from CAR, tearing down CAR in +there, would shooting in ones own foot, as our code would be gone +in doing so. The solution was to tear down CAR in a separate stage, +named 'postcar' stage. This provides a clean separation of programs +and results in needing less linker scripts hacks in romstage. This +solution was therefore adopted by many other platforms that still did +XIP. + +### AMD Zen, 2019 + +On AMD Zen the first CPU to come out of reset is the PSP and it +initializes the dram before pulling out the main CPU out of reset. +CAR won't be needed, nor used on this platform. + +### The future? + +For coreboot release 4.11, scheduled for october 2019, support for +ROMCC in the bootblock will be dropped as will support for the messy +tearing down of CAR in romstage as opposed to doing that in a separate +stage. + +## In depth analysis + +### CAR setup + +TODO: MTRR, IPI/hyperthreaded, ROM Caching, Non-evict + +### Linker symbols + +TODO: sharing things over multiple CAR stages: car.ld + +### CAR teardown + +TODO: postcarstage, NO_CAR_GLOBAL_MIGRATION + +## References +[2007, The Open Source BIOS is Ten An interview with the coreboot developers](http://www.h-online.com/open/features/The-Open-Source-BIOS-is-T… +[A Framework for Using Processor Cache-as-Ram (CAR)](https://www.coreboot.org/images/6/6c/LBCar.pdf) +[CAR: Using Cache-as-Ram in LinuxBIOS](https://www.coreboot.org/data/yhlu/cache_as_ram_lb_09142006.pdf) diff --git a/Documentation/index.md b/Documentation/index.md index 1c04ad3..85666cb 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -177,6 +177,7 @@ * [Display panel-specific documentation](gfx/display-panel.md) * [Architecture-specific documentation](arch/index.md) * [Platform independend drivers documentation](drivers/index.md) +* [CPU-specific documentation](cpu/index.md) * [Northbridge-specific documentation](northbridge/index.md) * [System on Chip-specific documentation](soc/index.md) * [Mainboard-specific documentation](mainboard/index.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/36126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I964d59a6bd210f3d4d06220d2ec7166110ab2cf3 Gerrit-Change-Number: 36126 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: soc/intel/cannonlake: Add romstage common stage file
by Bernardo Perez Priego (Code Review) Aug. 7, 2023

Aug. 7, 2023

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37883 ) Change subject: soc/intel/cannonlake: Add romstage common stage file ...................................................................... soc/intel/cannonlake: Add romstage common stage file Change-Id: I480bd720708496e393cdc7e85876a2209fe639fc --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/cannonlake/romstage/romstage.c 3 files changed, 124 insertions(+), 115 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37883/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index c744e99..16bcad6 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -113,6 +113,7 @@ CPPFLAGS_common += -I$(src)/soc/intel/cannonlake CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include +CPPFLAGS_common += -I$(src)/soc/intel/common/basecode/include # DSP firmware settings files. NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/cnl/nhlt-blobs diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 5c74d4a..9adae3d 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -27,109 +27,6 @@ #include "../chip.h" -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) -{ - unsigned int i; - uint32_t mask = 0; - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_ISH); - - /* Set IGD stolen size to 64MB. */ - m_cfg->IgdDvmt50PreAlloc = 2; - m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->SaGv = config->SaGv; - if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) - m_cfg->UserBd = BOARD_TYPE_DESKTOP; - else - m_cfg->UserBd = BOARD_TYPE_ULT_ULX; - m_cfg->RMT = config->RMT; - - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1 << i); - } - m_cfg->PcieRpEnableMask = mask; - m_cfg->PrmrrSize = get_prmrr_size(); - m_cfg->EnableC6Dram = config->enable_c6dram; -#if CONFIG(SOC_INTEL_COMETLAKE) - m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; -#else - m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; -#endif - /* - * PcdDebugInterfaceFlags - * This config will allow coreboot to pass information to the FSP - * regarding which debug interface is being used. - * Debug Interfaces: - * BIT0-RAM, BIT1-Legacy Uart BIT3-USB3, BIT4-LPSS Uart, BIT5-TraceHub - * BIT2 - Not used. - */ - m_cfg->PcdDebugInterfaceFlags = - CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10; - - /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ - m_cfg->VmxEnable = CONFIG(ENABLE_VMX); - -#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS) - m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; -#endif - - if (config->cpu_ratio_override) { - m_cfg->CpuRatio = config->cpu_ratio_override; - } else { - /* Set CpuRatio to match existing MSR value */ - msr_t flex_ratio; - flex_ratio = rdmsr(MSR_FLEX_RATIO); - m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; - } - - /* If ISH is enabled, enable ISH elements */ - if (!dev) - m_cfg->PchIshEnable = 0; - else - m_cfg->PchIshEnable = dev->enabled; - - /* If HDA is enabled, enable HDA elements */ - dev = pcidev_path_on_root(PCH_DEVFN_HDA); - if (!dev) - m_cfg->PchHdaEnable = 0; - else - m_cfg->PchHdaEnable = dev->enabled; - - /* Enable IPU only if the device is enabled */ - m_cfg->SaIpuEnable = 0; - dev = pcidev_path_on_root(SA_DEVFN_IPU); - if (dev) - m_cfg->SaIpuEnable = dev->enabled; -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); - const struct device *smbus = pcidev_path_on_root(PCH_DEVFN_SMBUS); - assert(dev != NULL); - const config_t *config = config_of(dev); - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig; - - soc_memory_init_params(m_cfg, config); - - /* Enable SMBus controller based on config */ - if (!smbus) - m_cfg->SmbusEnable = 0; - else - m_cfg->SmbusEnable = smbus->enabled; - - /* Set debug probe type */ - m_cfg->PlatformDebugConsent = - CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT; - - /* Configure VT-d */ - tconfig->VtdDisable = 0; - - mainboard_memory_init_params(mupd); -} - __weak void mainboard_memory_init_params(FSPM_UPD *mupd) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index f782f63..668ca50 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -27,6 +27,11 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <string.h> +#include <intelbasecode/romstage.h> +#include <assert.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/msr.h> +#include <cpu/x86/msr.h> #include "../chip.h" @@ -41,6 +46,121 @@ /* Default weak implementation, no need to override part number. */ } +void cnlk_soc_post_mem_init(void); + +void cnlk_soc_mem_init_params(FSPM_UPD *mupd); + +static struct romstage_ops cnlk_rs_ops = { + &romstage_cmn_soc_init, + &romstage_cmn_pch_init, + &romstage_cmn_cpu_init, + &romstage_cmn_is_s3wake, + &romstage_cmn_soc_mem_init_param, + &mainboard_memory_init_params, + &cnlk_soc_post_mem_init, + &cnlk_soc_post_mem_init +}; + +struct romstage_ops *soc_get_ops(void) +{ + return &cnlk_rs_ops; +} + +void cnlk_soc_mem_init_params(FSPM_UPD *mupd) +{ + unsigned int i; + uint32_t mask = 0; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const config_t *config = config_of(dev); + + assert(dev != NULL); + config = config_of(dev); + dev = pcidev_path_on_root(PCH_DEVFN_ISH); + /* Set IGD stolen size to 64MB. */ + m_cfg->IgdDvmt50PreAlloc = 2; + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->SaGv = config->SaGv; + if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) + m_cfg->UserBd = BOARD_TYPE_DESKTOP; + else + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; + m_cfg->RMT = config->RMT; + + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1 << i); + } + m_cfg->PcieRpEnableMask = mask; + m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->EnableC6Dram = config->enable_c6dram; +#if CONFIG(SOC_INTEL_COMETLAKE) + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; +#else + m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; +#endif + /* + * PcdDebugInterfaceFlags + * This config will allow coreboot to pass information to the FSP + * regarding which debug interface is being used. + * Debug Interfaces: + * BIT0-RAM, BIT1-Legacy Uart BIT3-USB3, BIT4-LPSS Uart, BIT5-TraceHub + * BIT2 - Not used. + */ + m_cfg->PcdDebugInterfaceFlags = + CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10; + + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + +#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS) + m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; +#endif + + if (config->cpu_ratio_override) { + m_cfg->CpuRatio = config->cpu_ratio_override; + } else { + /* Set CpuRatio to match existing MSR value */ + msr_t flex_ratio; + flex_ratio = rdmsr(MSR_FLEX_RATIO); + m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; + } + + /* If ISH is enabled, enable ISH elements */ + if (!dev) + m_cfg->PchIshEnable = 0; + else + m_cfg->PchIshEnable = dev->enabled; + + /* If HDA is enabled, enable HDA elements */ + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + if (!dev) + m_cfg->PchHdaEnable = 0; + else + m_cfg->PchHdaEnable = dev->enabled; + + /* Enable IPU only if the device is enabled */ + m_cfg->SaIpuEnable = 0; + dev = pcidev_path_on_root(SA_DEVFN_IPU); + if (dev) + m_cfg->SaIpuEnable = dev->enabled; + + /* Enable SMBus controller based on config */ + dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); + if (!dev) + m_cfg->SmbusEnable = 0; + else + m_cfg->SmbusEnable = dev->enabled; + + /* Set debug probe type */ + m_cfg->PlatformDebugConsent = + CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT; + + /* Configure VT-d */ + mupd->FspmTestConfig.VtdDisable = 0; +} + /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { @@ -125,19 +245,10 @@ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -void mainboard_romstage_entry(void) +void cnlk_soc_post_mem_init(void) { - bool s3wake; - struct chipset_power_state *ps = pmc_get_power_state(); - - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ - systemagent_early_init(); - /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); - - s3wake = pmc_fill_power_state(ps) == ACPI_S3; - fsp_memory_init(s3wake); pmc_set_disb(); - if (!s3wake) + if (!cnlk_rs_ops.is_s3wake()) save_dimm_info(); } + -- To view, visit https://review.coreboot.org/c/coreboot/+/37883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I480bd720708496e393cdc7e85876a2209fe639fc Gerrit-Change-Number: 37883 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: eltan/verified_boot: include vboot21 code directly
by Joel Kitching (Code Review) Aug. 7, 2023

Aug. 7, 2023

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37654 ) Change subject: eltan/verified_boot: include vboot21 code directly ...................................................................... eltan/verified_boot: include vboot21 code directly vboot 2.1 data structures and code, as well as the fwlib21 build target, are all being deprecated. Any use of these data structures and code should be forked and handled separately. The data structures and functions used by eltan verified boot were never part of the vboot API, and were never intended to be used by external parties. Instead of building fwlib21 target, build fwlib instead, which will be the only available library going forward. This can provide access to the vb2_sha.h API. Note that vboot 2.1 error codes will also be deprecated in the future. At this point, vb2_error_t may also be forked and included in eltan_vb21.h. BUG=b:124141368, chromium:968464 TEST=util/abuild/abuild -v -B -e -p none -t FACEBOOK_FBG1701 BRANCH=none Change-Id: Iae58a0c42161ddfec9908f9867286e3dc1f055a2 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/vendorcode/eltan/security/include/cb_sha.h M src/vendorcode/eltan/security/lib/Makefile.inc M src/vendorcode/eltan/security/verified_boot/Makefile.inc A src/vendorcode/eltan/security/verified_boot/eltan_vb21.c A src/vendorcode/eltan/security/verified_boot/eltan_vb21.h M src/vendorcode/eltan/security/verified_boot/vboot_check.c 6 files changed, 1,114 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/37654/1 diff --git a/src/vendorcode/eltan/security/include/cb_sha.h b/src/vendorcode/eltan/security/include/cb_sha.h index 9a231d8..eea9f40 100644 --- a/src/vendorcode/eltan/security/include/cb_sha.h +++ b/src/vendorcode/eltan/security/include/cb_sha.h @@ -16,9 +16,7 @@ #ifndef __SECURITY_CB_SHA_H__ #define __SECURITY_CB_SHA_H__ -#include <2rsa.h> -#include <vb21_common.h> -#include <vb2_api.h> +#include <vb2_sha.h> vb2_error_t cb_sha_little_endian(enum vb2_hash_algorithm hash_alg, const uint8_t *data, uint32_t len, uint8_t *digest); diff --git a/src/vendorcode/eltan/security/lib/Makefile.inc b/src/vendorcode/eltan/security/lib/Makefile.inc index 2e11fb5..d79d70b 100644 --- a/src/vendorcode/eltan/security/lib/Makefile.inc +++ b/src/vendorcode/eltan/security/lib/Makefile.inc @@ -16,7 +16,9 @@ # call with $1 = stage name to create rules for building the library # for the stage and adding it to the stage's set of object files. define vendor-security-lib -VEN_SEC_LIB_$(1) = $(obj)/external/ven_sec_lib-$(1)/vboot_fw21.a +VEN_SEC_LIB_$(1) = \ + $(obj)/external/ven_sec_lib-$(1)/vboot_fw.a + VEN_SEC_CFLAGS_$(1) += $$(patsubst -I%,-I$(top)/%,\ $$(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ $$(filter-out -I$(obj), $$(CPPFLAGS_$(1))))) @@ -32,29 +34,25 @@ $(MAKE) -C $(VBOOT_SOURCE) \ BUILD=$$(abspath $$(dir $$(VEN_SEC_LIB_$(1)))) \ V=$(V) \ - fwlib21 + fwlib endef # vendor-security-for-stage -CFLAGS_common += -I3rdparty/vboot/firmware/2lib/include -CFLAGS_common += -I3rdparty/vboot/firmware/lib21/include - ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) bootblock-y += cb_sha.c -bootblock-y += ../../../../security/vboot/vboot_logic.c $(eval $(call vendor-security-lib,bootblock)) -bootblock-srcs += $(obj)/external/ven_sec_lib-bootblock/vboot_fw21.a +bootblock-srcs += $(obj)/external/ven_sec_lib-bootblock/vboot_fw.a postcar-y += cb_sha.c $(eval $(call vendor-security-lib,postcar)) -postcar-srcs += $(obj)/external/ven_sec_lib-postcar/vboot_fw21.a +postcar-srcs += $(obj)/external/ven_sec_lib-postcar/vboot_fw.a ramstage-y += cb_sha.c $(eval $(call vendor-security-lib,ramstage)) -ramstage-srcs += $(obj)/external/ven_sec_lib-ramstage/vboot_fw21.a +ramstage-srcs += $(obj)/external/ven_sec_lib-ramstage/vboot_fw.a romstage-y += cb_sha.c $(eval $(call vendor-security-lib,romstage)) -romstage-srcs += $(obj)/external/ven_sec_lib-romstage/vboot_fw21.a +romstage-srcs += $(obj)/external/ven_sec_lib-romstage/vboot_fw.a -endif \ No newline at end of file +endif diff --git a/src/vendorcode/eltan/security/verified_boot/Makefile.inc b/src/vendorcode/eltan/security/verified_boot/Makefile.inc index 97d8f81..1663fa5 100644 --- a/src/vendorcode/eltan/security/verified_boot/Makefile.inc +++ b/src/vendorcode/eltan/security/verified_boot/Makefile.inc @@ -15,7 +15,10 @@ ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) -CPPFLAGS_common += -I$(src)/security/vboot +bootblock-y += eltan_vb21.c +postcar-y += eltan_vb21.c +romstage-y += eltan_vb21.c +ramstage-y += eltan_vb21.c bootblock-y += vboot_check.c postcar-y += vboot_check.c diff --git a/src/vendorcode/eltan/security/verified_boot/eltan_vb21.c b/src/vendorcode/eltan/security/verified_boot/eltan_vb21.c new file mode 100644 index 0000000..277b55a --- /dev/null +++ b/src/vendorcode/eltan/security/verified_boot/eltan_vb21.c @@ -0,0 +1,840 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <vb2_sha.h> +#include <vendorcode/eltan/security/verified_boot/eltan_vb21.h> + +/** + * a[] -= mod + */ +static void subM(const struct evb2_public_key *key, uint32_t *a) +{ + int64_t A = 0; + uint32_t i; + for (i = 0; i < key->arrsize; ++i) { + A += (uint64_t)a[i] - key->n[i]; + a[i] = (uint32_t)A; + A >>= 32; + } +} + +/** + * Return a[] >= mod + */ +static int evb2_mont_ge(const struct evb2_public_key *key, uint32_t *a) +{ + uint32_t i; + for (i = key->arrsize; i;) { + --i; + if (a[i] < key->n[i]) + return 0; + if (a[i] > key->n[i]) + return 1; + } + return 1; /* equal */ +} + +/** + * Montgomery c[] += a * b[] / R % mod + */ +static void montMulAdd(const struct evb2_public_key *key, + uint32_t *c, + const uint32_t a, + const uint32_t *b) +{ + uint64_t A = (uint64_t)a * b[0] + c[0]; + uint32_t d0 = (uint32_t)A * key->n0inv; + uint64_t B = (uint64_t)d0 * key->n[0] + (uint32_t)A; + uint32_t i; + + for (i = 1; i < key->arrsize; ++i) { + A = (A >> 32) + (uint64_t)a * b[i] + c[i]; + B = (B >> 32) + (uint64_t)d0 * key->n[i] + (uint32_t)A; + c[i - 1] = (uint32_t)B; + } + + A = (A >> 32) + (B >> 32); + + c[i - 1] = (uint32_t)A; + + if (A >> 32) { + subM(key, c); + } +} + +/** + * Montgomery c[] += 0 * b[] / R % mod + */ +static void montMulAdd0(const struct evb2_public_key *key, + uint32_t *c, + const uint32_t *b) +{ + uint32_t d0 = c[0] * key->n0inv; + uint64_t B = (uint64_t)d0 * key->n[0] + c[0]; + uint32_t i; + + for (i = 1; i < key->arrsize; ++i) { + B = (B >> 32) + (uint64_t)d0 * key->n[i] + c[i]; + c[i - 1] = (uint32_t)B; + } + + c[i - 1] = B >> 32; +} + +/** + * Montgomery c[] = a[] * b[] / R % mod + */ +static void montMul(const struct evb2_public_key *key, + uint32_t *c, + const uint32_t *a, + const uint32_t *b) +{ + uint32_t i; + for (i = 0; i < key->arrsize; ++i) { + c[i] = 0; + } + for (i = 0; i < key->arrsize; ++i) { + montMulAdd(key, c, a[i], b); + } +} + +/* Montgomery c[] = a[] * 1 / R % key. */ +static void montMul1(const struct evb2_public_key *key, + uint32_t *c, + const uint32_t *a) +{ + int i; + + for (i = 0; i < key->arrsize; ++i) + c[i] = 0; + + montMulAdd(key, c, 1, a); + for (i = 1; i < key->arrsize; ++i) + montMulAdd0(key, c, a); +} + +/** + * In-place public exponentiation. + * + * @param key Key to use in signing + * @param inout Input and output big-endian byte array + * @param workbuf32 Work buffer; caller must verify this is + * (3 * key->arrsize) elements long. + * @param exp RSA public exponent: either 65537 (F4) or 3 + */ +static void modpow(const struct evb2_public_key *key, uint8_t *inout, + uint32_t *workbuf32, int exp) +{ + uint32_t *a = workbuf32; + uint32_t *aR = a + key->arrsize; + uint32_t *aaR = aR + key->arrsize; + uint32_t *aaa = aaR; /* Re-use location. */ + int i; + + /* Convert from big endian byte array to little endian word array. */ + for (i = 0; i < (int)key->arrsize; ++i) { + uint32_t tmp = + ((uint32_t)inout[((key->arrsize - 1 - i) * 4) + 0] + << 24) | + (inout[((key->arrsize - 1 - i) * 4) + 1] << 16) | + (inout[((key->arrsize - 1 - i) * 4) + 2] << 8) | + (inout[((key->arrsize - 1 - i) * 4) + 3] << 0); + a[i] = tmp; + } + + montMul(key, aR, a, key->rr); /* aR = a * RR / R mod M */ + if (exp == 3) { + montMul(key, aaR, aR, aR); /* aaR = aR * aR / R mod M */ + montMul(key, a, aaR, aR); /* a = aaR * aR / R mod M */ + montMul1(key, aaa, a); /* aaa = a * 1 / R mod M */ + } else { + /* Exponent 65537 */ + for (i = 0; i < 16; i+=2) { + montMul(key, aaR, aR, aR); /* aaR = aR * aR / R mod M */ + montMul(key, aR, aaR, aaR); /* aR = aaR * aaR / R mod M */ + } + montMul(key, aaa, aR, a); /* aaa = aR * a / R mod M */ + } + + /* Make sure aaa < mod; aaa is at most 1x mod too large. */ + if (evb2_mont_ge(key, aaa)) { + subM(key, aaa); + } + + /* Convert to bigendian byte array */ + for (i = (int)key->arrsize - 1; i >= 0; --i) { + uint32_t tmp = aaa[i]; + *inout++ = (uint8_t)(tmp >> 24); + *inout++ = (uint8_t)(tmp >> 16); + *inout++ = (uint8_t)(tmp >> 8); + *inout++ = (uint8_t)(tmp >> 0); + } +} + +/** + * Safer memcmp() for use in crypto. + * + * Compares the buffers to see if they are equal. Time taken to perform + * the comparison is dependent only on the size, not the relationship of + * the match between the buffers. Note that unlike memcmp(), this only + * indicates inequality, not which buffer is lesser. + * + * @param s1 First buffer + * @param s2 Second buffer + * @param size Number of bytes to compare + * @return 0 if match or size=0, non-zero if at least one byte mismatched. + */ +static vb2_error_t evb2_safe_memcmp(const void *s1, const void *s2, size_t size) +{ + const unsigned char *us1 = s1; + const unsigned char *us2 = s2; + int result = 0; + + if (0 == size) + return 0; + + /* + * Code snippet without data-dependent branch due to Nate Lawson + * (nate(a)root.org) of Root Labs. + */ + while (size--) + result |= *us1++ ^ *us2++; + + return result != 0; +} + +/** + * Round up a number to a multiple of VB2_WORKBUF_ALIGN + * + * @param v Number to round up + * @return The number, rounded up. + */ +static inline uint32_t evb2_wb_round_up(uint32_t v) +{ + return (v + VB2_WORKBUF_ALIGN - 1) & ~(VB2_WORKBUF_ALIGN - 1); +} + +/** + * Allocate space in a work buffer. + * + * Note that the returned buffer will always be aligned to VB2_WORKBUF_ALIGN. + * + * The work buffer acts like a stack, and detailed tracking of allocs and frees + * is not done. The caller must track the size of each allocation and free via + * evb2_workbuf_free() in the reverse order they were allocated. + * + * An acceptable alternate workflow inside a function is to pass in a const + * work buffer, then make a local copy. Allocations done to the local copy + * then don't change the passed-in work buffer, and will effectively be freed + * when the local copy goes out of scope. + * + * @param wb Work buffer + * @param size Requested size in bytes + * @return A pointer to the allocated space, or NULL if error. + */ +static void *evb2_workbuf_alloc(struct evb2_workbuf *wb, uint32_t size) +{ + uint8_t *ptr = wb->buf; + + /* Round up size to work buffer alignment */ + size = evb2_wb_round_up(size); + + if (size > wb->size) + return NULL; + + wb->buf += size; + wb->size -= size; + + return ptr; +} + +/** + * Free the preceding allocation. + * + * Note that the work buffer acts like a stack, and detailed tracking of + * allocs and frees is not done. The caller must track the size of each + * allocation and free them in reverse order. + * + * @param wb Work buffer + * @param size Size of data to free + */ +static void evb2_workbuf_free(struct evb2_workbuf *wb, uint32_t size) +{ + /* Round up size to work buffer alignment */ + size = evb2_wb_round_up(size); + + wb->buf -= size; + wb->size += size; +} + +/* + * PKCS 1.5 padding (from the RSA PKCS#1 v2.1 standard) + * + * Depending on the RSA key size and hash function, the padding is calculated + * as follows: + * + * 0x00 || 0x01 || PS || 0x00 || T + * + * T: DER Encoded DigestInfo value which depends on the hash function used. + * + * SHA-1: (0x)30 21 30 09 06 05 2b 0e 03 02 1a 05 00 04 14 || H. + * SHA-256: (0x)30 31 30 0d 06 09 60 86 48 01 65 03 04 02 01 05 00 04 20 || H. + * SHA-512: (0x)30 51 30 0d 06 09 60 86 48 01 65 03 04 02 03 05 00 04 40 || H. + * + * Length(T) = 35 octets for SHA-1 + * Length(T) = 51 octets for SHA-256 + * Length(T) = 83 octets for SHA-512 + * + * PS: octet string consisting of {Length(RSA Key) - Length(T) - 3} 0xFF + */ +static const uint8_t sha1_tail[] = { + 0x00,0x30,0x21,0x30,0x09,0x06,0x05,0x2b, + 0x0e,0x03,0x02,0x1a,0x05,0x00,0x04,0x14 +}; + +static const uint8_t sha256_tail[] = { + 0x00,0x30,0x31,0x30,0x0d,0x06,0x09,0x60, + 0x86,0x48,0x01,0x65,0x03,0x04,0x02,0x01, + 0x05,0x00,0x04,0x20 +}; + +static const uint8_t sha512_tail[] = { + 0x00,0x30,0x51,0x30,0x0d,0x06,0x09,0x60, + 0x86,0x48,0x01,0x65,0x03,0x04,0x02,0x03, + 0x05,0x00,0x04,0x40 +}; + +/** + * Check pkcs 1.5 padding bytes + * + * @param sig Signature to verify + * @param key Key to take signature and hash algorithms from + * @return VB2_SUCCESS, or non-zero if error. + */ +static vb2_error_t evb2_check_padding(const uint8_t *sig, + const struct evb2_public_key *key) +{ + /* Determine padding to use depending on the signature type */ + uint32_t sig_size = evb2_rsa_sig_size(key->sig_alg); + uint32_t hash_size = vb2_digest_size(key->hash_alg); + uint32_t pad_size = sig_size - hash_size; + const uint8_t *tail; + uint32_t tail_size; + int result = 0; + int i; + + if (!sig_size || !hash_size || hash_size > sig_size) + return VB2_ERROR_RSA_PADDING_SIZE; + + switch (key->hash_alg) { + case VB2_HASH_SHA1: + tail = sha1_tail; + tail_size = sizeof(sha1_tail); + break; + case VB2_HASH_SHA256: + tail = sha256_tail; + tail_size = sizeof(sha256_tail); + break; + case VB2_HASH_SHA512: + tail = sha512_tail; + tail_size = sizeof(sha512_tail); + break; + default: + return VB2_ERROR_RSA_PADDING_ALGORITHM; + } + + /* First 2 bytes are always 0x00 0x01 */ + result |= *sig++ ^ 0x00; + result |= *sig++ ^ 0x01; + + /* Then 0xff bytes until the tail */ + for (i = 0; i < pad_size - tail_size - 2; i++) + result |= *sig++ ^ 0xff; + + /* + * Then the tail. Even though there are probably no timing issues + * here, we use evb2_safe_memcmp() just to be on the safe side. + */ + result |= evb2_safe_memcmp(sig, tail, tail_size); + + return result ? VB2_ERROR_RSA_PADDING : VB2_SUCCESS; +} + +/** + * Return the exponent used by an RSA algorithm + * + * @param sig_alg Signature algorithm + * @return The exponent to use (3 or 65537(F4)), or 0 if error. + */ +static uint32_t evb2_rsa_exponent(enum vb2_signature_algorithm sig_alg) +{ + switch (sig_alg) { + case VB2_SIG_RSA1024: + case VB2_SIG_RSA2048: + case VB2_SIG_RSA4096: + case VB2_SIG_RSA8192: + return 65537; + case VB2_SIG_RSA2048_EXP3: + case VB2_SIG_RSA3072_EXP3: + return 3; + default: + return 0; + } +} + +/** + * Verify a RSA PKCS1.5 signature against an expected hash digest. + * + * @param key Key to use in signature verification + * @param sig Signature to verify (destroyed in process) + * @param digest Digest of signed data + * @param wb Work buffer + * @return VB2_SUCCESS, or non-zero if error. + */ +static vb2_error_t evb2_rsa_verify_digest(const struct evb2_public_key *key, + uint8_t *sig, const uint8_t *digest, + const struct evb2_workbuf *wb) +{ + struct evb2_workbuf wblocal = *wb; + uint32_t *workbuf32; + uint32_t key_bytes; + int sig_size; + int pad_size; + int exp; + vb2_error_t rv; + + if (!key || !sig || !digest) + return VB2_ERROR_RSA_VERIFY_PARAM; + + sig_size = evb2_rsa_sig_size(key->sig_alg); + exp = evb2_rsa_exponent(key->sig_alg); + if (!sig_size || !exp) { + EVB2_DEBUG("Invalid signature type!\n"); + return VB2_ERROR_RSA_VERIFY_ALGORITHM; + } + + /* Signature length should be same as key length */ + key_bytes = key->arrsize * sizeof(uint32_t); + if (key_bytes != sig_size) { + EVB2_DEBUG("Signature is of incorrect length!\n"); + return VB2_ERROR_RSA_VERIFY_SIG_LEN; + } + + workbuf32 = evb2_workbuf_alloc(&wblocal, 3 * key_bytes); + if (!workbuf32) { + EVB2_DEBUG("ERROR - vboot2 work buffer too small!\n"); + return VB2_ERROR_RSA_VERIFY_WORKBUF; + } + + modpow(key, sig, workbuf32, exp); + + evb2_workbuf_free(&wblocal, 3 * key_bytes); + + /* + * Check padding. Only fail immediately if the padding size is bad. + * Otherwise, continue on to check the digest to reduce the risk of + * timing based attacks. + */ + rv = evb2_check_padding(sig, key); + if (rv == VB2_ERROR_RSA_PADDING_SIZE) + return rv; + + /* + * Check digest. Even though there are probably no timing issues here, + * use evb2_safe_memcmp() just to be on the safe side. (That's also why + * we don't return before this check if the padding check failed.) + */ + pad_size = sig_size - vb2_digest_size(key->hash_alg); + if (evb2_safe_memcmp(sig + pad_size, digest, key_bytes - pad_size)) { + EVB2_DEBUG("Digest check failed!\n"); + if (!rv) + rv = VB2_ERROR_RSA_VERIFY_DIGEST; + } + + return rv; +} + +/** + * Return the description of an object starting with a evb21_struct_common + * header. + * + * Does not sanity-check the buffer; merely returns the pointer. + * + * @param buf Pointer to common object + * @return A pointer to description or an empty string if none. + */ +static const char *evb21_common_desc(const void *buf) +{ + const struct evb21_struct_common *c = buf; + + return c->desc_size ? (const char *)c + c->fixed_size : ""; +} + +/** + * Verify the common struct header is fully contained in its parent data + * + * Also verifies the description is either zero-length or null-terminated. + * + * @param parent Parent data + * @param parent_size Parent size in bytes + * @return VB2_SUCCESS, or non-zero if error. + */ +static vb2_error_t evb21_verify_common_header(const void *parent, + uint32_t parent_size) +{ + const struct evb21_struct_common *c = parent; + + /* Parent buffer size must be at least the claimed total size */ + if (parent_size < c->total_size) + return VB2_ERROR_COMMON_TOTAL_SIZE; + + /* + * And big enough for the fixed size, which itself must be at least as + * big as the common struct header. + */ + if (c->total_size < c->fixed_size || c->fixed_size < sizeof(*c)) + return VB2_ERROR_COMMON_FIXED_SIZE; + + /* Make sure sizes are all multiples of 32 bits */ + if (!evb2_aligned(c->total_size, sizeof(uint32_t))) + return VB2_ERROR_COMMON_TOTAL_UNALIGNED; + if (!evb2_aligned(c->fixed_size, sizeof(uint32_t))) + return VB2_ERROR_COMMON_FIXED_UNALIGNED; + if (!evb2_aligned(c->desc_size, sizeof(uint32_t))) + return VB2_ERROR_COMMON_DESC_UNALIGNED; + + /* Check description */ + if (c->desc_size > 0) { + /* Make sure description fits and doesn't wrap */ + if (c->fixed_size + c->desc_size < c->fixed_size) + return VB2_ERROR_COMMON_DESC_WRAPS; + if (c->fixed_size + c->desc_size > c->total_size) + return VB2_ERROR_COMMON_DESC_SIZE; + + /* Description must be null-terminated */ + if (evb21_common_desc(c)[c->desc_size - 1] != 0) + return VB2_ERROR_COMMON_DESC_TERMINATOR; + } + + return VB2_SUCCESS; +} + +/** + * Verify a member is within the data for a parent object + * + * @param parent Parent data (starts with struct evb21_struct_common) + * @param min_offset Pointer to minimum offset where member can be located. + * If this offset is 0 on input, uses the size of the + * fixed header (and description, if any). This will be + * updated on return to the end of the passed member. On + * error, the value of min_offset is undefined. + * @param member_offset Offset of member data from start of parent, in bytes + * @param member_size Size of member data, in bytes + * @return VB2_SUCCESS, or non-zero if error. + */ +static vb2_error_t evb21_verify_common_member(const void *parent, + uint32_t *min_offset, + uint32_t member_offset, + uint32_t member_size) +{ + const struct evb21_struct_common *c = parent; + uint32_t member_end = member_offset + member_size; + + /* Make sure member doesn't wrap */ + if (member_end < member_offset) + return VB2_ERROR_COMMON_MEMBER_WRAPS; + + /* Member offset and size must be 32-bit aligned */ + if (!evb2_aligned(member_offset, sizeof(uint32_t)) || + !evb2_aligned(member_size, sizeof(uint32_t))) + return VB2_ERROR_COMMON_MEMBER_UNALIGNED; + + /* Initialize minimum offset if necessary */ + if (!*min_offset) + *min_offset = c->fixed_size + c->desc_size; + + /* Member must be after minimum offset */ + if (member_offset < *min_offset) + return VB2_ERROR_COMMON_MEMBER_OVERLAP; + + /* Member must end before total size */ + if (member_end > c->total_size) + return VB2_ERROR_COMMON_MEMBER_SIZE; + + /* Update minimum offset for subsequent checks */ + *min_offset = member_end; + + return VB2_SUCCESS; +} + +/** + * Return expected signature size for a signature/hash algorithm pair + * + * @param sig_alg Signature algorithm + * @param hash_alg Hash algorithm + * @return The signature size, or zero if error / unsupported algorithm. + */ +static uint32_t evb2_sig_size(enum vb2_signature_algorithm sig_alg, + enum vb2_hash_algorithm hash_alg) +{ + uint32_t digest_size = vb2_digest_size(hash_alg); + + /* Fail if we don't support the hash algorithm */ + if (!digest_size) + return 0; + + /* Handle unsigned hashes */ + if (sig_alg == VB2_SIG_NONE) + return digest_size; + + return evb2_rsa_sig_size(sig_alg); +} + +/** + * Return the signature data for a signature + */ +static uint8_t *evb21_signature_data(struct evb21_signature *sig) +{ + return (uint8_t *)sig + sig->sig_offset; +} + +/** + * Verify a signature against an expected hash digest. + * + * @param key Key to use in signature verification + * @param sig Signature to verify (may be destroyed in process) + * @param digest Digest of signed data + * @param wb Work buffer + * @return VB2_SUCCESS, or non-zero if error. + */ +static vb2_error_t evb21_verify_digest(const struct evb2_public_key *key, + struct evb21_signature *sig, + const uint8_t *digest, + const struct evb2_workbuf *wb) +{ + uint32_t key_sig_size = evb2_sig_size(key->sig_alg, key->hash_alg); + + /* If we can't figure out the signature size, key algorithm was bad */ + if (!key_sig_size) + return VB2_ERROR_VDATA_ALGORITHM; + + /* Make sure the signature and key algorithms match */ + if (key->sig_alg != sig->sig_alg || key->hash_alg != sig->hash_alg) + return VB2_ERROR_VDATA_ALGORITHM_MISMATCH; + + if (sig->sig_size != key_sig_size) + return VB2_ERROR_VDATA_SIG_SIZE; + + if (key->sig_alg == VB2_SIG_NONE) { + /* Bare hash */ + if (evb2_safe_memcmp(evb21_signature_data(sig), + digest, key_sig_size)) + return VB2_ERROR_VDATA_VERIFY_DIGEST; + + return VB2_SUCCESS; + } else { + /* RSA-signed digest */ + return evb2_rsa_verify_digest(key, + evb21_signature_data(sig), + digest, wb); + } +} + +/** + * Return the size of a pre-processed RSA public key. + * + * @param sig_alg Signature algorithm + * @return The size of the preprocessed key in bytes, or 0 if error. + */ +static uint32_t evb2_packed_key_size(enum vb2_signature_algorithm sig_alg) +{ + uint32_t sig_size = evb2_rsa_sig_size(sig_alg); + + if (!sig_size) + return 0; + + /* + * Total size needed by a RSAPublicKey buffer is = + * 2 * key_len bytes for the n and rr arrays + * + sizeof len + sizeof n0inv. + */ + return 2 * sig_size + 2 * sizeof(uint32_t); +} + +/** + * Unpack the RSA data fields for a public key + * + * This is called by evb21_unpack_key() to extract the arrays from a packed key. + * These elements of *key will point inside the key_data buffer. + * + * @param key Destination key for RSA data fields + * @param key_data Packed key data (from inside a packed key buffer) + * @param key_size Size of packed key data in bytes + */ +static vb2_error_t evb2_unpack_key_data(struct evb2_public_key *key, + const uint8_t *key_data, + uint32_t key_size) +{ + const uint32_t *buf32 = (const uint32_t *)key_data; + uint32_t expected_key_size = evb2_packed_key_size(key->sig_alg); + + /* Make sure buffer is the correct length */ + if (!expected_key_size || expected_key_size != key_size) { + EVB2_DEBUG("Wrong key size for algorithm\n"); + return VB2_ERROR_UNPACK_KEY_SIZE; + } + + /* Check for alignment */ + if (!evb2_aligned(buf32, sizeof(uint32_t))) + return VB2_ERROR_UNPACK_KEY_ALIGN; + + key->arrsize = buf32[0]; + + /* Sanity check key array size */ + if (key->arrsize * sizeof(uint32_t) != evb2_rsa_sig_size(key->sig_alg)) + return VB2_ERROR_UNPACK_KEY_ARRAY_SIZE; + + key->n0inv = buf32[1]; + + /* Arrays point inside the key data */ + key->n = buf32 + 2; + key->rr = buf32 + 2 + key->arrsize; + + return VB2_SUCCESS; +} + +vb2_error_t evb21_unpack_key(struct evb2_public_key *key, const uint8_t *buf, + uint32_t size) +{ + const struct evb21_packed_key *pkey = + (const struct evb21_packed_key *)buf; + uint32_t sig_size; + uint32_t min_offset = 0; + vb2_error_t rv; + + /* Check magic number */ + if (pkey->c.magic != VB21_MAGIC_PACKED_KEY) + return VB2_ERROR_UNPACK_KEY_MAGIC; + + rv = evb21_verify_common_header(buf, size); + if (rv) + return rv; + + /* Make sure key data is inside */ + rv = evb21_verify_common_member(pkey, &min_offset, + pkey->key_offset, pkey->key_size); + if (rv) + return rv; + + /* + * Check for compatible version. No need to check minor version, since + * that's compatible across readers matching the major version, and we + * haven't added any new fields. + */ + if (pkey->c.struct_version_major != VB21_PACKED_KEY_VERSION_MAJOR) + return VB2_ERROR_UNPACK_KEY_STRUCT_VERSION; + + /* Copy key algorithms */ + key->hash_alg = pkey->hash_alg; + if (!vb2_digest_size(key->hash_alg)) + return VB2_ERROR_UNPACK_KEY_HASH_ALGORITHM; + + key->sig_alg = pkey->sig_alg; + if (key->sig_alg != VB2_SIG_NONE) { + sig_size = evb2_rsa_sig_size(key->sig_alg); + if (!sig_size) + return VB2_ERROR_UNPACK_KEY_SIG_ALGORITHM; + rv = evb2_unpack_key_data( + key, + (const uint8_t *)pkey + pkey->key_offset, + pkey->key_size); + if (rv) + return rv; + } + + /* Key description */ + key->desc = evb21_common_desc(pkey); + key->version = pkey->key_version; + key->id = &pkey->id; + + return VB2_SUCCESS; +} + +uint32_t evb2_rsa_sig_size(enum vb2_signature_algorithm sig_alg) +{ + switch (sig_alg) { + case VB2_SIG_RSA1024: + return 1024 / 8; + case VB2_SIG_RSA2048: + case VB2_SIG_RSA2048_EXP3: + return 2048 / 8; + case VB2_SIG_RSA3072_EXP3: + return 3072 / 8; + case VB2_SIG_RSA4096: + return 4096 / 8; + case VB2_SIG_RSA8192: + return 8192 / 8; + default: + return 0; + } +} + +vb2_error_t evb21_verify_data(const void *data, uint32_t size, + struct evb21_signature *sig, + const struct evb2_public_key *key, + const struct evb2_workbuf *wb) +{ + struct evb2_workbuf wblocal = *wb; + struct vb2_digest_context *dc; + uint8_t *digest; + uint32_t digest_size; + vb2_error_t rv; + + if (sig->data_size != size) { + EVB2_DEBUG("Wrong amount of data signed.\n"); + return VB2_ERROR_VDATA_SIZE; + } + + /* Digest goes at start of work buffer */ + digest_size = vb2_digest_size(key->hash_alg); + if (!digest_size) + return VB2_ERROR_VDATA_DIGEST_SIZE; + + digest = evb2_workbuf_alloc(&wblocal, digest_size); + if (!digest) + return VB2_ERROR_VDATA_WORKBUF_DIGEST; + + /* Hashing requires temp space for the context */ + dc = evb2_workbuf_alloc(&wblocal, sizeof(*dc)); + if (!dc) + return VB2_ERROR_VDATA_WORKBUF_HASHING; + + rv = vb2_digest_init(dc, key->hash_alg); + if (rv) + return rv; + + rv = vb2_digest_extend(dc, data, size); + if (rv) + return rv; + + rv = vb2_digest_finalize(dc, digest, digest_size); + if (rv) + return rv; + + evb2_workbuf_free(&wblocal, sizeof(*dc)); + + return evb21_verify_digest(key, sig, digest, &wblocal); +} diff --git a/src/vendorcode/eltan/security/verified_boot/eltan_vb21.h b/src/vendorcode/eltan/security/verified_boot/eltan_vb21.h new file mode 100644 index 0000000..c2f7982 --- /dev/null +++ b/src/vendorcode/eltan/security/verified_boot/eltan_vb21.h @@ -0,0 +1,241 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ELTAN_VB21_H +#define ELTAN_VB21_H + +#include <vb2_api.h> +#include <vb2_sha.h> + +#define EVB2_DEBUG(format, args...) \ + printk(BIOS_INFO, format, ## args) + +/* Check if a pointer is aligned on an align-byte boundary */ +#define evb2_aligned(ptr, align) (!(((uintptr_t)(ptr)) & ((align) - 1))) + +/* + * Magic numbers used by evb21_struct_common.magic. + * + * All valid numbers should be listed here to avoid accidental overlap. + * Numbers start at a large value, so that previous parsers (which stored + * things like lengths and offsets at that field) will detect and reject new + * structs as invalid. + */ +enum evb21_struct_common_magic { + /* "Vb2P" = evb21_packed_key.c.magic */ + VB21_MAGIC_PACKED_KEY = 0x50326256, +}; + +/* Work buffer */ +struct evb2_workbuf { + uint8_t *buf; + uint32_t size; +}; + +#define EVB2_ID_NUM_BYTES 20 + +struct evb2_id { + uint8_t raw[EVB2_ID_NUM_BYTES]; +} __attribute__((packed)); + +/* Public key structure in RAM */ +struct evb2_public_key { + uint32_t arrsize; /* Length of n[] and rr[] in number of uint32_t */ + uint32_t n0inv; /* -1 / n[0] mod 2^32 */ + const uint32_t *n; /* Modulus as little endian array */ + const uint32_t *rr; /* R^2 as little endian array */ + enum vb2_signature_algorithm sig_alg; /* Signature algorithm */ + enum vb2_hash_algorithm hash_alg; /* Hash algorithm */ + const char *desc; /* Description */ + uint32_t version; /* Key version */ + const struct evb2_id *id; /* Key ID */ +}; + +/* + * Generic struct header for all vboot2.1 structs. This makes it easy to + * automatically parse and identify vboot structs (e.g., in futility). This + * must be the first member of the parent vboot2.1 struct. + */ +struct evb21_struct_common { + /* Magic number; see evb21_struct_common_magic for expected values */ + uint32_t magic; + + /* + * Parent struct version; see each struct for the expected value. + * + * How to handle struct version mismatches, if the parser is version + * A.b and the data is version C.d: + * 1) If A.b == C.d, we're good. + * 2) If A != C, the data cannot be parsed at all. + * 3) If b < d, C.d is a newer version of data which is backwards- + * compatible to old parsers. We're good. + * 4) If b > d, C.d is an older version of data. The parser should + * use default values for fields added after version d. We're + * good. + * + * Struct versions start at 3.0, since the highest version of the old + * structures was 2.1. This way, there is no possibility of collision + * for old code which depends on the version number. + */ + uint16_t struct_version_major; + uint16_t struct_version_minor; + + /* + * Size of the parent structure and all its data, including the + * description and any necessary padding. That is, all data must lie + * in a contiguous region of <total_size> bytes starting at the first + * byte of this header. + */ + uint32_t total_size; + + /* + * Size of the fixed portion of the parent structure. If a description + * is present, it must start at this offset. + */ + uint32_t fixed_size; + + /* + * The object may contain an ASCII description following the fixed + * portion of the structure. If it is present, it must be + * null-terminated, and padded with 0 (null) bytes to a multiple of 32 + * bits. + * + * Size of ASCII description in bytes, counting null terminator and + * padding (if any). Set 0 if no description is present. If non-zero, + * there must be a null terminator (0) at offset (fixed_size + + * desc_size - 1). + */ + uint32_t desc_size; +} __attribute__((packed)); + +/* + * Signature data + * + * The signature data must be arranged like this: + * 1) evb21_signature header struct h + * 2) Signature description (pointed to by h.c.fixed_size) + * 3) Signature data (pointed to by h.sig_offset) + */ +struct evb21_signature { + /* Common header fields */ + struct evb21_struct_common c; + + /* Offset of signature data from start of this struct */ + uint32_t sig_offset; + + /* Size of signature data in bytes */ + uint32_t sig_size; + + /* Size of the data block which was signed in bytes */ + uint32_t data_size; + + /* Signature algorithm used (enum vb2_signature_algorithm) */ + uint16_t sig_alg; + + /* Hash digest algorithm used (enum vb2_hash_algorithm) */ + uint16_t hash_alg; + + /* + * ID for the signature. + * + * If this is a keyblock signature entry, this is the ID of the key + * used to generate this signature. This allows the firmware to + * quickly determine which signature block (if any) goes with the key + * being used by the firmware. + * + * If this is a preamble hash entry, this is the ID of the data type + * being hashed. There is no key ID, because sig_alg=VB2_ALG_NONE. + */ + struct evb2_id id; +} __attribute__((packed)); + +/* Current version of evb21_packed_key struct */ +#define VB21_PACKED_KEY_VERSION_MAJOR 3 +#define VB21_PACKED_KEY_VERSION_MINOR 0 + +/* + * Packed public key data + * + * The key data must be arranged like this: + * 1) evb21_packed_key header struct h + * 2) Key description (pointed to by h.c.fixed_size) + * 3) Key data key (pointed to by h.key_offset) + */ +struct evb21_packed_key { + /* Common header fields */ + struct evb21_struct_common c; + + /* Offset of key data from start of this struct */ + uint32_t key_offset; + + /* Size of key data in bytes (NOT strength of key in bits) */ + uint32_t key_size; + + /* Signature algorithm used by the key (enum vb2_signature_algorithm) */ + uint16_t sig_alg; + + /* + * Hash digest algorithm used with the key (enum vb2_hash_algorithm). + * This is explicitly specified as part of the key to prevent use of a + * strong key with a weak hash. + */ + uint16_t hash_alg; + + /* Key version */ + uint32_t key_version; + + /* Key ID */ + struct evb2_id id; +} __attribute__((packed)); + +/** + * Unpack a key for use in verification + * + * The elements of the unpacked key will point into the source buffer, so don't + * free the source buffer until you're done with the key. + * + * @param key Destintion for unpacked key + * @param buf Source buffer containing packed key + * @param size Size of buffer in bytes + * @return VB2_SUCCESS, or non-zero error code if error. + */ +vb2_error_t evb21_unpack_key(struct evb2_public_key *key, const uint8_t *buf, + uint32_t size); + +/** + * Verify data matches signature. + * + * @param data Data to verify + * @param size Size of data buffer. Note that amount of data to + * actually validate is contained in sig->data_size. + * @param sig Signature of data (destroyed in process) + * @param key Key to use to validate signature + * @param wb Work buffer + * @return VB2_SUCCESS, or non-zero error code if error. + */ +vb2_error_t evb21_verify_data(const void *data, uint32_t size, + struct evb21_signature *sig, + const struct evb2_public_key *key, + const struct evb2_workbuf *wb); + +/** + * Return the size of a RSA signature + * + * @param sig_alg Signature algorithm + * @return The size of the signature in bytes, or 0 if error. + */ +uint32_t evb2_rsa_sig_size(enum vb2_signature_algorithm sig_alg); + +#endif //ELTAN_VB21_H diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index bc502c9..7d39a44 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -16,8 +16,10 @@ #include <boot_device.h> #include <bootmem.h> #include <cbfs.h> -#include <vboot_check.h> -#include <vboot_common.h> +#include <security/vboot/vboot_common.h> +#include <vb2_sha.h> +#include <vendorcode/eltan/security/verified_boot/vboot_check.h> +#include <vendorcode/eltan/security/verified_boot/eltan_vb21.h> #define RSA_PUBLICKEY_FILE_NAME "vboot_public_key.bin" @@ -32,11 +34,11 @@ int verified_boot_check_manifest(void) { uint8_t *buffer; - uint8_t sig_buffer[1024]; /* used to build vb21_signature */ + uint8_t sig_buffer[1024]; /* used to build evb21_signature */ size_t size = 0; - struct vb2_public_key key; - struct vb2_workbuf wb; - struct vb21_signature *vb2_sig_hdr = (struct vb21_signature *)sig_buffer; + struct evb2_public_key key; + struct evb2_workbuf wb; + struct evb21_signature *evb2_sig_hdr = (struct evb21_signature *)sig_buffer; uint8_t wb_buffer[1024]; buffer = cbfs_boot_map_with_leak(RSA_PUBLICKEY_FILE_NAME, CBFS_TYPE_RAW, &size); @@ -51,14 +53,14 @@ goto fail; } - if (vb21_unpack_key(&key, buffer, size)) { + if (evb21_unpack_key(&key, buffer, size)) { printk(BIOS_ERR, "ERROR: Invalid public key!\n"); goto fail; } cbfs_boot_map_with_leak("oemmanifest.bin", CBFS_TYPE_RAW, &size); if (size != (CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE) + - vb2_rsa_sig_size(VB2_SIG_RSA2048)) { + evb2_rsa_sig_size(VB2_SIG_RSA2048)) { printk(BIOS_ERR, "ERROR: Incorrect manifest size!\n"); goto fail; } @@ -67,18 +69,18 @@ wb.buf = (uint8_t *)&wb_buffer; wb.size = sizeof(wb_buffer); - /* Build vb2_sig_hdr buffer */ - vb2_sig_hdr->sig_offset = sizeof(struct vb21_signature) + + /* Build evb2_sig_hdr buffer */ + evb2_sig_hdr->sig_offset = sizeof(struct evb21_signature) + (CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE); - vb2_sig_hdr->sig_alg = VB2_SIG_RSA2048; - vb2_sig_hdr->sig_size = vb2_rsa_sig_size(VB2_SIG_RSA2048); - vb2_sig_hdr->hash_alg = HASH_ALG; - vb2_sig_hdr->data_size = CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE; - memcpy(&sig_buffer[sizeof(struct vb21_signature)], + evb2_sig_hdr->sig_alg = VB2_SIG_RSA2048; + evb2_sig_hdr->sig_size = evb2_rsa_sig_size(VB2_SIG_RSA2048); + evb2_sig_hdr->hash_alg = HASH_ALG; + evb2_sig_hdr->data_size = CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE; + memcpy(&sig_buffer[sizeof(struct evb21_signature)], (uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC, size); - if (vb21_verify_data(&sig_buffer[sizeof(struct vb21_signature)], vb2_sig_hdr->data_size, - (struct vb21_signature *)&sig_buffer, &key, &wb)) { + if (evb21_verify_data(&sig_buffer[sizeof(struct evb21_signature)], evb2_sig_hdr->data_size, + (struct evb21_signature *)&sig_buffer, &key, &wb)) { printk(BIOS_ERR, "ERROR: Signature verification failed for hash table\n"); goto fail; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae58a0c42161ddfec9908f9867286e3dc1f055a2 Gerrit-Change-Number: 37654 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: soc/intel/common/systemagent: Add SOC_INTEL_COMMON_BLOCK_SA_VERSION_2
by Subrata Banik (Code Review) Aug. 7, 2023

Aug. 7, 2023

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38456 ) Change subject: soc/intel/common/systemagent: Add SOC_INTEL_COMMON_BLOCK_SA_VERSION_2 ...................................................................... soc/intel/common/systemagent: Add SOC_INTEL_COMMON_BLOCK_SA_VERSION_2 System Agent (SA) register 0x60:PCIEXBAR register LENGTH offset definition has been changed for newer SoC. This change provides a new Kconfig option that can be selected by SoCs using these new bit definitions of LENGTH. Common code takes care of setting the right value for pciex length depending upon the version selected by SOC. TEST=DSDT dump shows PCIEXBAR.LENGTH offset (3:1) for TGL Change-Id: Ifa00c4e6b872896ace975f1c6bd56c6efb172410 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c 4 files changed, 62 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/38456/1 diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index d271dda..ac9e843 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -40,8 +40,13 @@ Offset(0x60), /* PCIEXBAR (0:0:0:60) */ PXEN, 1, /* Enable */ - PXSZ, 2, /* PCI Express Size */ +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA_VERSION_2) + PXSZ, 3, /* PCI Express Size */ + , 22, +#else + PXSZ, 2, /* PCI Express Size */ , 23, +#endif PXBR, 6, /* PCI Express BAR [31:26] */ Offset(0x68), /* DMIBAR (0:0:0:68) */ @@ -241,7 +246,15 @@ /* Get PCIe Length */ Method (GPCL, 0, Serialized) { +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA_VERSION_2) + If (LLess (\_SB.PCI0.MCHC.PXSZ, 3)) { + ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0) + } Else { + Store(0x10000000, Local0) + } +#else ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0) +#endif Return (Local0) } diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 1222573..017d85e 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -3,12 +3,24 @@ help Intel Processor common System Agent support +config SOC_INTEL_COMMON_BLOCK_SA_VERSION_2 + bool + default n + select SOC_INTEL_COMMON_BLOCK_SA + help + Intel Processor Common System Agent support version 2 to handle + DRAM changes introduced in TGL. + config MMCONF_BASE_ADDRESS hex default 0xe0000000 config SA_PCIEX_LENGTH hex + default 0x100000000 if (PCIEX_LENGTH_4096MB) + default 0x80000000 if (PCIEX_LENGTH_2048MB) + default 0x40000000 if (PCIEX_LENGTH_1024MB) + default 0x20000000 if (PCIEX_LENGTH_512MB) default 0x10000000 if (PCIEX_LENGTH_256MB) default 0x8000000 if (PCIEX_LENGTH_128MB) default 0x4000000 if (PCIEX_LENGTH_64MB) @@ -16,6 +28,22 @@ help This option allows you to select length of PCIEX region. +if SOC_INTEL_COMMON_BLOCK_SA_VERSION_2 + +config PCIEX_LENGTH_4096MB + bool + +config PCIEX_LENGTH_2048MB + bool + +config PCIEX_LENGTH_1024MB + bool + +config PCIEX_LENGTH_512MB + bool + +endif + config PCIEX_LENGTH_256MB bool diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index b89a10d..5f54c72 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -31,6 +31,12 @@ #define DPR_PRS (1 << 1) #define DPR_SIZE_MASK 0xff0 +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA_VERSION_2) +#define PCIEXBAR_LENGTH_4096MB 6 +#define PCIEXBAR_LENGTH_2048MB 5 +#define PCIEXBAR_LENGTH_1024MB 4 +#define PCIEXBAR_LENGTH_512MB 3 +#endif #define PCIEXBAR_LENGTH_64MB 2 #define PCIEXBAR_LENGTH_128MB 1 #define PCIEXBAR_LENGTH_256MB 0 diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index d6f129d..f0a867a 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -40,6 +40,20 @@ /* Get PCI Express Region Length */ switch (CONFIG_SA_PCIEX_LENGTH) { +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA_VERSION_2) + case 4096 * MiB: + pciexbar_length = PCIEXBAR_LENGTH_4096MB; + break; + case 2048 * MiB: + pciexbar_length = PCIEXBAR_LENGTH_2048MB; + break; + case 1024 * MiB: + pciexbar_length = PCIEXBAR_LENGTH_1024MB; + break; + case 512 * MiB: + pciexbar_length = PCIEXBAR_LENGTH_512MB; + break; +#endif case 256 * MiB: pciexbar_length = PCIEXBAR_LENGTH_256MB; break; -- To view, visit https://review.coreboot.org/c/coreboot/+/38456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa00c4e6b872896ace975f1c6bd56c6efb172410 Gerrit-Change-Number: 38456 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

7 41

Change in coreboot[master]: [WIP]mainboard/lenovo: do initial commit for t540p
by Patrick Elsen (Code Review) Aug. 7, 2023

Aug. 7, 2023

Patrick Elsen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38204 ) Change subject: [WIP]mainboard/lenovo: do initial commit for t540p ...................................................................... [WIP]mainboard/lenovo: do initial commit for t540p Based off of t440p. Change-Id: I02ecde6999d1b5ca7741371273edd90297899fa0 Signed-off-by: Patrick Elsen <pelsen(a)xfbs.net> --- A src/mainboard/lenovo/t540p/Kconfig A src/mainboard/lenovo/t540p/Kconfig.name A src/mainboard/lenovo/t540p/Makefile.inc A src/mainboard/lenovo/t540p/acpi/ec.asl A src/mainboard/lenovo/t540p/acpi/platform.asl A src/mainboard/lenovo/t540p/acpi/superio.asl A src/mainboard/lenovo/t540p/acpi_tables.c A src/mainboard/lenovo/t540p/board_info.txt A src/mainboard/lenovo/t540p/devicetree.cb A src/mainboard/lenovo/t540p/dsdt.asl A src/mainboard/lenovo/t540p/gma-mainboard.ads A src/mainboard/lenovo/t540p/gpio.c A src/mainboard/lenovo/t540p/hda_verb.c A src/mainboard/lenovo/t540p/mainboard.c A src/mainboard/lenovo/t540p/romstage.c A src/mainboard/lenovo/t540p/smihandler.c 16 files changed, 819 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/38204/1 diff --git a/src/mainboard/lenovo/t540p/Kconfig b/src/mainboard/lenovo/t540p/Kconfig new file mode 100644 index 0000000..9c136a4 --- /dev/null +++ b/src/mainboard/lenovo/t540p/Kconfig @@ -0,0 +1,41 @@ +if BOARD_LENOVO_THINKPAD_T540P + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_2048 # FIXME: correct this + select CPU_INTEL_HASWELL + select EC_LENOVO_H8 + select EC_LENOVO_PMH7 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default lenovo/t540p + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad T540p" + +config VGA_BIOS_FILE + string + default "pci8086,0416.rom" + +config VGA_BIOS_ID + string + default "8086,0416" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/lenovo/t540p/Kconfig.name b/src/mainboard/lenovo/t540p/Kconfig.name new file mode 100644 index 0000000..a7c6910 --- /dev/null +++ b/src/mainboard/lenovo/t540p/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKPAD_T540P + bool "ThinkPad T540p" diff --git a/src/mainboard/lenovo/t540p/Makefile.inc b/src/mainboard/lenovo/t540p/Makefile.inc new file mode 100644 index 0000000..fa6e7af --- /dev/null +++ b/src/mainboard/lenovo/t540p/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t540p/acpi/ec.asl b/src/mainboard/lenovo/t540p/acpi/ec.asl new file mode 100644 index 0000000..c3569e8 --- /dev/null +++ b/src/mainboard/lenovo/t540p/acpi/ec.asl @@ -0,0 +1 @@ +#include <ec/lenovo/h8/acpi/ec.asl> diff --git a/src/mainboard/lenovo/t540p/acpi/platform.asl b/src/mainboard/lenovo/t540p/acpi/platform.asl new file mode 100644 index 0000000..dfced7a --- /dev/null +++ b/src/mainboard/lenovo/t540p/acpi/platform.asl @@ -0,0 +1,12 @@ +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.RADI(0) +} diff --git a/src/mainboard/lenovo/t540p/acpi/superio.asl b/src/mainboard/lenovo/t540p/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/lenovo/t540p/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t540p/acpi_tables.c b/src/mainboard/lenovo/t540p/acpi_tables.c new file mode 100644 index 0000000..5dc98d8 --- /dev/null +++ b/src/mainboard/lenovo/t540p/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/lynxpoint/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/t540p/board_info.txt b/src/mainboard/lenovo/t540p/board_info.txt new file mode 100644 index 0000000..db677c6 --- /dev/null +++ b/src/mainboard/lenovo/t540p/board_info.txt @@ -0,0 +1,2 @@ +Category: laptop +FIXME: put ROM package, ROM socketed, ROM protocol, Flashrom support, Release year diff --git a/src/mainboard/lenovo/t540p/devicetree.cb b/src/mainboard/lenovo/t540p/devicetree.cb new file mode 100644 index 0000000..3ebaa42 --- /dev/null +++ b/src/mainboard/lenovo/t540p/devicetree.cb @@ -0,0 +1,166 @@ +chip northbridge/intel/haswell + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + register "gpu_cpu_backlight" = "0x12ba12ba" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight" = "0x12ba12ba" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x000c06a1" + register "gpi13_routing" = "2" + register "gpi1_routing" = "2" + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x89" + register "pirqd_routing" = "0x87" + register "pirqe_routing" = "0x8b" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x8a" + register "pirqh_routing" = "0x86" + register "sata_ahci" = "1" + register "sata_port_map" = "0x21" + device pci 14.0 on # xHCI Controller + subsystemid 0x17aa 0x2210 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x17aa 0x2210 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 on # Management Engine KT + subsystemid 0x17aa 0x2210 + end + device pci 19.0 on # Intel Gigabit Ethernet Unsupported PCI device 8086:153a + subsystemid 0x17aa 0x2210 + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x17aa 0x2210 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x17aa 0x2210 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x17aa 0x2210 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x17aa 0x2210 + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x17aa 0x2210 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x17aa 0x2210 + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x17aa 0x2210 + chip ec/lenovo/pmh7 + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + device pnp ff.1 on # dummy + end + end + chip ec/lenovo/h8 # FIXME: has_keyboard_backlight, has_power_management_beeps, has_uwb + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "config0" = "0xa7" + register "config1" = "0x0d" + register "config2" = "0xa8" + register "config3" = "0xc4" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0x3c" + register "event7_enable" = "0x81" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x9d" + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x17aa 0x2210 + end + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x2210 + chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + device i2c 54 on + end + device i2c 55 on + end + device i2c 56 on + end + device i2c 57 on + end + device i2c 5c on + end + device i2c 5d on + end + device i2c 5e on + end + device i2c 5f on + end + end + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x17aa 0x2210 + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x2210 + end + device pci 03.0 on # Mini-HD audio Audio controller + subsystemid 0x17aa 0x2210 + end + end +end diff --git a/src/mainboard/lenovo/t540p/dsdt.asl b/src/mainboard/lenovo/t540p/dsdt.asl new file mode 100644 index 0000000..4838877 --- /dev/null +++ b/src/mainboard/lenovo/t540p/dsdt.asl @@ -0,0 +1,31 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define THINKPAD_EC_GPE 17 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/lynxpoint/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/lenovo/t540p/gma-mainboard.ads b/src/mainboard/lenovo/t540p/gma-mainboard.ads new file mode 100644 index 0000000..d7afe73 --- /dev/null +++ b/src/mainboard/lenovo/t540p/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t540p/gpio.c b/src/mainboard/lenovo/t540p/gpio.c new file mode 100644 index 0000000..a351508 --- /dev/null +++ b/src/mainboard/lenovo/t540p/gpio.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/t540p/hda_verb.c b/src/mainboard/lenovo/t540p/hda_verb.c new file mode 100644 index 0000000..8574e4e --- /dev/null +++ b/src/mainboard/lenovo/t540p/hda_verb.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x80862807, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x0, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x0, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x0, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t540p/mainboard.c b/src/mainboard/lenovo/t540p/mainboard.c new file mode 100644 index 0000000..3440a0a --- /dev/null +++ b/src/mainboard/lenovo/t540p/mainboard.c @@ -0,0 +1,17 @@ +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/lenovo/h8/h8.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +void h8_mainboard_init_dock(void) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/t540p/romstage.c b/src/mainboard/lenovo/t540p/romstage.c new file mode 100644 index 0000000..4ecf202 --- /dev/null +++ b/src/mainboard/lenovo/t540p/romstage.c @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry(void) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 0, /* mobile */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + /* note that SPD addresses are left-shifted by 1. */ + .spd_addresses = { 0xa0, 0, 0xa2, 0 }, + .ec_present = 1, + .gbe_enable = 1, + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, USB_OC_PIN_SKIP }, + { 1, USB_OC_PIN_SKIP }, + { 1, 1 }, + { 1, 1 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = rcba_config, + }; + + romstage_common(&romstage_params); +} diff --git a/src/mainboard/lenovo/t540p/smihandler.c b/src/mainboard/lenovo/t540p/smihandler.c new file mode 100644 index 0000000..9f5044a --- /dev/null +++ b/src/mainboard/lenovo/t540p/smihandler.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_ops.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +/* lynxpoint doesn't have gpi_route_interrupt, so add it */ +#define GPI_DISABLE 0x00 +#define GPI_IS_SMI 0x01 +#define GPI_IS_SCI 0x02 +#define GPI_IS_NMI 0x03 + +static void gpi_route_interrupt(u8 gpi, u8 mode) +{ + u32 gpi_rout; + + gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + gpi_rout &= ~(3 << (2 * gpi)); + gpi_rout |= ((mode & 3) << (2 * gpi)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, + * enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02ecde6999d1b5ca7741371273edd90297899fa0 Gerrit-Change-Number: 38204 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Elsen Gerrit-MessageType: newchange

7 11