March 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: [WIP] mainboard: Add Acer ES1-572
by Angel Pons (Code Review) March 1, 2020

March 1, 2020

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mainboard: Add Acer ES1-572 ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/38978/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38978/3//COMMIT_MSG@31 PS3, Line 31: UART 2 > The FSP has a UPD to enable these. Try using: […] Yes, I had issues with that before. Now it works. Also, I forgot to send this message yesterday. It's not really verbose, most of the fun stuff is done inside FSP anyway. -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Mar 2020 11:42:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/{cnl, apl, skl}: Make use of print_me_fw_version() from CSE...
by Sridhar Siricilla (Code Review) March 1, 2020

March 1, 2020

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39011 ) Change subject: soc/intel/{cnl, apl, skl}: Make use of print_me_fw_version() from CSE lib ...................................................................... soc/intel/{cnl, apl, skl}: Make use of print_me_fw_version() from CSE lib Remove print_me_version/dump_me_version from cnl/skl/apl and make changes to call print_me_version() which is defined in the CSE lib. TEST=Verified on hatch, soraka and bobba. Change-Id: I9b4dcb6ff85cce09b548cdec4cb490bd8e34297e Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/apollolake/cse.c M src/soc/intel/cannonlake/me.c M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/me.c 4 files changed, 8 insertions(+), 213 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/39011/1 diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 6ee1a15..2445289 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -36,9 +36,6 @@ #define READ_FILE_FLAG_EMULATED (1 << 2) #define READ_FILE_FLAG_HW (1 << 3) -#define MKHI_GROUP_ID_GEN 0xff -#define GET_FW_VERSION 0x02 - #define MCA_MAX_FILE_PATH_SIZE 64 #define FUSE_LOCK_FILE "/fpf/intel/SocCfgLock" @@ -180,59 +177,6 @@ return reg; } -static void dump_cse_version(void *unused) -{ - int res; - size_t reply_size; - struct mkhi_hdr msg; - struct version { - uint16_t minor; - uint16_t major; - uint16_t build; - uint16_t hotfix; - } __packed; - - struct fw_version_response { - struct mkhi_hdr hdr; - struct version code; - struct version nftp; - struct version fitc; - } __packed rsp; - - /* - * Print ME version only if UART debugging is enabled. Else, it takes - * ~0.6 second to talk to ME and get this information. - */ - if (!CONFIG(CONSOLE_SERIAL)) - return; - - msg.group_id = MKHI_GROUP_ID_GEN; - msg.command = GET_FW_VERSION; - - res = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); - - if (!res) { - printk(BIOS_ERR, "Failed to send HECI message.\n"); - return; - } - - reply_size = sizeof(rsp); - res = heci_receive(&rsp, &reply_size); - - if (!res) { - printk(BIOS_ERR, "Failed to receive HECI reply.\n"); - return; - } - - if (rsp.hdr.result != 0) { - printk(BIOS_ERR, "Failed to get ME version.\n"); - return; - } - - printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", rsp.code.major, - rsp.code.minor, rsp.code.hotfix, rsp.code.build); -} - static void dump_cse_state(void) { uint32_t fwsts1; @@ -289,4 +233,4 @@ } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, fpf_blown, NULL); -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, dump_cse_version, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, print_me_fw_version, NULL); diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index 3d3fcb8..ccacbe2 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -23,14 +23,6 @@ #include <soc/pci_devs.h> #include <stdint.h> -/* Miscellaneous constants */ -enum { - MKHI_GEN_GROUP_ID = 0xFF, - MKHI_GET_FW_VERSION = 0x02, - ME_OPMODE_NORMAL = 0x00, - ME_WSTATE_NORMAL = 0x05, -}; - /* Host Firmware Status Register 2 */ union me_hfsts2 { uint32_t raw; @@ -115,76 +107,6 @@ } __packed fields; }; -/* - * From reading the documentation, this should work for both WHL and CML - * platforms. Also, calling this function from dump_me_status() does not - * work, as the ME does not respond and the command times out. - */ -static void print_me_version(void *unused) -{ - struct version { - uint16_t minor; - uint16_t major; - uint16_t build; - uint16_t hotfix; - } __packed; - - struct fw_ver_resp { - struct mkhi_hdr hdr; - struct version code; - struct version rec; - struct version fitc; - } __packed; - - union me_hfsts1 hfsts1; - const struct mkhi_hdr fw_ver_msg = { - .group_id = MKHI_GEN_GROUP_ID, - .command = MKHI_GET_FW_VERSION, - }; - struct fw_ver_resp resp; - size_t resp_size = sizeof(resp); - - /* Ignore if UART debugging is disabled */ - if (!CONFIG(CONSOLE_SERIAL)) - return; - - if (!is_cse_enabled()) - return; - - hfsts1.data = me_read_config32(PCI_ME_HFSTS1); - - /* - * Prerequisites: - * 1) HFSTS1 Current Working State is Normal - * 2) HFSTS1 Current Operation Mode is Normal - * 3) It's after DRAM INIT DONE message (taken care of by calling it - * during ramstage - */ - if ((hfsts1.fields.working_state != ME_WSTATE_NORMAL) || - (hfsts1.fields.operation_mode != ME_OPMODE_NORMAL)) - goto fail; - - heci_reset(); - - if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADDR, - HECI_MKHI_ADDR)) - goto fail; - - if (!heci_receive(&resp, &resp_size)) - goto fail; - - if (resp.hdr.result) - goto fail; - - printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, - resp.code.minor, resp.code.hotfix, resp.code.build); - return; - -fail: - printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); -} -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); - void dump_me_status(void *unused) { union me_hfsts1 hfsts1; @@ -252,3 +174,4 @@ } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 332340f..2f581fb 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -192,10 +192,6 @@ } __packed fields; }; -#define MKHI_GEN_GROUP_ID 0xff - -#define MKHI_GET_FW_VERSION 0x02 - void intel_me_status(void); int send_global_reset(void); diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index b45234e..45a7c48 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -196,80 +196,6 @@ "M0 kernel load", }; -static void print_me_version(void *unused) -{ - struct version { - uint16_t minor; - uint16_t major; - uint16_t build; - uint16_t hotfix; - } __packed; - - struct fw_ver_resp { - struct mkhi_hdr hdr; - struct version code; - struct version rec; - struct version fitc; - } __packed; - - const struct mkhi_hdr fw_ver_msg = { - .group_id = MKHI_GEN_GROUP_ID, - .command = MKHI_GET_FW_VERSION, - }; - - struct fw_ver_resp resp; - size_t resp_size = sizeof(resp); - union me_hfsts1 hfs1; - - /* - * Print ME version only if UART debugging is enabled. Else, it takes ~1 - * second to talk to ME and get this information. - */ - if (!CONFIG(CONSOLE_SERIAL)) - return; - - if (!is_cse_enabled()) - return; - - hfs1.data = me_read_config32(PCI_ME_HFSTS1); - /* - * This command can be run only if: - * - Working state is normal and - * - Operation mode is normal. - */ - if ((hfs1.fields.working_state != ME_HFS_CWS_NORMAL) || - (hfs1.fields.operation_mode != ME_HFS_MODE_NORMAL)) - goto failed; - - /* - * It is important to do a heci_reset to ensure BIOS and ME are in sync - * before reading firmware version. - */ - heci_reset(); - - if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADDR, - HECI_MKHI_ADDR)) - goto failed; - - if (!heci_receive(&resp, &resp_size)) - goto failed; - - if (resp.hdr.result) - goto failed; - - printk(BIOS_DEBUG, "ME: Version : %d.%d.%d.%d\n", resp.code.major, - resp.code.minor, resp.code.hotfix, resp.code.build); - return; - -failed: - printk(BIOS_DEBUG, "ME: Version : Unavailable\n"); -} -/* - * This can't be put in intel_me_status because by the time control - * reaches there, ME doesn't respond to GET_FW_VERSION command. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); - void intel_me_status(void) { union me_hfsts1 hfs1; @@ -445,3 +371,9 @@ ret: return status; } + +/* + * This can't be put in intel_me_status because by the time control + * reaches there, ME doesn't respond to GET_FW_VERSION command. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/39011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b4dcb6ff85cce09b548cdec4cb490bd8e34297e Gerrit-Change-Number: 39011 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

2 13

Change in coreboot[master]: soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig
by Subrata Banik (Code Review) Feb. 29, 2020

Feb. 29, 2020

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39152 ) Change subject: soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig ...................................................................... soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig This change is mainly to control PlatformDebugConsent FSP UPD. PlatformDebugConsent is enabled if SOC_INTEL_<SOC>LAKE_DEBUG_CONSENT != 0. PlatformDebugConsent in FspmUpd.h has the details. TEST=Able to connect ITP/DCI with target system. Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 7 files changed, 25 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/39152/1 diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 15a5a31..b30b8c6 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -186,6 +186,17 @@ depends on FSP_USE_REPO default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd" +config SOC_INTEL_ICELAKE_DEBUG_CONSENT + int "Debug Consent for ICL" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + config ENABLE_DISPLAY_OVER_EXT_PCIE_GFX bool "Enable display over external PCIE GFX card" select ALWAYS_LOAD_OPROM diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 0687513..569160f 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -203,15 +203,6 @@ uint8_t PmTimerDisabled; - /* Desired platform debug type. */ - enum { - DebugConsent_Disabled, - DebugConsent_DCI_DBC, - DebugConsent_DCI, - DebugConsent_USB3_DBC, - DebugConsent_XDP, /* XDP/Mipi60 */ - DebugConsent_USB2_DBC, - } DebugConsent; /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 1f99604..8dd6bfd 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -87,7 +87,7 @@ /* Enable SMBus controller based on config */ m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ICELAKE_DEBUG_CONSENT; /* Vt-D config */ m_cfg->VtdDisable = 0; diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 79d74b4..c18752f 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -212,4 +212,15 @@ default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE +config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT + int "Debug Consent for TGL" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + endif diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 5442361..02855b1 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -169,17 +169,6 @@ */ uint32_t PrmrrSize; uint8_t PmTimerDisabled; - /* Desired platform debug type. */ - enum { - DebugConsent_Disabled, - DebugConsent_DCI_DBC, - DebugConsent_DCI, - DebugConsent_USB3_DBC, - DebugConsent_XDP, /* XDP/Mipi60 */ - DebugConsent_USB2_DBC, - DebugConsent_2WIRE_DCI, - DebugConsent_Manual, - } DebugConsent; /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index e88d809..e02eb6a 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -80,7 +80,7 @@ m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT; /* VT-d config */ m_cfg->VtdDisable = 0; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index ed6aa5a..d769615 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -109,7 +109,7 @@ /* Enable SMBus controller based on config */ m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT; /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; -- To view, visit https://review.coreboot.org/c/coreboot/+/39152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440 Gerrit-Change-Number: 39152 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/tigerlake: Add Jasper lake GPIO support
by Subrata Banik (Code Review) Feb. 29, 2020

Feb. 29, 2020

Subrata Banik has uploaded a new patch set (#10) to the change originally created by Maulik V Vaghela. ( https://review.coreboot.org/c/coreboot/+/39111 ) Change subject: soc/intel/tigerlake: Add Jasper lake GPIO support ...................................................................... soc/intel/tigerlake: Add Jasper lake GPIO support Add gpio definition for Jasper Lake gpio controller. Also created a separate file for JSL and TGL gpios along with separate ASL files for JSL. GPIO controller includes 4 gpio community and 10 groups. Patch adds definition for all gpio within community and groups Updated IRQ mapping for all gpios TEST=Check if jslrvp code is compiling Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Signed-off-by: Usha P <usha.p(a)intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/acpi/gpio.asl A src/soc/intel/tigerlake/acpi/gpio_jsl.asl A src/soc/intel/tigerlake/acpi/gpio_op.asl A src/soc/intel/tigerlake/acpi/gpio_tgl.asl M src/soc/intel/tigerlake/chip.h A src/soc/intel/tigerlake/gpio_jsl.c R src/soc/intel/tigerlake/gpio_tgl.c M src/soc/intel/tigerlake/include/soc/gpio.h M src/soc/intel/tigerlake/include/soc/gpio_defs.h A src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h A src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h M src/soc/intel/tigerlake/include/soc/pmc.h 14 files changed, 1,634 insertions(+), 520 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/39111/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/39111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Gerrit-Change-Number: 39111 Gerrit-PatchSet: 10 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sooraj Govindan <sooraj.govindan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: [WIP] mainboard: Add Acer ES1-572
by Benjamin Doron (Code Review) Feb. 29, 2020

Feb. 29, 2020

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mainboard: Add Acer ES1-572 ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/38978/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38978/3//COMMIT_MSG@31 PS3, Line 31: UART 2 > The FSP has a UPD to enable these. Try using: […] Done. I guess if it's too verbose, you can disable it if you want? -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Mar 2020 01:20:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [WIP] mainboard: Add Acer ES1-572
by Angel Pons (Code Review) Feb. 29, 2020

Feb. 29, 2020

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38978 to look at the new patch set (#4). Change subject: [WIP] mainboard: Add Acer ES1-572 ...................................................................... [WIP] mainboard: Add Acer ES1-572 Both the Acer Aspire ES1-572 and the Acer Extensa 2540 use the same mainboard. (Compal LA-E061P) Tested and working: - Intel Core i3-6006U with KabyLakeFspBinPkg - Both SO-DIMM DDR4 slots - Ethernet - USB 3.0 port - HDMI with libgfxinit - SATA with an SSD - Loading Linux with SeaBIOS and tianocore - Power button soldered onto the board's debug pads. - UART 2 to get yelled at - S3 suspend and resume, for some reason Not working or need testing: - Wi-Fi card. Probably fixed with correct PCIe settings. - Fan is pretending to be a leaf blower. - All EC-related stuffs. The thing is an ENE KB9022, similar to KB9012. - Audio is missing configuration. - Internal eDP LCD. I think I have the cable somewhere. - Lid. It was brutally damaged, even though the LCD managed to survive. - Battery. I have it somewhere. - Keyboard and touchpad. - Card reader. Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A acer_a_thing.defconfig A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/es1-572/Kconfig A src/mainboard/acer/es1-572/Kconfig.name A src/mainboard/acer/es1-572/Makefile.inc A src/mainboard/acer/es1-572/acpi/ec.asl A src/mainboard/acer/es1-572/acpi/mainboard.asl A src/mainboard/acer/es1-572/acpi/superio.asl A src/mainboard/acer/es1-572/board_info.txt A src/mainboard/acer/es1-572/devicetree.cb A src/mainboard/acer/es1-572/dsdt.asl A src/mainboard/acer/es1-572/gma-mainboard.ads A src/mainboard/acer/es1-572/gpio.h A src/mainboard/acer/es1-572/hda_verb.c A src/mainboard/acer/es1-572/ramstage.c A src/mainboard/acer/es1-572/romstage.c 17 files changed, 1,514 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/38978/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: newpatchset

1 0